build/xilinx/platform: Add XilinxUS/USPPlatform.

litex/build/xilinx/__init__.py

@@ -1,2 +1,14 @@
-from litex.build.xilinx.platform import XilinxPlatform, XilinxSpartan6Platform, Xilinx7SeriesPlatform
+# Platforms.
-from litex.build.xilinx.programmer import UrJTAG, XC3SProg, FpgaProg, VivadoProgrammer, iMPACT, Adept
+from litex.build.xilinx.platform import XilinxPlatform
+from litex.build.xilinx.platform import XilinxSpartan6Platform
+from litex.build.xilinx.platform import Xilinx7SeriesPlatform
+from litex.build.xilinx.platform import XilinxUSPlatform
+from litex.build.xilinx.platform import XilinxUSPPlatform
+
+# Programmers.
+from litex.build.xilinx.programmer import UrJTAG
+from litex.build.xilinx.programmer import XC3SProg
+from litex.build.xilinx.programmer import FpgaProg
+from litex.build.xilinx.programmer import VivadoProgrammer
+from litex.build.xilinx.programmer import iMPACT
+from litex.build.xilinx.programmer import Adept

litex/build/xilinx/platform.py

@@ -17,8 +17,10 @@ class XilinxPlatform(GenericPlatform):
     bitstream_ext = ".bit"
 
     _supported_toolchains = {
-        "7series"  : ["vivado", "f4pga", "yosys+nextpnr"],
+        "spartan6"    : ["ise"],
-        "spartan6" : ["ise"],
+        "7series"     : ["vivado", "f4pga", "yosys+nextpnr"],
+        "ultrascale"  : ["vivado"],
+        "ultrascale+" : ["vivado"],
     }
 
     def __init__(self, *args, toolchain="ise", **kwargs):
@@ -127,13 +129,22 @@ class XilinxPlatform(GenericPlatform):
         else:
             return dict()
 
-# Xilinx7SeriesPlatform -----------------------------------------------------------------------------
-
-class Xilinx7SeriesPlatform(XilinxPlatform):
-    device_family = "7series"
-
 # XilinxSpartan6Platform ---------------------------------------------------------------------------
 
 class XilinxSpartan6Platform(XilinxPlatform):
     device_family = "spartan6"
 
+# Xilinx7SeriesPlatform ----------------------------------------------------------------------------
+
+class Xilinx7SeriesPlatform(XilinxPlatform):
+    device_family = "7series"
+
+# XilinxUSPlatform ---------------------------------------------------------------------------------
+
+class XilinxUSPlatform(XilinxPlatform):
+    device_family = "ultrascale"
+
+# XilinxUSPPlatform --------------------------------------------------------------------------------
+
+class XilinxUSPPlatform(XilinxPlatform):
+    device_family = "ultrascale+"