merge litesata
This commit is contained in:
Florent Kermarrec
commit
b6358be0a1
|
|
@ -0,0 +1,3 @@
|
|||
__pycache__
|
||||
*.pyc
|
||||
*.vcd
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
Unless otherwise noted, LiteSATA is copyright (C) 2014-2015 The University of
|
||||
Hong Kong
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
|
||||
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
|
||||
Other authors retain ownership of their contributions. If a submission can
|
||||
reasonably be considered independently copyrightable, it's yours and we
|
||||
encourage you to claim it with appropriate copyright notices. This submission
|
||||
then falls under the "otherwise noted" category. All submissions are strongly
|
||||
encouraged to use the two-clause BSD license reproduced above.
|
||||
|
|
@ -0,0 +1,173 @@
|
|||
__ _ __ _______ _________
|
||||
/ / (_) /____ / __/ _ /_ __/ _ |
|
||||
/ /__/ / __/ -_)\ \/ __ |/ / / __ |
|
||||
/____/_/\__/\__/___/_/ |_/_/ /_/ |_|
|
||||
|
||||
Copyright 2014-2015 The University of Hong Kong
|
||||
|
||||
A small footprint and configurable SATA core
|
||||
developed for HKU by M-Labs Ltd & EnjoyDigital
|
||||
|
||||
[> Doc
|
||||
---------
|
||||
HTML : www.enjoy-digital.fr/litex/litesata/
|
||||
PDF : www.enjoy-digital.fr/litex/litesata.pdf
|
||||
|
||||
[> Intro
|
||||
---------
|
||||
LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
|
||||
|
||||
LiteSATA is part of LiteX libraries whose aims are to lower entry level of complex
|
||||
FPGA cores by providing simple, elegant and efficient implementations of
|
||||
components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
|
||||
|
||||
The core uses simple and specific streaming buses and will provides in the future
|
||||
adapters to use standardized AXI or Avalon-ST streaming buses.
|
||||
|
||||
Since Python is used to describe the HDL, the core is highly and easily
|
||||
configurable.
|
||||
|
||||
The synthetizable BIST can be used as a starting point to integrate SATA in
|
||||
your own SoC.
|
||||
|
||||
LiteSATA uses technologies developed in partnership with M-Labs Ltd:
|
||||
- Migen enables generating HDL with Python in an efficient way.
|
||||
- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
|
||||
|
||||
LiteSATA can be used as a Migen/MiSoC library (by simply installing it
|
||||
with the provided setup.py) or can be integrated with your standard design flow
|
||||
by generating the verilog rtl that you will use as a standard core.
|
||||
|
||||
[> Features
|
||||
-----------
|
||||
PHY:
|
||||
- OOB, COMWAKE, COMINIT
|
||||
- ALIGN inserter/remover and bytes alignment on K28.5
|
||||
- 8B/10B encoding/decoding in transceiver
|
||||
- Errors detection and reporting
|
||||
- 32 bits interface
|
||||
- 1.5/3.0/6.0GBps supported speeds (respectively 37.5/75/150MHz system clk)
|
||||
Core:
|
||||
Link:
|
||||
- CONT inserter/remover
|
||||
- Scrambling/Descrambling of data
|
||||
- CRC inserter/checker
|
||||
- HOLD insertion/detection
|
||||
- Errors detection and reporting
|
||||
Transport/Command:
|
||||
- Easy to use user interfaces (Can be used with or without CPU)
|
||||
- 48 bits sector addressing
|
||||
- 3 supported commands: READ_DMA(_EXT), WRITE_DMA(_EXT), IDENTIFY_DEVICE
|
||||
- Errors detection and reporting
|
||||
|
||||
Frontend:
|
||||
- Configurable crossbar (simply use core.crossbar.get_port() to add a new port!)
|
||||
- Ports arbitration transparent to the user
|
||||
- Synthetizable BIST
|
||||
|
||||
[> Possibles improvements
|
||||
-------------------------
|
||||
- add standardized interfaces (AXI, Avalon-ST)
|
||||
- add NCQ support
|
||||
- add AES hardware encryption
|
||||
- add on-the-flow compression/decompression
|
||||
- add support for Altera PHYs.
|
||||
- add support for Lattice PHYs.
|
||||
- add support for Xilinx 7-Series GTP/GTH (currently only 7-Series GTX are
|
||||
supported)
|
||||
- add Zynq Linux drivers.
|
||||
- ... See below Support and consulting :)
|
||||
|
||||
If you want to support these features, please contact us at florent [AT]
|
||||
enjoy-digital.fr. You can also contact our partner on the public mailing list
|
||||
devel [AT] lists.m-labs.hk.
|
||||
|
||||
|
||||
[> Getting started
|
||||
------------------
|
||||
1. Install Python3 and your vendor's software
|
||||
|
||||
2. Obtain Migen and install it:
|
||||
git clone https://github.com/m-labs/migen
|
||||
cd migen
|
||||
python3 setup.py install
|
||||
cd ..
|
||||
|
||||
Note: in case you have issues with Migen, please retry
|
||||
with our fork at:
|
||||
https://github.com/enjoy-digital/misoc
|
||||
until new features are merged.
|
||||
|
||||
3. Obtain LiteScope and install it:
|
||||
git clone https://github.com/enjoy-digital/litescope
|
||||
cd litescope
|
||||
python3 setup.py install
|
||||
cd ..
|
||||
|
||||
4. Obtain LiteSATA
|
||||
git clone https://github.com/enjoy-digital/litesata
|
||||
|
||||
5. Build and load BIST design (only for KC705 for now):
|
||||
python3 make.py all (-s BISTSoCDevel to add LiteScopeLA)
|
||||
|
||||
6. Test design (only for KC705 for now):
|
||||
go to ./test directory and run:
|
||||
change com port in config.py to your com port
|
||||
python3 bist.py
|
||||
|
||||
7. Visualize Link Layer transactions (if BISTSoCDevel):
|
||||
go to ./test directory and run:
|
||||
python3 test_la.py [your_cond]
|
||||
your_cond can be wr_cmd, id_cmd, rd_resp, ...
|
||||
(open test_la.py to see all conditions or add yours)
|
||||
|
||||
8. If you only want to build the core and use it with your
|
||||
regular design flow:
|
||||
python3 make.py -t core build-core
|
||||
|
||||
[> Simulations:
|
||||
Simulations are available in ./lib/sata/test:
|
||||
- crc_tb
|
||||
- scrambler_tb
|
||||
- phy_datapath_tb
|
||||
- link_tb
|
||||
- command_tb
|
||||
- bist_tb
|
||||
hdd.py is a simplified HDD model implementing all SATA layers.
|
||||
To run a simulation, move to ./lib/sata/test and run:
|
||||
make simulation_name
|
||||
|
||||
[> Tests :
|
||||
A synthetizable BIST is provided and can be controlled with ./test/bist.py
|
||||
By using LiteScope and the provided ./test/test_link.py example you are able to
|
||||
visualize the internal logic of the design and even inject the captured data in
|
||||
the HDD model!
|
||||
|
||||
[> License
|
||||
-----------
|
||||
LiteSATA is released under the very permissive two-clause BSD license. Under the
|
||||
terms of this license, you are authorized to use LiteSATA for closed-source
|
||||
proprietary designs.
|
||||
Even though we do not require you to do so, those things are awesome, so please
|
||||
do them if possible:
|
||||
- tell us that you are using LiteSATA
|
||||
- cite LiteSATA in publications related to research it has helped
|
||||
- send us feedback and suggestions for improvements
|
||||
- send us bug reports when something goes wrong
|
||||
- send us the modifications and improvements you have done to LiteSATA.
|
||||
|
||||
[> Support and consulting
|
||||
--------------------------
|
||||
We love open-source hardware and like sharing our designs with others.
|
||||
|
||||
LiteSATA is developed and maintained by EnjoyDigital.
|
||||
|
||||
If you would like to know more about LiteSATA or if you are already a happy user
|
||||
and would like to extend it for your needs, EnjoyDigital can provide standard
|
||||
commercial support as well as consulting services.
|
||||
|
||||
So feel free to contact us, we'd love to work with you! (and eventually shorten
|
||||
the list of the possible improvements :)
|
||||
|
||||
[> Contact
|
||||
E-mail: florent [AT] enjoy-digital.fr
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
*.diff
|
||||
*.pyc
|
||||
*~
|
||||
*.bc
|
||||
*.md
|
||||
|
||||
# Ignore generated files
|
||||
build/
|
||||
|
|
@ -0,0 +1,157 @@
|
|||
# Makefile for Sphinx documentation
|
||||
#
|
||||
|
||||
# You can set these variables from the command line.
|
||||
SPHINXOPTS =
|
||||
SPHINXBUILD = sphinx-build
|
||||
PAPER =
|
||||
BUILDDIR = build
|
||||
|
||||
# User-friendly check for sphinx-build
|
||||
ifeq ($(shell which $(SPHINXBUILD) >/dev/null 2>&1; echo $$?), 1)
|
||||
$(error The '$(SPHINXBUILD)' command was not found. Make sure you have Sphinx installed, then set the SPHINXBUILD environment variable to point to the full path of the '$(SPHINXBUILD)' executable. Alternatively you can add the directory with the executable to your PATH. If you don't have Sphinx installed, grab it from http://sphinx-doc.org/)
|
||||
endif
|
||||
|
||||
# Internal variables.
|
||||
PAPEROPT_a4 = -D latex_paper_size=a4
|
||||
PAPEROPT_letter = -D latex_paper_size=letter
|
||||
ALLSPHINXOPTS = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) source
|
||||
# the i18n builder cannot share the environment and doctrees with the others
|
||||
I18NSPHINXOPTS = $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) source
|
||||
|
||||
.PHONY: help clean html dirhtml singlehtml pickle json htmlhelp qthelp devhelp epub latex latexpdf text man changes linkcheck doctest gettext
|
||||
|
||||
help:
|
||||
@echo "Please use \`make <target>' where <target> is one of"
|
||||
@echo " html to make standalone HTML files"
|
||||
@echo " dirhtml to make HTML files named index.html in directories"
|
||||
@echo " singlehtml to make a single large HTML file"
|
||||
@echo " pickle to make pickle files"
|
||||
@echo " json to make JSON files"
|
||||
@echo " htmlhelp to make HTML files and a HTML help project"
|
||||
@echo " epub to make an epub"
|
||||
@echo " latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter"
|
||||
@echo " latexpdf to make LaTeX files and run them through pdflatex"
|
||||
@echo " latexpdfja to make LaTeX files and run them through platex/dvipdfmx"
|
||||
@echo " text to make text files"
|
||||
@echo " man to make manual pages"
|
||||
@echo " texinfo to make Texinfo files"
|
||||
@echo " info to make Texinfo files and run them through makeinfo"
|
||||
@echo " gettext to make PO message catalogs"
|
||||
@echo " changes to make an overview of all changed/added/deprecated items"
|
||||
@echo " xml to make Docutils-native XML files"
|
||||
@echo " pseudoxml to make pseudoxml-XML files for display purposes"
|
||||
@echo " linkcheck to check all external links for integrity"
|
||||
@echo " doctest to run all doctests embedded in the documentation (if enabled)"
|
||||
|
||||
clean:
|
||||
rm -rf $(BUILDDIR)/*
|
||||
|
||||
html:
|
||||
$(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html
|
||||
@echo
|
||||
@echo "Build finished. The HTML pages are in $(BUILDDIR)/html."
|
||||
|
||||
dirhtml:
|
||||
$(SPHINXBUILD) -b dirhtml $(ALLSPHINXOPTS) $(BUILDDIR)/dirhtml
|
||||
@echo
|
||||
@echo "Build finished. The HTML pages are in $(BUILDDIR)/dirhtml."
|
||||
|
||||
singlehtml:
|
||||
$(SPHINXBUILD) -b singlehtml $(ALLSPHINXOPTS) $(BUILDDIR)/singlehtml
|
||||
@echo
|
||||
@echo "Build finished. The HTML page is in $(BUILDDIR)/singlehtml."
|
||||
|
||||
pickle:
|
||||
$(SPHINXBUILD) -b pickle $(ALLSPHINXOPTS) $(BUILDDIR)/pickle
|
||||
@echo
|
||||
@echo "Build finished; now you can process the pickle files."
|
||||
|
||||
json:
|
||||
$(SPHINXBUILD) -b json $(ALLSPHINXOPTS) $(BUILDDIR)/json
|
||||
@echo
|
||||
@echo "Build finished; now you can process the JSON files."
|
||||
|
||||
htmlhelp:
|
||||
$(SPHINXBUILD) -b htmlhelp $(ALLSPHINXOPTS) $(BUILDDIR)/htmlhelp
|
||||
@echo
|
||||
@echo "Build finished; now you can run HTML Help Workshop with the" \
|
||||
".hhp project file in $(BUILDDIR)/htmlhelp."
|
||||
|
||||
epub:
|
||||
$(SPHINXBUILD) -b epub $(ALLSPHINXOPTS) $(BUILDDIR)/epub
|
||||
@echo
|
||||
@echo "Build finished. The epub file is in $(BUILDDIR)/epub."
|
||||
|
||||
latex:
|
||||
$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
|
||||
@echo
|
||||
@echo "Build finished; the LaTeX files are in $(BUILDDIR)/latex."
|
||||
@echo "Run \`make' in that directory to run these through (pdf)latex" \
|
||||
"(use \`make latexpdf' here to do that automatically)."
|
||||
|
||||
latexpdf:
|
||||
$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
|
||||
@echo "Running LaTeX files through pdflatex..."
|
||||
$(MAKE) -C $(BUILDDIR)/latex all-pdf
|
||||
@echo "pdflatex finished; the PDF files are in $(BUILDDIR)/latex."
|
||||
|
||||
latexpdfja:
|
||||
$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
|
||||
@echo "Running LaTeX files through platex and dvipdfmx..."
|
||||
$(MAKE) -C $(BUILDDIR)/latex all-pdf-ja
|
||||
@echo "pdflatex finished; the PDF files are in $(BUILDDIR)/latex."
|
||||
|
||||
text:
|
||||
$(SPHINXBUILD) -b text $(ALLSPHINXOPTS) $(BUILDDIR)/text
|
||||
@echo
|
||||
@echo "Build finished. The text files are in $(BUILDDIR)/text."
|
||||
|
||||
man:
|
||||
$(SPHINXBUILD) -b man $(ALLSPHINXOPTS) $(BUILDDIR)/man
|
||||
@echo
|
||||
@echo "Build finished. The manual pages are in $(BUILDDIR)/man."
|
||||
|
||||
texinfo:
|
||||
$(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo
|
||||
@echo
|
||||
@echo "Build finished. The Texinfo files are in $(BUILDDIR)/texinfo."
|
||||
@echo "Run \`make' in that directory to run these through makeinfo" \
|
||||
"(use \`make info' here to do that automatically)."
|
||||
|
||||
info:
|
||||
$(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo
|
||||
@echo "Running Texinfo files through makeinfo..."
|
||||
make -C $(BUILDDIR)/texinfo info
|
||||
@echo "makeinfo finished; the Info files are in $(BUILDDIR)/texinfo."
|
||||
|
||||
gettext:
|
||||
$(SPHINXBUILD) -b gettext $(I18NSPHINXOPTS) $(BUILDDIR)/locale
|
||||
@echo
|
||||
@echo "Build finished. The message catalogs are in $(BUILDDIR)/locale."
|
||||
|
||||
changes:
|
||||
$(SPHINXBUILD) -b changes $(ALLSPHINXOPTS) $(BUILDDIR)/changes
|
||||
@echo
|
||||
@echo "The overview file is in $(BUILDDIR)/changes."
|
||||
|
||||
linkcheck:
|
||||
$(SPHINXBUILD) -b linkcheck $(ALLSPHINXOPTS) $(BUILDDIR)/linkcheck
|
||||
@echo
|
||||
@echo "Link check complete; look for any errors in the above output " \
|
||||
"or in $(BUILDDIR)/linkcheck/output.txt."
|
||||
|
||||
doctest:
|
||||
$(SPHINXBUILD) -b doctest $(ALLSPHINXOPTS) $(BUILDDIR)/doctest
|
||||
@echo "Testing of doctests in the sources finished, look at the " \
|
||||
"results in $(BUILDDIR)/doctest/output.txt."
|
||||
|
||||
xml:
|
||||
$(SPHINXBUILD) -b xml $(ALLSPHINXOPTS) $(BUILDDIR)/xml
|
||||
@echo
|
||||
@echo "Build finished. The XML files are in $(BUILDDIR)/xml."
|
||||
|
||||
pseudoxml:
|
||||
$(SPHINXBUILD) -b pseudoxml $(ALLSPHINXOPTS) $(BUILDDIR)/pseudoxml
|
||||
@echo
|
||||
@echo "Build finished. The pseudo-XML files are in $(BUILDDIR)/pseudoxml."
|
||||
|
|
@ -0,0 +1,220 @@
|
|||
@ECHO OFF
|
||||
|
||||
REM Command file for Sphinx documentation
|
||||
|
||||
if "%SPHINXBUILD%" == "" (
|
||||
set SPHINXBUILD=sphinx-build
|
||||
)
|
||||
set BUILDDIR=build
|
||||
set ALLSPHINXOPTS=-d %BUILDDIR%/doctrees %SPHINXOPTS% source
|
||||
set I18NSPHINXOPTS=%SPHINXOPTS% source
|
||||
if NOT "%PAPER%" == "" (
|
||||
set ALLSPHINXOPTS=-D latex_paper_size=%PAPER% %ALLSPHINXOPTS%
|
||||
set I18NSPHINXOPTS=-D latex_paper_size=%PAPER% %I18NSPHINXOPTS%
|
||||
)
|
||||
|
||||
if "%1" == "" goto help
|
||||
|
||||
if "%1" == "help" (
|
||||
:help
|
||||
echo.Please use `make ^<target^>` where ^<target^> is one of
|
||||
echo. html to make standalone HTML files
|
||||
echo. dirhtml to make HTML files named index.html in directories
|
||||
echo. singlehtml to make a single large HTML file
|
||||
echo. pickle to make pickle files
|
||||
echo. json to make JSON files
|
||||
echo. htmlhelp to make HTML files and a HTML help project
|
||||
echo. epub to make an epub
|
||||
echo. latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter
|
||||
echo. text to make text files
|
||||
echo. man to make manual pages
|
||||
echo. texinfo to make Texinfo files
|
||||
echo. gettext to make PO message catalogs
|
||||
echo. changes to make an overview over all changed/added/deprecated items
|
||||
echo. xml to make Docutils-native XML files
|
||||
echo. pseudoxml to make pseudoxml-XML files for display purposes
|
||||
echo. linkcheck to check all external links for integrity
|
||||
echo. doctest to run all doctests embedded in the documentation if enabled
|
||||
goto end
|
||||
)
|
||||
|
||||
if "%1" == "clean" (
|
||||
for /d %%i in (%BUILDDIR%\*) do rmdir /q /s %%i
|
||||
del /q /s %BUILDDIR%\*
|
||||
goto end
|
||||
)
|
||||
|
||||
|
||||
%SPHINXBUILD% 2> nul
|
||||
if errorlevel 9009 (
|
||||
echo.
|
||||
echo.The 'sphinx-build' command was not found. Make sure you have Sphinx
|
||||
echo.installed, then set the SPHINXBUILD environment variable to point
|
||||
echo.to the full path of the 'sphinx-build' executable. Alternatively you
|
||||
echo.may add the Sphinx directory to PATH.
|
||||
echo.
|
||||
echo.If you don't have Sphinx installed, grab it from
|
||||
echo.http://sphinx-doc.org/
|
||||
exit /b 1
|
||||
)
|
||||
|
||||
if "%1" == "html" (
|
||||
%SPHINXBUILD% -b html %ALLSPHINXOPTS% %BUILDDIR%/html
|
||||
if errorlevel 1 exit /b 1
|
||||
echo.
|
||||
echo.Build finished. The HTML pages are in %BUILDDIR%/html.
|
||||
goto end
|
||||
)
|
||||
|
||||
if "%1" == "dirhtml" (
|
||||
%SPHINXBUILD% -b dirhtml %ALLSPHINXOPTS% %BUILDDIR%/dirhtml
|
||||
if errorlevel 1 exit /b 1
|
||||
echo.
|
||||
echo.Build finished. The HTML pages are in %BUILDDIR%/dirhtml.
|
||||
goto end
|
||||
)
|
||||
|
||||
if "%1" == "singlehtml" (
|
||||
%SPHINXBUILD% -b singlehtml %ALLSPHINXOPTS% %BUILDDIR%/singlehtml
|
||||
if errorlevel 1 exit /b 1
|
||||
echo.
|
||||
echo.Build finished. The HTML pages are in %BUILDDIR%/singlehtml.
|
||||
goto end
|
||||
)
|
||||
|
||||
if "%1" == "pickle" (
|
||||
%SPHINXBUILD% -b pickle %ALLSPHINXOPTS% %BUILDDIR%/pickle
|
||||
if errorlevel 1 exit /b 1
|
||||
echo.
|
||||
echo.Build finished; now you can process the pickle files.
|
||||
goto end
|
||||
)
|
||||
|
||||
if "%1" == "json" (
|
||||
%SPHINXBUILD% -b json %ALLSPHINXOPTS% %BUILDDIR%/json
|
||||
if errorlevel 1 exit /b 1
|
||||
echo.
|
||||
echo.Build finished; now you can process the JSON files.
|
||||
goto end
|
||||
)
|
||||
|
||||
if "%1" == "htmlhelp" (
|
||||
%SPHINXBUILD% -b htmlhelp %ALLSPHINXOPTS% %BUILDDIR%/htmlhelp
|
||||
if errorlevel 1 exit /b 1
|
||||
echo.
|
||||
echo.Build finished; now you can run HTML Help Workshop with the ^
|
||||
.hhp project file in %BUILDDIR%/htmlhelp.
|
||||
goto end
|
||||
)
|
||||
|
||||
if "%1" == "epub" (
|
||||
%SPHINXBUILD% -b epub %ALLSPHINXOPTS% %BUILDDIR%/epub
|
||||
if errorlevel 1 exit /b 1
|
||||
echo.
|
||||
echo.Build finished. The epub file is in %BUILDDIR%/epub.
|
||||
goto end
|
||||
)
|
||||
|
||||
if "%1" == "latex" (
|
||||
%SPHINXBUILD% -b latex %ALLSPHINXOPTS% %BUILDDIR%/latex
|
||||
if errorlevel 1 exit /b 1
|
||||
echo.
|
||||
echo.Build finished; the LaTeX files are in %BUILDDIR%/latex.
|
||||
goto end
|
||||
)
|
||||
|
||||
if "%1" == "latexpdf" (
|
||||
%SPHINXBUILD% -b latex %ALLSPHINXOPTS% %BUILDDIR%/latex
|
||||
cd %BUILDDIR%/latex
|
||||
make all-pdf
|
||||
cd %BUILDDIR%/..
|
||||
echo.
|
||||
echo.Build finished; the PDF files are in %BUILDDIR%/latex.
|
||||
goto end
|
||||
)
|
||||
|
||||
if "%1" == "latexpdfja" (
|
||||
%SPHINXBUILD% -b latex %ALLSPHINXOPTS% %BUILDDIR%/latex
|
||||
cd %BUILDDIR%/latex
|
||||
make all-pdf-ja
|
||||
cd %BUILDDIR%/..
|
||||
echo.
|
||||
echo.Build finished; the PDF files are in %BUILDDIR%/latex.
|
||||
goto end
|
||||
)
|
||||
|
||||
if "%1" == "text" (
|
||||
%SPHINXBUILD% -b text %ALLSPHINXOPTS% %BUILDDIR%/text
|
||||
if errorlevel 1 exit /b 1
|
||||
echo.
|
||||
echo.Build finished. The text files are in %BUILDDIR%/text.
|
||||
goto end
|
||||
)
|
||||
|
||||
if "%1" == "man" (
|
||||
%SPHINXBUILD% -b man %ALLSPHINXOPTS% %BUILDDIR%/man
|
||||
if errorlevel 1 exit /b 1
|
||||
echo.
|
||||
echo.Build finished. The manual pages are in %BUILDDIR%/man.
|
||||
goto end
|
||||
)
|
||||
|
||||
if "%1" == "texinfo" (
|
||||
%SPHINXBUILD% -b texinfo %ALLSPHINXOPTS% %BUILDDIR%/texinfo
|
||||
if errorlevel 1 exit /b 1
|
||||
echo.
|
||||
echo.Build finished. The Texinfo files are in %BUILDDIR%/texinfo.
|
||||
goto end
|
||||
)
|
||||
|
||||
if "%1" == "gettext" (
|
||||
%SPHINXBUILD% -b gettext %I18NSPHINXOPTS% %BUILDDIR%/locale
|
||||
if errorlevel 1 exit /b 1
|
||||
echo.
|
||||
echo.Build finished. The message catalogs are in %BUILDDIR%/locale.
|
||||
goto end
|
||||
)
|
||||
|
||||
if "%1" == "changes" (
|
||||
%SPHINXBUILD% -b changes %ALLSPHINXOPTS% %BUILDDIR%/changes
|
||||
if errorlevel 1 exit /b 1
|
||||
echo.
|
||||
echo.The overview file is in %BUILDDIR%/changes.
|
||||
goto end
|
||||
)
|
||||
|
||||
if "%1" == "linkcheck" (
|
||||
%SPHINXBUILD% -b linkcheck %ALLSPHINXOPTS% %BUILDDIR%/linkcheck
|
||||
if errorlevel 1 exit /b 1
|
||||
echo.
|
||||
echo.Link check complete; look for any errors in the above output ^
|
||||
or in %BUILDDIR%/linkcheck/output.txt.
|
||||
goto end
|
||||
)
|
||||
|
||||
if "%1" == "doctest" (
|
||||
%SPHINXBUILD% -b doctest %ALLSPHINXOPTS% %BUILDDIR%/doctest
|
||||
if errorlevel 1 exit /b 1
|
||||
echo.
|
||||
echo.Testing of doctests in the sources finished, look at the ^
|
||||
results in %BUILDDIR%/doctest/output.txt.
|
||||
goto end
|
||||
)
|
||||
|
||||
if "%1" == "xml" (
|
||||
%SPHINXBUILD% -b xml %ALLSPHINXOPTS% %BUILDDIR%/xml
|
||||
if errorlevel 1 exit /b 1
|
||||
echo.
|
||||
echo.Build finished. The XML files are in %BUILDDIR%/xml.
|
||||
goto end
|
||||
)
|
||||
|
||||
if "%1" == "pseudoxml" (
|
||||
%SPHINXBUILD% -b pseudoxml %ALLSPHINXOPTS% %BUILDDIR%/pseudoxml
|
||||
if errorlevel 1 exit /b 1
|
||||
echo.
|
||||
echo.Build finished. The pseudo-XML files are in %BUILDDIR%/pseudoxml.
|
||||
goto end
|
||||
)
|
||||
|
||||
:end
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 29 KiB |
|
|
@ -0,0 +1,240 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!-- Created with Inkscape (http://www.inkscape.org/) -->
|
||||
|
||||
<svg
|
||||
xmlns:dc="http://purl.org/dc/elements/1.1/"
|
||||
xmlns:cc="http://creativecommons.org/ns#"
|
||||
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
|
||||
xmlns:svg="http://www.w3.org/2000/svg"
|
||||
xmlns="http://www.w3.org/2000/svg"
|
||||
xmlns:xlink="http://www.w3.org/1999/xlink"
|
||||
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
|
||||
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
|
||||
width="210mm"
|
||||
height="297mm"
|
||||
id="svg2"
|
||||
version="1.1"
|
||||
inkscape:version="0.48.4 r9939"
|
||||
sodipodi:docname="LiteSATA_logo_full.svg">
|
||||
<defs
|
||||
id="defs4">
|
||||
<linearGradient
|
||||
gradientTransform="matrix(1,0,0,1.1424088,0,-67.150429)"
|
||||
gradientUnits="userSpaceOnUse"
|
||||
y2="471.54514"
|
||||
x2="289.73526"
|
||||
y1="471.54514"
|
||||
x1="242.87946"
|
||||
id="linearGradient6099"
|
||||
xlink:href="#linearGradient6093"
|
||||
inkscape:collect="always" />
|
||||
<linearGradient
|
||||
id="linearGradient6093">
|
||||
<stop
|
||||
id="stop6095"
|
||||
offset="0"
|
||||
style="stop-color:#2ca22c;stop-opacity:0;" />
|
||||
<stop
|
||||
id="stop6097"
|
||||
offset="1"
|
||||
style="stop-color:#2ca22c;stop-opacity:1;" />
|
||||
</linearGradient>
|
||||
<linearGradient
|
||||
y2="204.03999"
|
||||
x2="252.2"
|
||||
y1="-22.384001"
|
||||
x1="150.95"
|
||||
gradientTransform="matrix(0.24477,0,0,0.24477,280.71427,440.33237)"
|
||||
gradientUnits="userSpaceOnUse"
|
||||
id="linearGradient3349"
|
||||
xlink:href="#a"
|
||||
inkscape:collect="always" />
|
||||
<linearGradient
|
||||
x1="200.5"
|
||||
x2="200.5"
|
||||
y1="13.899"
|
||||
gradientUnits="userSpaceOnUse"
|
||||
y2="150.32001"
|
||||
id="a">
|
||||
<stop
|
||||
id="stop7"
|
||||
offset=".1374"
|
||||
style="stop-color:#fff" />
|
||||
<stop
|
||||
id="stop9"
|
||||
offset="1"
|
||||
style="stop-color:#509e10;stop-opacity:1;" />
|
||||
</linearGradient>
|
||||
</defs>
|
||||
<sodipodi:namedview
|
||||
id="base"
|
||||
pagecolor="#ffffff"
|
||||
bordercolor="#666666"
|
||||
borderopacity="1.0"
|
||||
inkscape:pageopacity="0.0"
|
||||
inkscape:pageshadow="2"
|
||||
inkscape:zoom="0.70710678"
|
||||
inkscape:cx="309.79428"
|
||||
inkscape:cy="549.37114"
|
||||
inkscape:document-units="px"
|
||||
inkscape:current-layer="layer1"
|
||||
showgrid="false"
|
||||
inkscape:window-width="1920"
|
||||
inkscape:window-height="1039"
|
||||
inkscape:window-x="-4"
|
||||
inkscape:window-y="-4"
|
||||
inkscape:window-maximized="1" />
|
||||
<metadata
|
||||
id="metadata7">
|
||||
<rdf:RDF>
|
||||
<cc:Work
|
||||
rdf:about="">
|
||||
<dc:format>image/svg+xml</dc:format>
|
||||
<dc:type
|
||||
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
|
||||
<dc:title />
|
||||
</cc:Work>
|
||||
</rdf:RDF>
|
||||
</metadata>
|
||||
<g
|
||||
inkscape:label="Calque 1"
|
||||
inkscape:groupmode="layer"
|
||||
id="layer1">
|
||||
<text
|
||||
xml:space="preserve"
|
||||
style="font-size:40px;font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Vermin Vibes Slant;-inkscape-font-specification:Vermin Vibes Slant"
|
||||
x="102.85714"
|
||||
y="571.79077"
|
||||
id="text2989"
|
||||
sodipodi:linespacing="125%"
|
||||
inkscape:export-filename="C:\Documents and Settings\Administrateur\Bureau\rect3019.png"
|
||||
inkscape:export-xdpi="299.89999"
|
||||
inkscape:export-ydpi="299.89999"><tspan
|
||||
sodipodi:role="line"
|
||||
id="tspan2991"
|
||||
x="102.85714"
|
||||
y="571.79077">LITE</tspan></text>
|
||||
<text
|
||||
xml:space="preserve"
|
||||
style="font-size:64px;font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Vermin Vibes Slant;-inkscape-font-specification:Vermin Vibes Slant"
|
||||
x="298.32632"
|
||||
y="573.13269"
|
||||
id="text2993"
|
||||
sodipodi:linespacing="125%"
|
||||
inkscape:export-filename="C:\Documents and Settings\Administrateur\Bureau\rect3019.png"
|
||||
inkscape:export-xdpi="299.89999"
|
||||
inkscape:export-ydpi="299.89999"><tspan
|
||||
sodipodi:role="line"
|
||||
id="tspan2995"
|
||||
x="298.32632"
|
||||
y="573.13269">SATA</tspan></text>
|
||||
<rect
|
||||
style="fill:none;stroke:#0e3333;stroke-width:1;stroke-miterlimit:4;stroke-opacity:0;stroke-dasharray:1, 1;stroke-dashoffset:0"
|
||||
id="rect3019"
|
||||
width="666.70068"
|
||||
height="144.45181"
|
||||
x="61.619305"
|
||||
y="477.08786"
|
||||
inkscape:export-xdpi="299.89999"
|
||||
inkscape:export-ydpi="299.89999" />
|
||||
<text
|
||||
xml:space="preserve"
|
||||
style="font-size:64px;font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Vermin Vibes Slant;-inkscape-font-specification:Vermin Vibes Slant"
|
||||
x="354.59747"
|
||||
y="605.80811"
|
||||
id="text2987"
|
||||
sodipodi:linespacing="125%"><tspan
|
||||
sodipodi:role="line"
|
||||
id="tspan2989"
|
||||
x="354.59747"
|
||||
y="605.80811"
|
||||
style="font-size:14px">powered by</tspan></text>
|
||||
<g
|
||||
transform="matrix(0.47542256,0,0,0.47542256,432.54099,375.04272)"
|
||||
id="layer1-7"
|
||||
inkscape:label="Layer 1">
|
||||
<rect
|
||||
y="459.6947"
|
||||
x="242.87946"
|
||||
height="23.704336"
|
||||
width="66.843575"
|
||||
id="rect6043"
|
||||
style="fill:url(#linearGradient6099);fill-opacity:1;stroke:none" />
|
||||
<path
|
||||
style="font-size:18px;fill:#00ad00;fill-opacity:1;font-family:'DejaVu Sans, Arial, Sans'"
|
||||
d="m 366.02427,471.24237 c -22.519,36.716 -73.921,29.454 -73.921,29.454 32.229,-32.229 0.16326,-57.929 0.16326,-57.929 0,0 51.973,-7.996 73.758,28.475"
|
||||
id="path29"
|
||||
inkscape:connector-curvature="0" />
|
||||
<path
|
||||
style="font-size:18px;fill:none;font-family:'DejaVu Sans, Arial, Sans'"
|
||||
d="m 366.02427,471.24237 c -22.519,36.716 -73.921,29.454 -73.921,29.454 32.229,-32.229 0.16326,-57.929 0.16326,-57.929 0,0 51.973,-7.996 73.758,28.475"
|
||||
id="path31"
|
||||
inkscape:connector-curvature="0" />
|
||||
<path
|
||||
d="m 364.64427,470.43237 c -5.3108,8.6038 -12.825,15.435 -21.719,20.199 -7.7214,4.1357 -16.268,6.5868 -24.897,7.9228 -6.0011,0.92916 -12.11,1.2491 -18.178,1.0907 -1.8804,-0.0489 -3.76,-0.15102 -5.6339,-0.31747 -0.51696,-0.046 -1.0334,-0.0977 -1.5489,-0.15739 -0.29226,-0.0338 -0.85842,-0.11431 -0.14808,-0.0144 0.234,0.88632 0.468,1.7726 0.702,2.6592 8.3771,-8.431 15.128,-19.206 14.819,-31.472 -0.20072,-7.9507 -3.4638,-15.551 -8.2374,-21.816 -1.8852,-2.4739 -3.9815,-4.9329 -6.418,-6.8911 -0.234,0.88633 -0.46801,1.7729 -0.70201,2.6592 0.61487,-0.0942 -0.31747,0.0377 0.24551,-0.0343 0.60361,-0.0769 1.2087,-0.14221 1.814,-0.20194 2.1765,-0.21442 4.3616,-0.33925 6.5477,-0.40461 7.0088,-0.20928 14.057,0.24796 20.959,1.4953 7.9781,1.442 15.783,3.9756 22.86,7.9654 8.0388,4.532 14.777,11.012 19.535,18.924 1.0557,1.756 3.8079,0.15739 2.7476,-1.606 -5.1914,-8.6336 -12.6,-15.613 -21.408,-20.474 -7.7483,-4.275 -16.361,-6.8644 -25.074,-8.2486 -9.4825,-1.5066 -19.54,-1.944 -29.073,-0.48367 -1.1345,0.17379 -1.5874,1.9477 -0.70201,2.6592 3.0624,2.4612 5.6283,5.6205 7.7454,8.8104 4.5202,6.8118 6.9303,14.977 5.6423,23.154 -1.4588,9.2607 -7.0781,17.201 -13.551,23.715 -0.75977,0.76492 -0.53067,2.4859 0.70201,2.6592 9.9738,1.4023 20.482,0.7025 30.334,-1.1362 8.4689,-1.5805 16.759,-4.3922 24.256,-8.6664 8.6297,-4.9199 15.91,-11.93 21.128,-20.383 1.0812,-1.7514 -1.6723,-3.3482 -2.7473,-1.606 z"
|
||||
id="path33"
|
||||
inkscape:connector-curvature="0"
|
||||
style="font-size:18px;font-family:'DejaVu Sans, Arial, Sans'" />
|
||||
<path
|
||||
style="font-size:18px;fill:url(#linearGradient3349);fill-opacity:1;font-family:'DejaVu Sans, Arial, Sans'"
|
||||
d="m 295.19427,443.74237 c 0,0 12.67,11.257 12.67,27.475 0,0 9.8236,-9.7551 23.069,0 0,0 15.098,13.305 33.229,0 0,0 -15.539,-32.087 -68.968,-27.475 z"
|
||||
id="path35"
|
||||
inkscape:connector-curvature="0" />
|
||||
<line
|
||||
style="font-size:18px;fill:none;stroke:#000000;stroke-width:2.44770002;font-family:'DejaVu Sans, Arial, Sans'"
|
||||
x1="366.79425"
|
||||
y1="471.03238"
|
||||
x2="400.71429"
|
||||
y2="471.03238"
|
||||
id="line39" />
|
||||
<path
|
||||
sodipodi:nodetypes="cc"
|
||||
style="font-size:18px;fill:none;stroke:#000000;stroke-width:2.44799995;stroke-miterlimit:4;stroke-dasharray:none;font-family:'DejaVu Sans, Arial, Sans'"
|
||||
d="m 344.15733,461.16448 4.84652,0"
|
||||
id="path59"
|
||||
inkscape:connector-curvature="0" />
|
||||
<path
|
||||
inkscape:connector-curvature="0"
|
||||
id="path6037"
|
||||
d="m 344.15733,481.90109 4.84652,0"
|
||||
style="font-size:18px;fill:none;stroke:#000000;stroke-width:2.44799995;stroke-miterlimit:4;stroke-dasharray:none;font-family:'DejaVu Sans, Arial, Sans'"
|
||||
sodipodi:nodetypes="cc" />
|
||||
<g
|
||||
id="text6055"
|
||||
style="font-size:40px;font-style:normal;font-variant:normal;font-weight:300;font-stretch:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Orbitron;-inkscape-font-specification:Orbitron Light">
|
||||
<path
|
||||
id="path3009"
|
||||
d="m 289.94285,514.5193 -30.64,0 0,23.2 3.32,0 0,-18.36 c 0,-0.84 0.72,-1.56 1.56,-1.56 l 9.68,0 c 0.84,0 1.56,0.72 1.56,1.56 l 0,18.36 3.32,0 0,-18.36 c 0,-0.84 0.68,-1.56 1.56,-1.56 l 9.64,0 c 0.88,0 1.6,0.72 1.6,1.56 l 0,18.36 3.24,0 0,-18.36 c 0,-2.68 -2.12,-4.84 -4.84,-4.84"
|
||||
inkscape:connector-curvature="0" />
|
||||
<path
|
||||
id="path3011"
|
||||
d="m 298.36348,537.7193 3.28,0 0,-23.2 -3.28,0 0,23.2 m 0,-30.8 0,3.28 3.28,0 0,-3.28 -3.28,0"
|
||||
inkscape:connector-curvature="0" />
|
||||
<path
|
||||
id="path3013"
|
||||
d="m 329.88285,541.9993 0,-22.64 c 0,-2.68 -2.12,-4.84 -4.84,-4.84 l -13.92,0 c -2.67999,0 -4.84,2.16 -4.84,4.84 l 0,13.52 c 0,2.68 2.16001,4.84 4.84,4.84 l 15.48,0 0,4.28 c 0,0.84 -0.72,1.56 -1.56,1.56 l -14.48,0 0,3.32 14.48,0 c 2.72,0 4.84,-2.16 4.84,-4.88 m -18.76,-7.56 c -0.84,0 -1.56,-0.72 -1.56,-1.56 l 0,-13.52 c 0,-0.84 0.72,-1.56 1.56,-1.56 l 13.92,0 c 0.84,0 1.56,0.72 1.56,1.56 l 0,13.52 c 0,0.84 -0.72,1.56 -1.56,1.56 l -13.92,0"
|
||||
inkscape:connector-curvature="0" />
|
||||
<path
|
||||
id="path3015"
|
||||
d="m 352.1616,514.5193 -13.92,0 c -2.67999,0 -4.84,2.16 -4.84,4.84 l 0,13.52 c 0,2.68 2.16001,4.84 4.84,4.84 l 18.8,0 0,-3.28 -18.8,0 c -0.84,0 -1.56,-0.72 -1.56,-1.56 l 0,-5.12 20.36,0 0,-8.4 c 0,-2.68 -2.16,-4.84 -4.88,-4.84 m -15.48,9.96 0,-5.12 c 0,-0.84 0.72,-1.56 1.56,-1.56 l 13.92,0 c 0.88,0 1.56,0.72 1.56,1.56 l 0,5.12 -17.04,0"
|
||||
inkscape:connector-curvature="0" />
|
||||
<path
|
||||
id="path3017"
|
||||
d="m 379.97785,514.5193 -18.8,0 0,23.2 3.28,0 0,-18.36 c 0,-0.84 0.72,-1.56 1.6,-1.56 l 13.92,0 c 0.84,0 1.56,0.72 1.56,1.56 l 0,18.36 3.28,0 0,-18.36 c 0,-2.68 -2.16,-4.84 -4.84,-4.84"
|
||||
inkscape:connector-curvature="0" />
|
||||
</g>
|
||||
<path
|
||||
inkscape:connector-curvature="0"
|
||||
id="path6105"
|
||||
d="m 289.42519,459.68794 14.57866,0"
|
||||
style="font-size:18px;fill:none;stroke:#000000;stroke-width:2.61650872;stroke-miterlimit:4;stroke-dasharray:none;font-family:'DejaVu Sans, Arial, Sans'"
|
||||
sodipodi:nodetypes="cc" />
|
||||
<path
|
||||
sodipodi:nodetypes="cc"
|
||||
style="font-size:18px;fill:none;stroke:#000000;stroke-width:2.61650872;stroke-miterlimit:4;stroke-dasharray:none;font-family:'DejaVu Sans, Arial, Sans'"
|
||||
d="m 289.42519,483.37763 14.57866,0"
|
||||
id="path6107"
|
||||
inkscape:connector-curvature="0" />
|
||||
</g>
|
||||
</g>
|
||||
</svg>
|
||||
|
After Width: | Height: | Size: 12 KiB |
|
|
@ -0,0 +1,17 @@
|
|||
"""Sphinx ReadTheDocs theme.
|
||||
|
||||
From https://github.com/ryan-roemer/sphinx-bootstrap-theme.
|
||||
|
||||
"""
|
||||
import os
|
||||
|
||||
VERSION = (0, 1, 6)
|
||||
|
||||
__version__ = ".".join(str(v) for v in VERSION)
|
||||
__version_full__ = __version__
|
||||
|
||||
|
||||
def get_html_theme_path():
|
||||
"""Return list of HTML theme paths."""
|
||||
cur_dir = os.path.abspath(os.path.dirname(os.path.dirname(__file__)))
|
||||
return cur_dir
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
<div role="navigation" aria-label="breadcrumbs navigation">
|
||||
|
||||
<div class="breadcrumb-box">
|
||||
<a class="breadcrumb-box-item" href="{{ pathto(master_doc) }}">Home</a>
|
||||
{% for doc in parents %}
|
||||
<a class="breadcrumb-box-item" href="{{ doc.link|e }}">» {{ doc.title }}</a>
|
||||
{% endfor %}
|
||||
<div class="breadcrumb-box-item">» {{ title }}</div>
|
||||
</div>
|
||||
|
||||
</div>
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
<footer>
|
||||
{% if next or prev %}
|
||||
<div class="rst-footer-buttons" role="navigation" aria-label="footer navigation">
|
||||
{% if next %}
|
||||
<a href="{{ next.link|e }}" class="btn btn-neutral float-right" title="{{ next.title|striptags|e }}"/>Next <span class="fa fa-arrow-circle-right"></span></a>
|
||||
{% endif %}
|
||||
{% if prev %}
|
||||
<a href="{{ prev.link|e }}" class="btn btn-neutral" title="{{ prev.title|striptags|e }}"><span class="fa fa-arrow-circle-left"></span> Previous</a>
|
||||
{% endif %}
|
||||
</div>
|
||||
{% endif %}
|
||||
|
||||
|
||||
<!--begin hamishw addition -->
|
||||
|
||||
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!--Footer important links
|
||||
If no such page exists then nav item is not created. CSS defines which of the long or short version is
|
||||
displayed. -->
|
||||
|
||||
|
||||
{% set footer_links = [
|
||||
('docs/getting_started/bug_reports', 'Report Bug', 'Report Bug'),
|
||||
('docs/introducing_litesata/license', 'Licensing', 'Licensing'),
|
||||
('docs/contributing/contributing', 'Contributing', 'Contributing'),
|
||||
('docs/introducing_litesata/release_notes', 'Release notes', 'Release notes'),
|
||||
('docs/introducing_litesata/community', 'Help', 'Contact'),
|
||||
] -%}
|
||||
|
||||
<div class="footer-nav-bar" style="">
|
||||
<div class="footer-options">
|
||||
|
||||
{% for document, shorttext, longtext in footer_links %}
|
||||
{%- if hasdoc(document) %}
|
||||
<a class="footer-navlink-short" title="{{ shorttext }}" href="{{ pathto(document) }}">{{ shorttext }}</a><a class="footer-navlink-long" title="{{ longtext }}" href="{{ pathto(document) }}">{{ longtext }}</a>
|
||||
{%- elif document | truncate(4, True, end='') == 'http' %}
|
||||
<a class="footer-navlink-short external" href="{{ document }}">{{ shorttext }}</a><a class="footer-navlink-long external" href="{{ document }}">{{ longtext }}</a>
|
||||
{%- else %}
|
||||
{{ shorttext }}
|
||||
{%- endif %}
|
||||
{% endfor %}
|
||||
|
||||
</div>
|
||||
|
||||
|
||||
|
||||
</div>
|
||||
|
||||
<!-- {% include "breadcrumbs.html" %} -->
|
||||
|
||||
<!-- {% trans %}<a href="https://github.com/snide/sphinx_rtd_theme">Sphinx theme</a> provided by <a href="https://readthedocs.org">Read the Docs</a>{% endtrans %} --.
|
||||
<!--end hamishw addition -->
|
||||
|
||||
|
||||
|
||||
<!-- end section moved here by hamishw -->
|
||||
<div role="contentinfo" class="copyright-box">
|
||||
<!-- section moved here by hamishw - needs tidying, which is why it is still in breadcrumbs mode -->
|
||||
<ul class="wy-breadcrumbs">
|
||||
<li class="wy-breadcrumbs-aside">
|
||||
{% if display_github %}
|
||||
<a href="https://github.com/{{ github_user }}/{{ github_repo }}/blob/{{ github_version }}{{ conf_py_path }}{{ pagename }}.rst" class="fa fa-github"> Edit on GitHub</a>
|
||||
{% elif display_bitbucket %}
|
||||
<a href="https://bitbucket.org/{{ bitbucket_user }}/{{ bitbucket_repo }}/src/{{ bitbucket_version}}{{ conf_py_path }}{{ pagename }}.rst" class="fa fa-bitbucket"> Edit on Bitbucket</a>
|
||||
{% elif show_source and has_source and sourcename %}
|
||||
<a href="{{ pathto('_sources/' + sourcename, true)|e }}" rel="nofollow"> View page source</a>
|
||||
{% endif %}
|
||||
</li>
|
||||
|
||||
<li class="wy-breadcrumbs-aside">
|
||||
{%- if hasdoc('docs/site/about') %}
|
||||
<a href="{{pathto('docs/site/about')}}">About site</a>
|
||||
{%- endif %}
|
||||
</li>
|
||||
|
||||
</ul>
|
||||
|
||||
<p>
|
||||
{%- if show_copyright %}
|
||||
{%- if hasdoc('copyright') %}
|
||||
{% trans path=pathto('copyright'), copyright=copyright|e %}© <a href="{{ path }}">Copyright</a> {{ copyright }}.{% endtrans %}
|
||||
{%- else %}
|
||||
<!-- {% trans copyright=copyright|e %}© Copyright {{ copyright }}.{% endtrans %} -->
|
||||
© Copyright {{ copyright }} <a href="{{ pathto("docs\contributing\AUTHORS") }}">EnjoyDigital and M-Labs Contributors</a>.
|
||||
<!-- update theme to remove the translation stuff here - it was breaking due to link to AUTHORS file. This is a cludge to allow specific link to my authors file -->
|
||||
{%- endif %}
|
||||
{%- endif %}
|
||||
|
||||
{%- if last_updated %}
|
||||
{% trans last_updated=last_updated|e %}Last updated on {{ last_updated }}.{% endtrans %}
|
||||
{%- endif %}
|
||||
</p>
|
||||
|
||||
</div>
|
||||
|
||||
|
||||
</footer>
|
||||
|
|
@ -0,0 +1,208 @@
|
|||
{# TEMPLATE VAR SETTINGS #}
|
||||
{%- set url_root = pathto('', 1) %}
|
||||
{%- if url_root == '#' %}{% set url_root = '' %}{% endif %}
|
||||
{%- if not embedded and docstitle %}
|
||||
{%- set titlesuffix = " — "|safe + docstitle|e %}
|
||||
{%- else %}
|
||||
{%- set titlesuffix = "" %}
|
||||
{%- endif %}
|
||||
|
||||
<!DOCTYPE html>
|
||||
<!--[if IE 8]><html class="no-js lt-ie9" lang="en" > <![endif]-->
|
||||
<!--[if gt IE 8]><!--> <html class="no-js" lang="en" > <!--<![endif]-->
|
||||
<head>
|
||||
<meta charset="utf-8">
|
||||
<meta name="viewport" content="width=device-width, initial-scale=1.0">
|
||||
{% block htmltitle %}
|
||||
<title>{{ title|striptags|e }}{{ titlesuffix }}</title>
|
||||
{% endblock %}
|
||||
|
||||
{# FAVICON #}
|
||||
{% if favicon %}
|
||||
<link rel="shortcut icon" href="{{ pathto('_static/' + favicon, 1) }}"/>
|
||||
{% endif %}
|
||||
|
||||
{# CSS #}
|
||||
<link href='https://fonts.googleapis.com/css?family=Lato:400,700|Roboto+Slab:400,700|Inconsolata:400,700' rel='stylesheet' type='text/css'>
|
||||
|
||||
{# OPENSEARCH #}
|
||||
{% if not embedded %}
|
||||
{% if use_opensearch %}
|
||||
<link rel="search" type="application/opensearchdescription+xml" title="{% trans docstitle=docstitle|e %}Search within {{ docstitle }}{% endtrans %}" href="{{ pathto('_static/opensearch.xml', 1) }}"/>
|
||||
{% endif %}
|
||||
|
||||
{% endif %}
|
||||
|
||||
{# RTD hosts this file, so just load on non RTD builds #}
|
||||
{% if not READTHEDOCS %}
|
||||
<link rel="stylesheet" href="{{ pathto('_static/' + style, 1) }}" type="text/css" />
|
||||
{% endif %}
|
||||
|
||||
{% for cssfile in css_files %}
|
||||
<link rel="stylesheet" href="{{ pathto(cssfile, 1) }}" type="text/css" />
|
||||
{% endfor %}
|
||||
|
||||
{%- block linktags %}
|
||||
{%- if hasdoc('about') %}
|
||||
<link rel="author" title="{{ _('About these documents') }}"
|
||||
href="{{ pathto('about') }}"/>
|
||||
{%- endif %}
|
||||
{%- if hasdoc('genindex') %}
|
||||
<link rel="index" title="{{ _('Index') }}"
|
||||
href="{{ pathto('genindex') }}"/>
|
||||
{%- endif %}
|
||||
{%- if hasdoc('search') %}
|
||||
<link rel="search" title="{{ _('Search') }}" href="{{ pathto('search') }}"/>
|
||||
{%- endif %}
|
||||
{%- if hasdoc('copyright') %}
|
||||
<link rel="copyright" title="{{ _('Copyright') }}" href="{{ pathto('copyright') }}"/>
|
||||
{%- endif %}
|
||||
<link rel="top" title="{{ docstitle|e }}" href="{{ pathto('index') }}"/>
|
||||
{%- if parents %}
|
||||
<link rel="up" title="{{ parents[-1].title|striptags|e }}" href="{{ parents[-1].link|e }}"/>
|
||||
{%- endif %}
|
||||
{%- if next %}
|
||||
<link rel="next" title="{{ next.title|striptags|e }}" href="{{ next.link|e }}"/>
|
||||
{%- endif %}
|
||||
{%- if prev %}
|
||||
<link rel="prev" title="{{ prev.title|striptags|e }}" href="{{ prev.link|e }}"/>
|
||||
{%- endif %}
|
||||
{%- endblock %}
|
||||
{%- block extrahead %} {% endblock %}
|
||||
|
||||
{# Keep modernizr in head - http://modernizr.com/docs/#installing #}
|
||||
<script src="https://cdnjs.cloudflare.com/ajax/libs/modernizr/2.6.2/modernizr.min.js"></script>
|
||||
|
||||
</head>
|
||||
|
||||
<body class="wy-body-for-nav" role="document">
|
||||
|
||||
|
||||
<div class="grid-to-center-rtd-theme">
|
||||
|
||||
<div class="wy-grid-for-nav">
|
||||
|
||||
|
||||
|
||||
{# SIDE NAV, TOGGLES ON MOBILE #}
|
||||
<nav data-toggle="wy-nav-shift" class="wy-nav-side">
|
||||
<div class="wy-side-nav-search">
|
||||
<!-- <a href="{{ pathto(master_doc) }}" class="fa fa-home"> {{ project }}</a> -->
|
||||
<a href="{{ pathto(master_doc) }}"> <img src="{{ url_root }}/_static/{{ logo }}" alt="Logo" /> </a>
|
||||
|
||||
{% include "searchbox.html" %}
|
||||
</div>
|
||||
|
||||
<div class="wy-menu wy-menu-vertical" data-spy="affix" role="navigation" aria-label="main navigation">
|
||||
|
||||
{% set toctree = toctree(maxdepth=4, collapse=False, includehidden=True) %}
|
||||
{% if toctree %}
|
||||
{{ toctree }}
|
||||
<a class="toctree-l1" title="Index" href="{{ pathto('genindex') }}">Index</a>
|
||||
{% else %}
|
||||
<!-- Local TOC -->
|
||||
<div class="local-toc">{{ toc }}</div>
|
||||
{% endif %}
|
||||
</div>
|
||||
|
||||
</nav>
|
||||
|
||||
<section data-toggle="wy-nav-shift" class="wy-nav-content-wrap">
|
||||
|
||||
{# MOBILE NAV, TRIGGLES SIDE NAV ON TOGGLE #}
|
||||
<nav class="wy-nav-top" role="navigation" aria-label="top navigation">
|
||||
<i data-toggle="wy-nav-top" class="fa fa-bars"></i>
|
||||
<!-- <a href="{{ pathto(master_doc) }}">{{ project }}</a> -->
|
||||
<a href="{{ pathto(master_doc) }}"> <img src="{{ url_root }}/_static/{{ logo }}" alt="Logo" /> </a>
|
||||
</nav>
|
||||
|
||||
|
||||
|
||||
{# PAGE CONTENT #}
|
||||
<div class="wy-nav-content">
|
||||
<div class="rst-content">
|
||||
|
||||
<!--begin hamishw addition -->
|
||||
|
||||
<!--Nav bar defined as a document followed by short version of nav text and long version
|
||||
If no such page exists then nav item is not created. CSS defines which of the long or short version is
|
||||
displayed. -->
|
||||
{% set navigation_bar = [
|
||||
('docs/index', 'Docs', 'Documentation'),
|
||||
('docs/getting_started/downloads', 'SDK', 'Downloads'),
|
||||
('docs/introducing_litesata/community', 'Help', 'Community'),
|
||||
('https://github.com/enjoy-digital/litesata', 'Github', 'Github Project')
|
||||
] -%}
|
||||
|
||||
|
||||
<div class="main-nav-bar" style="">
|
||||
|
||||
<!-- the layout of the menu options - centered with left and right alignment of the first and last loop items respectively.
|
||||
This is VERY UGLY as I'm adding to the CSS in the code to force the alignment. Would be better just to have the elements here and have the CSS in the CSS file. This could be done with a CSS selector, but not worked out how yet. -->
|
||||
|
||||
<ul id="menu-options">
|
||||
{% for document, shorttext, longtext in navigation_bar %}
|
||||
{%- if hasdoc(document) %}
|
||||
<li{%- if loop.first %} style="text-align:left;" {%- endif %}{%- if loop.last %} style="text-align:right;" {%- endif %}><a class="navlink-short" title="{{ shorttext }}" href="{{ pathto(document) }}">{{ shorttext }}</a><a class="navlink-long" title="{{ longtext }}" href="{{ pathto(document) }}">{{ longtext }}</a></li>
|
||||
{%- elif document | truncate(4, True, end='') == 'http' %}
|
||||
<li{%- if loop.first %} style="text-align:left;" {%- endif %}{%- if loop.last %} style="text-align:right;" {%- endif %}><a class="navlink-short external" href="{{ document }}">{{ shorttext }}</a><a class="navlink-long external" href="{{ document }}">{{ longtext }}</a></li>
|
||||
{%- endif %}
|
||||
{% endfor %}
|
||||
</ul>
|
||||
<!-- <div style="clear:both;"></div> -->
|
||||
{% include "breadcrumbs.html" %}
|
||||
|
||||
</div>
|
||||
|
||||
|
||||
|
||||
<!--end hamishw addition -->
|
||||
|
||||
<!--HamishW move {% include "breadcrumbs.html" %} -->
|
||||
<div role="main">
|
||||
{% block body %}{% endblock %}
|
||||
</div>
|
||||
{% include "footer.html" %}
|
||||
</div>
|
||||
</div>
|
||||
|
||||
</section>
|
||||
|
||||
</div>
|
||||
{% include "versions.html" %}
|
||||
|
||||
{% if not embedded %}
|
||||
|
||||
<script type="text/javascript">
|
||||
var DOCUMENTATION_OPTIONS = {
|
||||
URL_ROOT:'{{ url_root }}',
|
||||
VERSION:'{{ release|e }}',
|
||||
COLLAPSE_INDEX:false,
|
||||
FILE_SUFFIX:'{{ '' if no_search_suffix else file_suffix }}',
|
||||
HAS_SOURCE: {{ has_source|lower }}
|
||||
};
|
||||
</script>
|
||||
{%- for scriptfile in script_files %}
|
||||
<script type="text/javascript" src="{{ pathto(scriptfile, 1) }}"></script>
|
||||
{%- endfor %}
|
||||
|
||||
{% endif %}
|
||||
|
||||
{# RTD hosts this file, so just load on non RTD builds #}
|
||||
{% if not READTHEDOCS %}
|
||||
<script type="text/javascript" src="{{ pathto('_static/js/theme.js', 1) }}"></script>
|
||||
{% endif %}
|
||||
|
||||
{# STICKY NAVIGATION #}
|
||||
{% if theme_sticky_navigation %}
|
||||
<script type="text/javascript">
|
||||
jQuery(function () {
|
||||
SphinxRtdTheme.StickyNav.enable();
|
||||
});
|
||||
</script>
|
||||
{% endif %}
|
||||
|
||||
{%- block footer %} {% endblock %}
|
||||
</div>
|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,205 @@
|
|||
{#
|
||||
basic/layout.html
|
||||
~~~~~~~~~~~~~~~~~
|
||||
|
||||
Master layout template for Sphinx themes.
|
||||
|
||||
:copyright: Copyright 2007-2013 by the Sphinx team, see AUTHORS.
|
||||
:license: BSD, see LICENSE for details.
|
||||
#}
|
||||
{%- block doctype -%}
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
|
||||
"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
{%- endblock %}
|
||||
{%- set reldelim1 = reldelim1 is not defined and ' »' or reldelim1 %}
|
||||
{%- set reldelim2 = reldelim2 is not defined and ' |' or reldelim2 %}
|
||||
{%- set render_sidebar = (not embedded) and (not theme_nosidebar|tobool) and
|
||||
(sidebars != []) %}
|
||||
{%- set url_root = pathto('', 1) %}
|
||||
{# XXX necessary? #}
|
||||
{%- if url_root == '#' %}{% set url_root = '' %}{% endif %}
|
||||
{%- if not embedded and docstitle %}
|
||||
{%- set titlesuffix = " — "|safe + docstitle|e %}
|
||||
{%- else %}
|
||||
{%- set titlesuffix = "" %}
|
||||
{%- endif %}
|
||||
|
||||
{%- macro relbar() %}
|
||||
<div class="related">
|
||||
<h3>{{ _('Navigation') }}</h3>
|
||||
<ul>
|
||||
{%- for rellink in rellinks %}
|
||||
<li class="right" {% if loop.first %}style="margin-right: 10px"{% endif %}>
|
||||
<a href="{{ pathto(rellink[0]) }}" title="{{ rellink[1]|striptags|e }}"
|
||||
{{ accesskey(rellink[2]) }}>{{ rellink[3] }}</a>
|
||||
{%- if not loop.first %}{{ reldelim2 }}{% endif %}</li>
|
||||
{%- endfor %}
|
||||
{%- block rootrellink %}
|
||||
<li><a href="{{ pathto(master_doc) }}">{{ shorttitle|e }}</a>{{ reldelim1 }}</li>
|
||||
{%- endblock %}
|
||||
{%- for parent in parents %}
|
||||
<li><a href="{{ parent.link|e }}" {% if loop.last %}{{ accesskey("U") }}{% endif %}>{{ parent.title }}</a>{{ reldelim1 }}</li>
|
||||
{%- endfor %}
|
||||
{%- block relbaritems %} {% endblock %}
|
||||
</ul>
|
||||
</div>
|
||||
{%- endmacro %}
|
||||
|
||||
{%- macro sidebar() %}
|
||||
{%- if render_sidebar %}
|
||||
<div class="sphinxsidebar">
|
||||
<div class="sphinxsidebarwrapper">
|
||||
{%- block sidebarlogo %}
|
||||
{%- if logo %}
|
||||
<p class="logo"><a href="{{ pathto(master_doc) }}">
|
||||
<img class="logo" src="{{ pathto('_static/' + logo, 1) }}" alt="Logo"/>
|
||||
</a></p>
|
||||
{%- endif %}
|
||||
{%- endblock %}
|
||||
{%- if sidebars != None %}
|
||||
{#- new style sidebar: explicitly include/exclude templates #}
|
||||
{%- for sidebartemplate in sidebars %}
|
||||
{%- include sidebartemplate %}
|
||||
{%- endfor %}
|
||||
{%- else %}
|
||||
{#- old style sidebars: using blocks -- should be deprecated #}
|
||||
{%- block sidebartoc %}
|
||||
{%- include "localtoc.html" %}
|
||||
{%- endblock %}
|
||||
{%- block sidebarrel %}
|
||||
{%- include "relations.html" %}
|
||||
{%- endblock %}
|
||||
{%- block sidebarsourcelink %}
|
||||
{%- include "sourcelink.html" %}
|
||||
{%- endblock %}
|
||||
{%- if customsidebar %}
|
||||
{%- include customsidebar %}
|
||||
{%- endif %}
|
||||
{%- block sidebarsearch %}
|
||||
{%- include "searchbox.html" %}
|
||||
{%- endblock %}
|
||||
{%- endif %}
|
||||
</div>
|
||||
</div>
|
||||
{%- endif %}
|
||||
{%- endmacro %}
|
||||
|
||||
{%- macro script() %}
|
||||
<script type="text/javascript">
|
||||
var DOCUMENTATION_OPTIONS = {
|
||||
URL_ROOT: '{{ url_root }}',
|
||||
VERSION: '{{ release|e }}',
|
||||
COLLAPSE_INDEX: false,
|
||||
FILE_SUFFIX: '{{ '' if no_search_suffix else file_suffix }}',
|
||||
HAS_SOURCE: {{ has_source|lower }}
|
||||
};
|
||||
</script>
|
||||
{%- for scriptfile in script_files %}
|
||||
<script type="text/javascript" src="{{ pathto(scriptfile, 1) }}"></script>
|
||||
{%- endfor %}
|
||||
{%- endmacro %}
|
||||
|
||||
{%- macro css() %}
|
||||
<link rel="stylesheet" href="{{ pathto('_static/' + style, 1) }}" type="text/css" />
|
||||
<link rel="stylesheet" href="{{ pathto('_static/pygments.css', 1) }}" type="text/css" />
|
||||
{%- for cssfile in css_files %}
|
||||
<link rel="stylesheet" href="{{ pathto(cssfile, 1) }}" type="text/css" />
|
||||
{%- endfor %}
|
||||
{%- endmacro %}
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset={{ encoding }}" />
|
||||
{{ metatags }}
|
||||
{%- block htmltitle %}
|
||||
<title>{{ title|striptags|e }}{{ titlesuffix }}</title>
|
||||
{%- endblock %}
|
||||
{{ css() }}
|
||||
{%- if not embedded %}
|
||||
{{ script() }}
|
||||
{%- if use_opensearch %}
|
||||
<link rel="search" type="application/opensearchdescription+xml"
|
||||
title="{% trans docstitle=docstitle|e %}Search within {{ docstitle }}{% endtrans %}"
|
||||
href="{{ pathto('_static/opensearch.xml', 1) }}"/>
|
||||
{%- endif %}
|
||||
{%- if favicon %}
|
||||
<link rel="shortcut icon" href="{{ pathto('_static/' + favicon, 1) }}"/>
|
||||
{%- endif %}
|
||||
{%- endif %}
|
||||
{%- block linktags %}
|
||||
{%- if hasdoc('about') %}
|
||||
<link rel="author" title="{{ _('About these documents') }}" href="{{ pathto('about') }}" />
|
||||
{%- endif %}
|
||||
{%- if hasdoc('genindex') %}
|
||||
<link rel="index" title="{{ _('Index') }}" href="{{ pathto('genindex') }}" />
|
||||
{%- endif %}
|
||||
{%- if hasdoc('search') %}
|
||||
<link rel="search" title="{{ _('Search') }}" href="{{ pathto('search') }}" />
|
||||
{%- endif %}
|
||||
{%- if hasdoc('copyright') %}
|
||||
<link rel="copyright" title="{{ _('Copyright') }}" href="{{ pathto('copyright') }}" />
|
||||
{%- endif %}
|
||||
<link rel="top" title="{{ docstitle|e }}" href="{{ pathto('index') }}" />
|
||||
{%- if parents %}
|
||||
<link rel="up" title="{{ parents[-1].title|striptags|e }}" href="{{ parents[-1].link|e }}" />
|
||||
{%- endif %}
|
||||
{%- if next %}
|
||||
<link rel="next" title="{{ next.title|striptags|e }}" href="{{ next.link|e }}" />
|
||||
{%- endif %}
|
||||
{%- if prev %}
|
||||
<link rel="prev" title="{{ prev.title|striptags|e }}" href="{{ prev.link|e }}" />
|
||||
{%- endif %}
|
||||
{%- endblock %}
|
||||
{%- block extrahead %} {% endblock %}
|
||||
</head>
|
||||
<body>
|
||||
{%- block header %}{% endblock %}
|
||||
|
||||
{%- block relbar1 %}{{ relbar() }}{% endblock %}
|
||||
|
||||
{%- block content %}
|
||||
{%- block sidebar1 %} {# possible location for sidebar #} {% endblock %}
|
||||
|
||||
<div class="document">
|
||||
{%- block document %}
|
||||
<div class="documentwrapper">
|
||||
{%- if render_sidebar %}
|
||||
<div class="bodywrapper">
|
||||
{%- endif %}
|
||||
<div class="body">
|
||||
{% block body %} {% endblock %}
|
||||
</div>
|
||||
{%- if render_sidebar %}
|
||||
</div>
|
||||
{%- endif %}
|
||||
</div>
|
||||
{%- endblock %}
|
||||
|
||||
{%- block sidebar2 %}{{ sidebar() }}{% endblock %}
|
||||
<div class="clearer"></div>
|
||||
</div>
|
||||
{%- endblock %}
|
||||
|
||||
{%- block relbar2 %}{{ relbar() }}{% endblock %}
|
||||
|
||||
{%- block footer %}
|
||||
<div class="footer">
|
||||
{%- if show_copyright %}
|
||||
{%- if hasdoc('copyright') %}
|
||||
{% trans path=pathto('copyright'), copyright=copyright|e %}© <a href="{{ path }}">Copyright</a> {{ copyright }}.{% endtrans %}
|
||||
{%- else %}
|
||||
{% trans copyright=copyright|e %}© Copyright {{ copyright }}.{% endtrans %}
|
||||
{%- endif %}
|
||||
{%- endif %}
|
||||
{%- if last_updated %}
|
||||
{% trans last_updated=last_updated|e %}Last updated on {{ last_updated }}.{% endtrans %}
|
||||
{%- endif %}
|
||||
{%- if show_sphinx %}
|
||||
{% trans sphinx_version=sphinx_version|e %}Created using <a href="http://sphinx-doc.org/">Sphinx</a> {{ sphinx_version }}.{% endtrans %}
|
||||
{%- endif %}
|
||||
</div>
|
||||
<p>asdf asdf asdf asdf 22</p>
|
||||
{%- endblock %}
|
||||
</body>
|
||||
</html>
|
||||
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
{#
|
||||
basic/search.html
|
||||
~~~~~~~~~~~~~~~~~
|
||||
|
||||
Template for the search page.
|
||||
|
||||
:copyright: Copyright 2007-2013 by the Sphinx team, see AUTHORS.
|
||||
:license: BSD, see LICENSE for details.
|
||||
#}
|
||||
{%- extends "layout.html" %}
|
||||
{% set title = _('Search') %}
|
||||
{% set script_files = script_files + ['_static/searchtools.js'] %}
|
||||
{% block footer %}
|
||||
<script type="text/javascript">
|
||||
jQuery(function() { Search.loadIndex("{{ pathto('searchindex.js', 1) }}"); });
|
||||
</script>
|
||||
{# this is used when loading the search index using $.ajax fails,
|
||||
such as on Chrome for documents on localhost #}
|
||||
<script type="text/javascript" id="searchindexloader"></script>
|
||||
{{ super() }}
|
||||
{% endblock %}
|
||||
{% block body %}
|
||||
<noscript>
|
||||
<div id="fallback" class="admonition warning">
|
||||
<p class="last">
|
||||
{% trans %}Please activate JavaScript to enable the search
|
||||
functionality.{% endtrans %}
|
||||
</p>
|
||||
</div>
|
||||
</noscript>
|
||||
|
||||
{% if search_performed %}
|
||||
<h2>{{ _('Search Results') }}</h2>
|
||||
{% if not search_results %}
|
||||
<p>{{ _('Your search did not match any documents. Please make sure that all words are spelled correctly and that you\'ve selected enough categories.') }}</p>
|
||||
{% endif %}
|
||||
{% endif %}
|
||||
<div id="search-results">
|
||||
{% if search_results %}
|
||||
<ul>
|
||||
{% for href, caption, context in search_results %}
|
||||
<li>
|
||||
<a href="{{ pathto(item.href) }}">{{ caption }}</a>
|
||||
<p class="context">{{ context|e }}</p>
|
||||
</li>
|
||||
{% endfor %}
|
||||
</ul>
|
||||
{% endif %}
|
||||
</div>
|
||||
{% endblock %}
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
<div role="search">
|
||||
<form id ="rtd-search-form" class="wy-form" action="{{ pathto('search') }}" method="get">
|
||||
<input type="text" name="q" placeholder="Search docs" />
|
||||
<input type="hidden" name="check_keywords" value="yes" />
|
||||
<input type="hidden" name="area" value="default" />
|
||||
</form>
|
||||
</div>
|
||||
|
|
@ -0,0 +1 @@
|
|||
.fa:before{-webkit-font-smoothing:antialiased}.clearfix{*zoom:1}.clearfix:before,.clearfix:after{display:table;content:""}.clearfix:after{clear:both}@font-face{font-family:FontAwesome;font-weight:normal;font-style:normal;src:url("../font/fontawesome_webfont.eot");src:url("../font/fontawesome_webfont.eot?#iefix") format("embedded-opentype"),url("../font/fontawesome_webfont.woff") format("woff"),url("../font/fontawesome_webfont.ttf") format("truetype"),url("../font/fontawesome_webfont.svg#FontAwesome") format("svg")}.fa:before{display:inline-block;font-family:FontAwesome;font-style:normal;font-weight:normal;line-height:1;text-decoration:inherit}a .fa{display:inline-block;text-decoration:inherit}li .fa{display:inline-block}li .fa-large:before,li .fa-large:before{width:1.875em}ul.fas{list-style-type:none;margin-left:2em;text-indent:-0.8em}ul.fas li .fa{width:0.8em}ul.fas li .fa-large:before,ul.fas li .fa-large:before{vertical-align:baseline}.fa-book:before{content:"\f02d"}.icon-book:before{content:"\f02d"}.fa-caret-down:before{content:"\f0d7"}.icon-caret-down:before{content:"\f0d7"}.fa-caret-up:before{content:"\f0d8"}.icon-caret-up:before{content:"\f0d8"}.fa-caret-left:before{content:"\f0d9"}.icon-caret-left:before{content:"\f0d9"}.fa-caret-right:before{content:"\f0da"}.icon-caret-right:before{content:"\f0da"}.rst-versions{position:fixed;bottom:0;left:0;width:300px;color:#fcfcfc;background:#1f1d1d;border-top:solid 10px #343131;font-family:"Lato","proxima-nova","Helvetica Neue",Arial,sans-serif;z-index:400}.rst-versions a{color:#2980b9;text-decoration:none}.rst-versions .rst-badge-small{display:none}.rst-versions .rst-current-version{padding:12px;background-color:#272525;display:block;text-align:right;font-size:90%;cursor:pointer;color:#27ae60;*zoom:1}.rst-versions .rst-current-version:before,.rst-versions .rst-current-version:after{display:table;content:""}.rst-versions .rst-current-version:after{clear:both}.rst-versions .rst-current-version .fa{color:#fcfcfc}.rst-versions .rst-current-version .fa-book{float:left}.rst-versions .rst-current-version .icon-book{float:left}.rst-versions .rst-current-version.rst-out-of-date{background-color:#e74c3c;color:#fff}.rst-versions .rst-current-version.rst-active-old-version{background-color:#f1c40f;color:#000}.rst-versions.shift-up .rst-other-versions{display:block}.rst-versions .rst-other-versions{font-size:90%;padding:12px;color:gray;display:none}.rst-versions .rst-other-versions hr{display:block;height:1px;border:0;margin:20px 0;padding:0;border-top:solid 1px #413d3d}.rst-versions .rst-other-versions dd{display:inline-block;margin:0}.rst-versions .rst-other-versions dd a{display:inline-block;padding:6px;color:#fcfcfc}.rst-versions.rst-badge{width:auto;bottom:20px;right:20px;left:auto;border:none;max-width:300px}.rst-versions.rst-badge .icon-book{float:none}.rst-versions.rst-badge .fa-book{float:none}.rst-versions.rst-badge.shift-up .rst-current-version{text-align:right}.rst-versions.rst-badge.shift-up .rst-current-version .fa-book{float:left}.rst-versions.rst-badge.shift-up .rst-current-version .icon-book{float:left}.rst-versions.rst-badge .rst-current-version{width:auto;height:30px;line-height:30px;padding:0 6px;display:block;text-align:center}@media screen and (max-width: 768px){.rst-versions{width:85%;display:none}.rst-versions.shift{display:block}img{width:100%;height:auto}}
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
Binary file not shown.
|
|
@ -0,0 +1,414 @@
|
|||
<?xml version="1.0" standalone="no"?>
|
||||
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd" >
|
||||
<svg xmlns="http://www.w3.org/2000/svg">
|
||||
<metadata></metadata>
|
||||
<defs>
|
||||
<font id="fontawesomeregular" horiz-adv-x="1536" >
|
||||
<font-face units-per-em="1792" ascent="1536" descent="-256" />
|
||||
<missing-glyph horiz-adv-x="448" />
|
||||
<glyph unicode=" " horiz-adv-x="448" />
|
||||
<glyph unicode="	" horiz-adv-x="448" />
|
||||
<glyph unicode=" " horiz-adv-x="448" />
|
||||
<glyph unicode="¨" horiz-adv-x="1792" />
|
||||
<glyph unicode="©" horiz-adv-x="1792" />
|
||||
<glyph unicode="®" horiz-adv-x="1792" />
|
||||
<glyph unicode="´" horiz-adv-x="1792" />
|
||||
<glyph unicode="Æ" horiz-adv-x="1792" />
|
||||
<glyph unicode=" " horiz-adv-x="768" />
|
||||
<glyph unicode=" " />
|
||||
<glyph unicode=" " horiz-adv-x="768" />
|
||||
<glyph unicode=" " />
|
||||
<glyph unicode=" " horiz-adv-x="512" />
|
||||
<glyph unicode=" " horiz-adv-x="384" />
|
||||
<glyph unicode=" " horiz-adv-x="256" />
|
||||
<glyph unicode=" " horiz-adv-x="256" />
|
||||
<glyph unicode=" " horiz-adv-x="192" />
|
||||
<glyph unicode=" " horiz-adv-x="307" />
|
||||
<glyph unicode=" " horiz-adv-x="85" />
|
||||
<glyph unicode=" " horiz-adv-x="307" />
|
||||
<glyph unicode=" " horiz-adv-x="384" />
|
||||
<glyph unicode="™" horiz-adv-x="1792" />
|
||||
<glyph unicode="∞" horiz-adv-x="1792" />
|
||||
<glyph unicode="≠" horiz-adv-x="1792" />
|
||||
<glyph unicode="" horiz-adv-x="500" d="M0 0z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1699 1350q0 -35 -43 -78l-632 -632v-768h320q26 0 45 -19t19 -45t-19 -45t-45 -19h-896q-26 0 -45 19t-19 45t19 45t45 19h320v768l-632 632q-43 43 -43 78q0 23 18 36.5t38 17.5t43 4h1408q23 0 43 -4t38 -17.5t18 -36.5z" />
|
||||
<glyph unicode="" d="M1536 1312v-1120q0 -50 -34 -89t-86 -60.5t-103.5 -32t-96.5 -10.5t-96.5 10.5t-103.5 32t-86 60.5t-34 89t34 89t86 60.5t103.5 32t96.5 10.5q105 0 192 -39v537l-768 -237v-709q0 -50 -34 -89t-86 -60.5t-103.5 -32t-96.5 -10.5t-96.5 10.5t-103.5 32t-86 60.5t-34 89 t34 89t86 60.5t103.5 32t96.5 10.5q105 0 192 -39v967q0 31 19 56.5t49 35.5l832 256q12 4 28 4q40 0 68 -28t28 -68z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1152 704q0 185 -131.5 316.5t-316.5 131.5t-316.5 -131.5t-131.5 -316.5t131.5 -316.5t316.5 -131.5t316.5 131.5t131.5 316.5zM1664 -128q0 -52 -38 -90t-90 -38q-54 0 -90 38l-343 342q-179 -124 -399 -124q-143 0 -273.5 55.5t-225 150t-150 225t-55.5 273.5 t55.5 273.5t150 225t225 150t273.5 55.5t273.5 -55.5t225 -150t150 -225t55.5 -273.5q0 -220 -124 -399l343 -343q37 -37 37 -90z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1664 32v768q-32 -36 -69 -66q-268 -206 -426 -338q-51 -43 -83 -67t-86.5 -48.5t-102.5 -24.5h-1h-1q-48 0 -102.5 24.5t-86.5 48.5t-83 67q-158 132 -426 338q-37 30 -69 66v-768q0 -13 9.5 -22.5t22.5 -9.5h1472q13 0 22.5 9.5t9.5 22.5zM1664 1083v11v13.5t-0.5 13 t-3 12.5t-5.5 9t-9 7.5t-14 2.5h-1472q-13 0 -22.5 -9.5t-9.5 -22.5q0 -168 147 -284q193 -152 401 -317q6 -5 35 -29.5t46 -37.5t44.5 -31.5t50.5 -27.5t43 -9h1h1q20 0 43 9t50.5 27.5t44.5 31.5t46 37.5t35 29.5q208 165 401 317q54 43 100.5 115.5t46.5 131.5z M1792 1120v-1088q0 -66 -47 -113t-113 -47h-1472q-66 0 -113 47t-47 113v1088q0 66 47 113t113 47h1472q66 0 113 -47t47 -113z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M896 -128q-26 0 -44 18l-624 602q-10 8 -27.5 26t-55.5 65.5t-68 97.5t-53.5 121t-23.5 138q0 220 127 344t351 124q62 0 126.5 -21.5t120 -58t95.5 -68.5t76 -68q36 36 76 68t95.5 68.5t120 58t126.5 21.5q224 0 351 -124t127 -344q0 -221 -229 -450l-623 -600 q-18 -18 -44 -18z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1664 889q0 -22 -26 -48l-363 -354l86 -500q1 -7 1 -20q0 -21 -10.5 -35.5t-30.5 -14.5q-19 0 -40 12l-449 236l-449 -236q-22 -12 -40 -12q-21 0 -31.5 14.5t-10.5 35.5q0 6 2 20l86 500l-364 354q-25 27 -25 48q0 37 56 46l502 73l225 455q19 41 49 41t49 -41l225 -455 l502 -73q56 -9 56 -46z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1137 532l306 297l-422 62l-189 382l-189 -382l-422 -62l306 -297l-73 -421l378 199l377 -199zM1664 889q0 -22 -26 -48l-363 -354l86 -500q1 -7 1 -20q0 -50 -41 -50q-19 0 -40 12l-449 236l-449 -236q-22 -12 -40 -12q-21 0 -31.5 14.5t-10.5 35.5q0 6 2 20l86 500 l-364 354q-25 27 -25 48q0 37 56 46l502 73l225 455q19 41 49 41t49 -41l225 -455l502 -73q56 -9 56 -46z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M1408 131q0 -120 -73 -189.5t-194 -69.5h-874q-121 0 -194 69.5t-73 189.5q0 53 3.5 103.5t14 109t26.5 108.5t43 97.5t62 81t85.5 53.5t111.5 20q9 0 42 -21.5t74.5 -48t108 -48t133.5 -21.5t133.5 21.5t108 48t74.5 48t42 21.5q61 0 111.5 -20t85.5 -53.5t62 -81 t43 -97.5t26.5 -108.5t14 -109t3.5 -103.5zM1088 1024q0 -159 -112.5 -271.5t-271.5 -112.5t-271.5 112.5t-112.5 271.5t112.5 271.5t271.5 112.5t271.5 -112.5t112.5 -271.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M384 -64v128q0 26 -19 45t-45 19h-128q-26 0 -45 -19t-19 -45v-128q0 -26 19 -45t45 -19h128q26 0 45 19t19 45zM384 320v128q0 26 -19 45t-45 19h-128q-26 0 -45 -19t-19 -45v-128q0 -26 19 -45t45 -19h128q26 0 45 19t19 45zM384 704v128q0 26 -19 45t-45 19h-128 q-26 0 -45 -19t-19 -45v-128q0 -26 19 -45t45 -19h128q26 0 45 19t19 45zM1408 -64v512q0 26 -19 45t-45 19h-768q-26 0 -45 -19t-19 -45v-512q0 -26 19 -45t45 -19h768q26 0 45 19t19 45zM384 1088v128q0 26 -19 45t-45 19h-128q-26 0 -45 -19t-19 -45v-128q0 -26 19 -45 t45 -19h128q26 0 45 19t19 45zM1792 -64v128q0 26 -19 45t-45 19h-128q-26 0 -45 -19t-19 -45v-128q0 -26 19 -45t45 -19h128q26 0 45 19t19 45zM1408 704v512q0 26 -19 45t-45 19h-768q-26 0 -45 -19t-19 -45v-512q0 -26 19 -45t45 -19h768q26 0 45 19t19 45zM1792 320v128 q0 26 -19 45t-45 19h-128q-26 0 -45 -19t-19 -45v-128q0 -26 19 -45t45 -19h128q26 0 45 19t19 45zM1792 704v128q0 26 -19 45t-45 19h-128q-26 0 -45 -19t-19 -45v-128q0 -26 19 -45t45 -19h128q26 0 45 19t19 45zM1792 1088v128q0 26 -19 45t-45 19h-128q-26 0 -45 -19 t-19 -45v-128q0 -26 19 -45t45 -19h128q26 0 45 19t19 45zM1920 1248v-1344q0 -66 -47 -113t-113 -47h-1600q-66 0 -113 47t-47 113v1344q0 66 47 113t113 47h1600q66 0 113 -47t47 -113z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M768 512v-384q0 -52 -38 -90t-90 -38h-512q-52 0 -90 38t-38 90v384q0 52 38 90t90 38h512q52 0 90 -38t38 -90zM768 1280v-384q0 -52 -38 -90t-90 -38h-512q-52 0 -90 38t-38 90v384q0 52 38 90t90 38h512q52 0 90 -38t38 -90zM1664 512v-384q0 -52 -38 -90t-90 -38 h-512q-52 0 -90 38t-38 90v384q0 52 38 90t90 38h512q52 0 90 -38t38 -90zM1664 1280v-384q0 -52 -38 -90t-90 -38h-512q-52 0 -90 38t-38 90v384q0 52 38 90t90 38h512q52 0 90 -38t38 -90z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M512 288v-192q0 -40 -28 -68t-68 -28h-320q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h320q40 0 68 -28t28 -68zM512 800v-192q0 -40 -28 -68t-68 -28h-320q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h320q40 0 68 -28t28 -68zM1152 288v-192q0 -40 -28 -68t-68 -28h-320 q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h320q40 0 68 -28t28 -68zM512 1312v-192q0 -40 -28 -68t-68 -28h-320q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h320q40 0 68 -28t28 -68zM1152 800v-192q0 -40 -28 -68t-68 -28h-320q-40 0 -68 28t-28 68v192q0 40 28 68t68 28 h320q40 0 68 -28t28 -68zM1792 288v-192q0 -40 -28 -68t-68 -28h-320q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h320q40 0 68 -28t28 -68zM1152 1312v-192q0 -40 -28 -68t-68 -28h-320q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h320q40 0 68 -28t28 -68zM1792 800v-192 q0 -40 -28 -68t-68 -28h-320q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h320q40 0 68 -28t28 -68zM1792 1312v-192q0 -40 -28 -68t-68 -28h-320q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h320q40 0 68 -28t28 -68z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M512 288v-192q0 -40 -28 -68t-68 -28h-320q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h320q40 0 68 -28t28 -68zM512 800v-192q0 -40 -28 -68t-68 -28h-320q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h320q40 0 68 -28t28 -68zM1792 288v-192q0 -40 -28 -68t-68 -28h-960 q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h960q40 0 68 -28t28 -68zM512 1312v-192q0 -40 -28 -68t-68 -28h-320q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h320q40 0 68 -28t28 -68zM1792 800v-192q0 -40 -28 -68t-68 -28h-960q-40 0 -68 28t-28 68v192q0 40 28 68t68 28 h960q40 0 68 -28t28 -68zM1792 1312v-192q0 -40 -28 -68t-68 -28h-960q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h960q40 0 68 -28t28 -68z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1671 970q0 -40 -28 -68l-724 -724l-136 -136q-28 -28 -68 -28t-68 28l-136 136l-362 362q-28 28 -28 68t28 68l136 136q28 28 68 28t68 -28l294 -295l656 657q28 28 68 28t68 -28l136 -136q28 -28 28 -68z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M1298 214q0 -40 -28 -68l-136 -136q-28 -28 -68 -28t-68 28l-294 294l-294 -294q-28 -28 -68 -28t-68 28l-136 136q-28 28 -28 68t28 68l294 294l-294 294q-28 28 -28 68t28 68l136 136q28 28 68 28t68 -28l294 -294l294 294q28 28 68 28t68 -28l136 -136q28 -28 28 -68 t-28 -68l-294 -294l294 -294q28 -28 28 -68z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1024 736v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-224v-224q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v224h-224q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h224v224q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5v-224h224 q13 0 22.5 -9.5t9.5 -22.5zM1152 704q0 185 -131.5 316.5t-316.5 131.5t-316.5 -131.5t-131.5 -316.5t131.5 -316.5t316.5 -131.5t316.5 131.5t131.5 316.5zM1664 -128q0 -53 -37.5 -90.5t-90.5 -37.5q-54 0 -90 38l-343 342q-179 -124 -399 -124q-143 0 -273.5 55.5 t-225 150t-150 225t-55.5 273.5t55.5 273.5t150 225t225 150t273.5 55.5t273.5 -55.5t225 -150t150 -225t55.5 -273.5q0 -220 -124 -399l343 -343q37 -37 37 -90z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1024 736v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-576q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h576q13 0 22.5 -9.5t9.5 -22.5zM1152 704q0 185 -131.5 316.5t-316.5 131.5t-316.5 -131.5t-131.5 -316.5t131.5 -316.5t316.5 -131.5t316.5 131.5t131.5 316.5z M1664 -128q0 -53 -37.5 -90.5t-90.5 -37.5q-54 0 -90 38l-343 342q-179 -124 -399 -124q-143 0 -273.5 55.5t-225 150t-150 225t-55.5 273.5t55.5 273.5t150 225t225 150t273.5 55.5t273.5 -55.5t225 -150t150 -225t55.5 -273.5q0 -220 -124 -399l343 -343q37 -37 37 -90z " />
|
||||
<glyph unicode="" d="M1536 640q0 -156 -61 -298t-164 -245t-245 -164t-298 -61t-298 61t-245 164t-164 245t-61 298q0 182 80.5 343t226.5 270q43 32 95.5 25t83.5 -50q32 -42 24.5 -94.5t-49.5 -84.5q-98 -74 -151.5 -181t-53.5 -228q0 -104 40.5 -198.5t109.5 -163.5t163.5 -109.5 t198.5 -40.5t198.5 40.5t163.5 109.5t109.5 163.5t40.5 198.5q0 121 -53.5 228t-151.5 181q-42 32 -49.5 84.5t24.5 94.5q31 43 84 50t95 -25q146 -109 226.5 -270t80.5 -343zM896 1408v-640q0 -52 -38 -90t-90 -38t-90 38t-38 90v640q0 52 38 90t90 38t90 -38t38 -90z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M256 96v-192q0 -14 -9 -23t-23 -9h-192q-14 0 -23 9t-9 23v192q0 14 9 23t23 9h192q14 0 23 -9t9 -23zM640 224v-320q0 -14 -9 -23t-23 -9h-192q-14 0 -23 9t-9 23v320q0 14 9 23t23 9h192q14 0 23 -9t9 -23zM1024 480v-576q0 -14 -9 -23t-23 -9h-192q-14 0 -23 9t-9 23 v576q0 14 9 23t23 9h192q14 0 23 -9t9 -23zM1408 864v-960q0 -14 -9 -23t-23 -9h-192q-14 0 -23 9t-9 23v960q0 14 9 23t23 9h192q14 0 23 -9t9 -23zM1792 1376v-1472q0 -14 -9 -23t-23 -9h-192q-14 0 -23 9t-9 23v1472q0 14 9 23t23 9h192q14 0 23 -9t9 -23z" />
|
||||
<glyph unicode="" d="M1024 640q0 106 -75 181t-181 75t-181 -75t-75 -181t75 -181t181 -75t181 75t75 181zM1536 749v-222q0 -12 -8 -23t-20 -13l-185 -28q-19 -54 -39 -91q35 -50 107 -138q10 -12 10 -25t-9 -23q-27 -37 -99 -108t-94 -71q-12 0 -26 9l-138 108q-44 -23 -91 -38 q-16 -136 -29 -186q-7 -28 -36 -28h-222q-14 0 -24.5 8.5t-11.5 21.5l-28 184q-49 16 -90 37l-141 -107q-10 -9 -25 -9q-14 0 -25 11q-126 114 -165 168q-7 10 -7 23q0 12 8 23q15 21 51 66.5t54 70.5q-27 50 -41 99l-183 27q-13 2 -21 12.5t-8 23.5v222q0 12 8 23t19 13 l186 28q14 46 39 92q-40 57 -107 138q-10 12 -10 24q0 10 9 23q26 36 98.5 107.5t94.5 71.5q13 0 26 -10l138 -107q44 23 91 38q16 136 29 186q7 28 36 28h222q14 0 24.5 -8.5t11.5 -21.5l28 -184q49 -16 90 -37l142 107q9 9 24 9q13 0 25 -10q129 -119 165 -170q7 -8 7 -22 q0 -12 -8 -23q-15 -21 -51 -66.5t-54 -70.5q26 -50 41 -98l183 -28q13 -2 21 -12.5t8 -23.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M512 800v-576q0 -14 -9 -23t-23 -9h-64q-14 0 -23 9t-9 23v576q0 14 9 23t23 9h64q14 0 23 -9t9 -23zM768 800v-576q0 -14 -9 -23t-23 -9h-64q-14 0 -23 9t-9 23v576q0 14 9 23t23 9h64q14 0 23 -9t9 -23zM1024 800v-576q0 -14 -9 -23t-23 -9h-64q-14 0 -23 9t-9 23v576 q0 14 9 23t23 9h64q14 0 23 -9t9 -23zM1152 76v948h-896v-948q0 -22 7 -40.5t14.5 -27t10.5 -8.5h832q3 0 10.5 8.5t14.5 27t7 40.5zM480 1152h448l-48 117q-7 9 -17 11h-317q-10 -2 -17 -11zM1408 1120v-64q0 -14 -9 -23t-23 -9h-96v-948q0 -83 -47 -143.5t-113 -60.5h-832 q-66 0 -113 58.5t-47 141.5v952h-96q-14 0 -23 9t-9 23v64q0 14 9 23t23 9h309l70 167q15 37 54 63t79 26h320q40 0 79 -26t54 -63l70 -167h309q14 0 23 -9t9 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1408 544v-480q0 -26 -19 -45t-45 -19h-384v384h-256v-384h-384q-26 0 -45 19t-19 45v480q0 1 0.5 3t0.5 3l575 474l575 -474q1 -2 1 -6zM1631 613l-62 -74q-8 -9 -21 -11h-3q-13 0 -21 7l-692 577l-692 -577q-12 -8 -24 -7q-13 2 -21 11l-62 74q-8 10 -7 23.5t11 21.5 l719 599q32 26 76 26t76 -26l244 -204v195q0 14 9 23t23 9h192q14 0 23 -9t9 -23v-408l219 -182q10 -8 11 -21.5t-7 -23.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1280" d="M128 0h1024v768h-416q-40 0 -68 28t-28 68v416h-512v-1280zM768 896h376q-10 29 -22 41l-313 313q-12 12 -41 22v-376zM1280 864v-896q0 -40 -28 -68t-68 -28h-1088q-40 0 -68 28t-28 68v1344q0 40 28 68t68 28h640q40 0 88 -20t76 -48l312 -312q28 -28 48 -76t20 -88z " />
|
||||
<glyph unicode="" d="M896 992v-448q0 -14 -9 -23t-23 -9h-320q-14 0 -23 9t-9 23v64q0 14 9 23t23 9h224v352q0 14 9 23t23 9h64q14 0 23 -9t9 -23zM1312 640q0 148 -73 273t-198 198t-273 73t-273 -73t-198 -198t-73 -273t73 -273t198 -198t273 -73t273 73t198 198t73 273zM1536 640 q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M1111 540v4l-24 320q-1 13 -11 22.5t-23 9.5h-186q-13 0 -23 -9.5t-11 -22.5l-24 -320v-4q-1 -12 8 -20t21 -8h244q12 0 21 8t8 20zM1870 73q0 -73 -46 -73h-704q13 0 22 9.5t8 22.5l-20 256q-1 13 -11 22.5t-23 9.5h-272q-13 0 -23 -9.5t-11 -22.5l-20 -256 q-1 -13 8 -22.5t22 -9.5h-704q-46 0 -46 73q0 54 26 116l417 1044q8 19 26 33t38 14h339q-13 0 -23 -9.5t-11 -22.5l-15 -192q-1 -14 8 -23t22 -9h166q13 0 22 9t8 23l-15 192q-1 13 -11 22.5t-23 9.5h339q20 0 38 -14t26 -33l417 -1044q26 -62 26 -116z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1280 192q0 26 -19 45t-45 19t-45 -19t-19 -45t19 -45t45 -19t45 19t19 45zM1536 192q0 26 -19 45t-45 19t-45 -19t-19 -45t19 -45t45 -19t45 19t19 45zM1664 416v-320q0 -40 -28 -68t-68 -28h-1472q-40 0 -68 28t-28 68v320q0 40 28 68t68 28h465l135 -136 q58 -56 136 -56t136 56l136 136h464q40 0 68 -28t28 -68zM1339 985q17 -41 -14 -70l-448 -448q-18 -19 -45 -19t-45 19l-448 448q-31 29 -14 70q17 39 59 39h256v448q0 26 19 45t45 19h256q26 0 45 -19t19 -45v-448h256q42 0 59 -39z" />
|
||||
<glyph unicode="" d="M1120 608q0 -12 -10 -24l-319 -319q-11 -9 -23 -9t-23 9l-320 320q-15 16 -7 35q8 20 30 20h192v352q0 14 9 23t23 9h192q14 0 23 -9t9 -23v-352h192q14 0 23 -9t9 -23zM768 1184q-148 0 -273 -73t-198 -198t-73 -273t73 -273t198 -198t273 -73t273 73t198 198t73 273 t-73 273t-198 198t-273 73zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M1118 660q-8 -20 -30 -20h-192v-352q0 -14 -9 -23t-23 -9h-192q-14 0 -23 9t-9 23v352h-192q-14 0 -23 9t-9 23q0 12 10 24l319 319q11 9 23 9t23 -9l320 -320q15 -16 7 -35zM768 1184q-148 0 -273 -73t-198 -198t-73 -273t73 -273t198 -198t273 -73t273 73t198 198 t73 273t-73 273t-198 198t-273 73zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M1023 576h316q-1 3 -2.5 8t-2.5 8l-212 496h-708l-212 -496q-1 -2 -2.5 -8t-2.5 -8h316l95 -192h320zM1536 546v-482q0 -26 -19 -45t-45 -19h-1408q-26 0 -45 19t-19 45v482q0 62 25 123l238 552q10 25 36.5 42t52.5 17h832q26 0 52.5 -17t36.5 -42l238 -552 q25 -61 25 -123z" />
|
||||
<glyph unicode="" d="M1184 640q0 -37 -32 -55l-544 -320q-15 -9 -32 -9q-16 0 -32 8q-32 19 -32 56v640q0 37 32 56q33 18 64 -1l544 -320q32 -18 32 -55zM1312 640q0 148 -73 273t-198 198t-273 73t-273 -73t-198 -198t-73 -273t73 -273t198 -198t273 -73t273 73t198 198t73 273zM1536 640 q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M1536 1280v-448q0 -26 -19 -45t-45 -19h-448q-42 0 -59 40q-17 39 14 69l138 138q-148 137 -349 137q-104 0 -198.5 -40.5t-163.5 -109.5t-109.5 -163.5t-40.5 -198.5t40.5 -198.5t109.5 -163.5t163.5 -109.5t198.5 -40.5q119 0 225 52t179 147q7 10 23 12q14 0 25 -9 l137 -138q9 -8 9.5 -20.5t-7.5 -22.5q-109 -132 -264 -204.5t-327 -72.5q-156 0 -298 61t-245 164t-164 245t-61 298t61 298t164 245t245 164t298 61q147 0 284.5 -55.5t244.5 -156.5l130 129q29 31 70 14q39 -17 39 -59z" />
|
||||
<glyph unicode="" d="M1511 480q0 -5 -1 -7q-64 -268 -268 -434.5t-478 -166.5q-146 0 -282.5 55t-243.5 157l-129 -129q-19 -19 -45 -19t-45 19t-19 45v448q0 26 19 45t45 19h448q26 0 45 -19t19 -45t-19 -45l-137 -137q71 -66 161 -102t187 -36q134 0 250 65t186 179q11 17 53 117 q8 23 30 23h192q13 0 22.5 -9.5t9.5 -22.5zM1536 1280v-448q0 -26 -19 -45t-45 -19h-448q-26 0 -45 19t-19 45t19 45l138 138q-148 137 -349 137q-134 0 -250 -65t-186 -179q-11 -17 -53 -117q-8 -23 -30 -23h-199q-13 0 -22.5 9.5t-9.5 22.5v7q65 268 270 434.5t480 166.5 q146 0 284 -55.5t245 -156.5l130 129q19 19 45 19t45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M384 352v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5zM384 608v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5z M384 864v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5zM1536 352v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-960q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h960q13 0 22.5 -9.5t9.5 -22.5z M1536 608v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-960q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h960q13 0 22.5 -9.5t9.5 -22.5zM1536 864v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-960q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h960q13 0 22.5 -9.5 t9.5 -22.5zM1664 160v832q0 13 -9.5 22.5t-22.5 9.5h-1472q-13 0 -22.5 -9.5t-9.5 -22.5v-832q0 -13 9.5 -22.5t22.5 -9.5h1472q13 0 22.5 9.5t9.5 22.5zM1792 1248v-1088q0 -66 -47 -113t-113 -47h-1472q-66 0 -113 47t-47 113v1088q0 66 47 113t113 47h1472q66 0 113 -47 t47 -113z" />
|
||||
<glyph unicode="" horiz-adv-x="1152" d="M320 768h512v192q0 106 -75 181t-181 75t-181 -75t-75 -181v-192zM1152 672v-576q0 -40 -28 -68t-68 -28h-960q-40 0 -68 28t-28 68v576q0 40 28 68t68 28h32v192q0 184 132 316t316 132t316 -132t132 -316v-192h32q40 0 68 -28t28 -68z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M320 1280q0 -72 -64 -110v-1266q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v1266q-64 38 -64 110q0 53 37.5 90.5t90.5 37.5t90.5 -37.5t37.5 -90.5zM1792 1216v-763q0 -25 -12.5 -38.5t-39.5 -27.5q-215 -116 -369 -116q-61 0 -123.5 22t-108.5 48 t-115.5 48t-142.5 22q-192 0 -464 -146q-17 -9 -33 -9q-26 0 -45 19t-19 45v742q0 32 31 55q21 14 79 43q236 120 421 120q107 0 200 -29t219 -88q38 -19 88 -19q54 0 117.5 21t110 47t88 47t54.5 21q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1664 650q0 -166 -60 -314l-20 -49l-185 -33q-22 -83 -90.5 -136.5t-156.5 -53.5v-32q0 -14 -9 -23t-23 -9h-64q-14 0 -23 9t-9 23v576q0 14 9 23t23 9h64q14 0 23 -9t9 -23v-32q71 0 130 -35.5t93 -95.5l68 12q29 95 29 193q0 148 -88 279t-236.5 209t-315.5 78 t-315.5 -78t-236.5 -209t-88 -279q0 -98 29 -193l68 -12q34 60 93 95.5t130 35.5v32q0 14 9 23t23 9h64q14 0 23 -9t9 -23v-576q0 -14 -9 -23t-23 -9h-64q-14 0 -23 9t-9 23v32q-88 0 -156.5 53.5t-90.5 136.5l-185 33l-20 49q-60 148 -60 314q0 151 67 291t179 242.5 t266 163.5t320 61t320 -61t266 -163.5t179 -242.5t67 -291z" />
|
||||
<glyph unicode="" horiz-adv-x="768" d="M768 1184v-1088q0 -26 -19 -45t-45 -19t-45 19l-333 333h-262q-26 0 -45 19t-19 45v384q0 26 19 45t45 19h262l333 333q19 19 45 19t45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1152" d="M768 1184v-1088q0 -26 -19 -45t-45 -19t-45 19l-333 333h-262q-26 0 -45 19t-19 45v384q0 26 19 45t45 19h262l333 333q19 19 45 19t45 -19t19 -45zM1152 640q0 -76 -42.5 -141.5t-112.5 -93.5q-10 -5 -25 -5q-26 0 -45 18.5t-19 45.5q0 21 12 35.5t29 25t34 23t29 35.5 t12 57t-12 57t-29 35.5t-34 23t-29 25t-12 35.5q0 27 19 45.5t45 18.5q15 0 25 -5q70 -27 112.5 -93t42.5 -142z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M768 1184v-1088q0 -26 -19 -45t-45 -19t-45 19l-333 333h-262q-26 0 -45 19t-19 45v384q0 26 19 45t45 19h262l333 333q19 19 45 19t45 -19t19 -45zM1152 640q0 -76 -42.5 -141.5t-112.5 -93.5q-10 -5 -25 -5q-26 0 -45 18.5t-19 45.5q0 21 12 35.5t29 25t34 23t29 35.5 t12 57t-12 57t-29 35.5t-34 23t-29 25t-12 35.5q0 27 19 45.5t45 18.5q15 0 25 -5q70 -27 112.5 -93t42.5 -142zM1408 640q0 -153 -85 -282.5t-225 -188.5q-13 -5 -25 -5q-27 0 -46 19t-19 45q0 39 39 59q56 29 76 44q74 54 115.5 135.5t41.5 173.5t-41.5 173.5 t-115.5 135.5q-20 15 -76 44q-39 20 -39 59q0 26 19 45t45 19q13 0 26 -5q140 -59 225 -188.5t85 -282.5zM1664 640q0 -230 -127 -422.5t-338 -283.5q-13 -5 -26 -5q-26 0 -45 19t-19 45q0 36 39 59q7 4 22.5 10.5t22.5 10.5q46 25 82 51q123 91 192 227t69 289t-69 289 t-192 227q-36 26 -82 51q-7 4 -22.5 10.5t-22.5 10.5q-39 23 -39 59q0 26 19 45t45 19q13 0 26 -5q211 -91 338 -283.5t127 -422.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M384 384v-128h-128v128h128zM384 1152v-128h-128v128h128zM1152 1152v-128h-128v128h128zM128 129h384v383h-384v-383zM128 896h384v384h-384v-384zM896 896h384v384h-384v-384zM640 640v-640h-640v640h640zM1152 128v-128h-128v128h128zM1408 128v-128h-128v128h128z M1408 640v-384h-384v128h-128v-384h-128v640h384v-128h128v128h128zM640 1408v-640h-640v640h640zM1408 1408v-640h-640v640h640z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M63 0h-63v1408h63v-1408zM126 1h-32v1407h32v-1407zM220 1h-31v1407h31v-1407zM377 1h-31v1407h31v-1407zM534 1h-62v1407h62v-1407zM660 1h-31v1407h31v-1407zM723 1h-31v1407h31v-1407zM786 1h-31v1407h31v-1407zM943 1h-63v1407h63v-1407zM1100 1h-63v1407h63v-1407z M1226 1h-63v1407h63v-1407zM1352 1h-63v1407h63v-1407zM1446 1h-63v1407h63v-1407zM1635 1h-94v1407h94v-1407zM1698 1h-32v1407h32v-1407zM1792 0h-63v1408h63v-1408z" />
|
||||
<glyph unicode="" d="M448 1088q0 53 -37.5 90.5t-90.5 37.5t-90.5 -37.5t-37.5 -90.5t37.5 -90.5t90.5 -37.5t90.5 37.5t37.5 90.5zM1515 512q0 -53 -37 -90l-491 -492q-39 -37 -91 -37q-53 0 -90 37l-715 716q-38 37 -64.5 101t-26.5 117v416q0 52 38 90t90 38h416q53 0 117 -26.5t102 -64.5 l715 -714q37 -39 37 -91z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M448 1088q0 53 -37.5 90.5t-90.5 37.5t-90.5 -37.5t-37.5 -90.5t37.5 -90.5t90.5 -37.5t90.5 37.5t37.5 90.5zM1515 512q0 -53 -37 -90l-491 -492q-39 -37 -91 -37q-53 0 -90 37l-715 716q-38 37 -64.5 101t-26.5 117v416q0 52 38 90t90 38h416q53 0 117 -26.5t102 -64.5 l715 -714q37 -39 37 -91zM1899 512q0 -53 -37 -90l-491 -492q-39 -37 -91 -37q-36 0 -59 14t-53 45l470 470q37 37 37 90q0 52 -37 91l-715 714q-38 38 -102 64.5t-117 26.5h224q53 0 117 -26.5t102 -64.5l715 -714q37 -39 37 -91z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1639 1058q40 -57 18 -129l-275 -906q-19 -64 -76.5 -107.5t-122.5 -43.5h-923q-77 0 -148.5 53.5t-99.5 131.5q-24 67 -2 127q0 4 3 27t4 37q1 8 -3 21.5t-3 19.5q2 11 8 21t16.5 23.5t16.5 23.5q23 38 45 91.5t30 91.5q3 10 0.5 30t-0.5 28q3 11 17 28t17 23 q21 36 42 92t25 90q1 9 -2.5 32t0.5 28q4 13 22 30.5t22 22.5q19 26 42.5 84.5t27.5 96.5q1 8 -3 25.5t-2 26.5q2 8 9 18t18 23t17 21q8 12 16.5 30.5t15 35t16 36t19.5 32t26.5 23.5t36 11.5t47.5 -5.5l-1 -3q38 9 51 9h761q74 0 114 -56t18 -130l-274 -906 q-36 -119 -71.5 -153.5t-128.5 -34.5h-869q-27 0 -38 -15q-11 -16 -1 -43q24 -70 144 -70h923q29 0 56 15.5t35 41.5l300 987q7 22 5 57q38 -15 59 -43zM575 1056q-4 -13 2 -22.5t20 -9.5h608q13 0 25.5 9.5t16.5 22.5l21 64q4 13 -2 22.5t-20 9.5h-608q-13 0 -25.5 -9.5 t-16.5 -22.5zM492 800q-4 -13 2 -22.5t20 -9.5h608q13 0 25.5 9.5t16.5 22.5l21 64q4 13 -2 22.5t-20 9.5h-608q-13 0 -25.5 -9.5t-16.5 -22.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1280" d="M1164 1408q23 0 44 -9q33 -13 52.5 -41t19.5 -62v-1289q0 -34 -19.5 -62t-52.5 -41q-19 -8 -44 -8q-48 0 -83 32l-441 424l-441 -424q-36 -33 -83 -33q-23 0 -44 9q-33 13 -52.5 41t-19.5 62v1289q0 34 19.5 62t52.5 41q21 9 44 9h1048z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M384 0h896v256h-896v-256zM384 640h896v384h-160q-40 0 -68 28t-28 68v160h-640v-640zM1536 576q0 26 -19 45t-45 19t-45 -19t-19 -45t19 -45t45 -19t45 19t19 45zM1664 576v-416q0 -13 -9.5 -22.5t-22.5 -9.5h-224v-160q0 -40 -28 -68t-68 -28h-960q-40 0 -68 28t-28 68 v160h-224q-13 0 -22.5 9.5t-9.5 22.5v416q0 79 56.5 135.5t135.5 56.5h64v544q0 40 28 68t68 28h672q40 0 88 -20t76 -48l152 -152q28 -28 48 -76t20 -88v-256h64q79 0 135.5 -56.5t56.5 -135.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M960 864q119 0 203.5 -84.5t84.5 -203.5t-84.5 -203.5t-203.5 -84.5t-203.5 84.5t-84.5 203.5t84.5 203.5t203.5 84.5zM1664 1280q106 0 181 -75t75 -181v-896q0 -106 -75 -181t-181 -75h-1408q-106 0 -181 75t-75 181v896q0 106 75 181t181 75h224l51 136 q19 49 69.5 84.5t103.5 35.5h512q53 0 103.5 -35.5t69.5 -84.5l51 -136h224zM960 128q185 0 316.5 131.5t131.5 316.5t-131.5 316.5t-316.5 131.5t-316.5 -131.5t-131.5 -316.5t131.5 -316.5t316.5 -131.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M725 977l-170 -450q73 -1 153.5 -2t119 -1.5t52.5 -0.5l29 2q-32 95 -92 241q-53 132 -92 211zM21 -128h-21l2 79q22 7 80 18q89 16 110 31q20 16 48 68l237 616l280 724h75h53l11 -21l205 -480q103 -242 124 -297q39 -102 96 -235q26 -58 65 -164q24 -67 65 -149 q22 -49 35 -57q22 -19 69 -23q47 -6 103 -27q6 -39 6 -57q0 -14 -1 -26q-80 0 -192 8q-93 8 -189 8q-79 0 -135 -2l-200 -11l-58 -2q0 45 4 78l131 28q56 13 68 23q12 12 12 27t-6 32l-47 114l-92 228l-450 2q-29 -65 -104 -274q-23 -64 -23 -84q0 -31 17 -43 q26 -21 103 -32q3 0 13.5 -2t30 -5t40.5 -6q1 -28 1 -58q0 -17 -2 -27q-66 0 -349 20l-48 -8q-81 -14 -167 -14z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M555 15q76 -32 140 -32q131 0 216 41t122 113q38 70 38 181q0 114 -41 180q-58 94 -141 126q-80 32 -247 32q-74 0 -101 -10v-144l-1 -173l3 -270q0 -15 12 -44zM541 761q43 -7 109 -7q175 0 264 65t89 224q0 112 -85 187q-84 75 -255 75q-52 0 -130 -13q0 -44 2 -77 q7 -122 6 -279l-1 -98q0 -43 1 -77zM0 -128l2 94q45 9 68 12q77 12 123 31q17 27 21 51q9 66 9 194l-2 497q-5 256 -9 404q-1 87 -11 109q-1 4 -12 12q-18 12 -69 15q-30 2 -114 13l-4 83l260 6l380 13l45 1q5 0 14 0.5t14 0.5q1 0 21.5 -0.5t40.5 -0.5h74q88 0 191 -27 q43 -13 96 -39q57 -29 102 -76q44 -47 65 -104t21 -122q0 -70 -32 -128t-95 -105q-26 -20 -150 -77q177 -41 267 -146q92 -106 92 -236q0 -76 -29 -161q-21 -62 -71 -117q-66 -72 -140 -108q-73 -36 -203 -60q-82 -15 -198 -11l-197 4q-84 2 -298 -11q-33 -3 -272 -11z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M0 -126l17 85q4 1 77 20q76 19 116 39q29 37 41 101l27 139l56 268l12 64q8 44 17 84.5t16 67t12.5 46.5t9 30.5t3.5 11.5l29 157l16 63l22 135l8 50v38q-41 22 -144 28q-28 2 -38 4l19 103l317 -14q39 -2 73 -2q66 0 214 9q33 2 68 4.5t36 2.5q-2 -19 -6 -38 q-7 -29 -13 -51q-55 -19 -109 -31q-64 -16 -101 -31q-12 -31 -24 -88q-9 -44 -13 -82q-44 -199 -66 -306l-61 -311l-38 -158l-43 -235l-12 -45q-2 -7 1 -27q64 -15 119 -21q36 -5 66 -10q-1 -29 -7 -58q-7 -31 -9 -41q-18 0 -23 -1q-24 -2 -42 -2q-9 0 -28 3q-19 4 -145 17 l-198 2q-41 1 -174 -11q-74 -7 -98 -9z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M81 1407l54 -27q20 -5 211 -5h130l19 3l115 1l215 -1h293l34 -2q14 -1 28 7t21 16l7 8l42 1q15 0 28 -1v-104.5t1 -131.5l1 -100l-1 -58q0 -32 -4 -51q-39 -15 -68 -18q-25 43 -54 128q-8 24 -15.5 62.5t-11.5 65.5t-6 29q-13 15 -27 19q-7 2 -42.5 2t-103.5 -1t-111 -1 q-34 0 -67 -5q-10 -97 -8 -136l1 -152v-332l3 -359l-1 -147q-1 -46 11 -85q49 -25 89 -32q2 0 18 -5t44 -13t43 -12q30 -8 50 -18q5 -45 5 -50q0 -10 -3 -29q-14 -1 -34 -1q-110 0 -187 10q-72 8 -238 8q-88 0 -233 -14q-48 -4 -70 -4q-2 22 -2 26l-1 26v9q21 33 79 49 q139 38 159 50q9 21 12 56q8 192 6 433l-5 428q-1 62 -0.5 118.5t0.5 102.5t-2 57t-6 15q-6 5 -14 6q-38 6 -148 6q-43 0 -100 -13.5t-73 -24.5q-13 -9 -22 -33t-22 -75t-24 -84q-6 -19 -19.5 -32t-20.5 -13q-44 27 -56 44v297v86zM1744 128q33 0 42 -18.5t-11 -44.5 l-126 -162q-20 -26 -49 -26t-49 26l-126 162q-20 26 -11 44.5t42 18.5h80v1024h-80q-33 0 -42 18.5t11 44.5l126 162q20 26 49 26t49 -26l126 -162q20 -26 11 -44.5t-42 -18.5h-80v-1024h80z" />
|
||||
<glyph unicode="" d="M81 1407l54 -27q20 -5 211 -5h130l19 3l115 1l446 -1h318l34 -2q14 -1 28 7t21 16l7 8l42 1q15 0 28 -1v-104.5t1 -131.5l1 -100l-1 -58q0 -32 -4 -51q-39 -15 -68 -18q-25 43 -54 128q-8 24 -15.5 62.5t-11.5 65.5t-6 29q-13 15 -27 19q-7 2 -58.5 2t-138.5 -1t-128 -1 q-94 0 -127 -5q-10 -97 -8 -136l1 -152v52l3 -359l-1 -147q-1 -46 11 -85q49 -25 89 -32q2 0 18 -5t44 -13t43 -12q30 -8 50 -18q5 -45 5 -50q0 -10 -3 -29q-14 -1 -34 -1q-110 0 -187 10q-72 8 -238 8q-82 0 -233 -13q-45 -5 -70 -5q-2 22 -2 26l-1 26v9q21 33 79 49 q139 38 159 50q9 21 12 56q6 137 6 433l-5 44q0 265 -2 278q-2 11 -6 15q-6 5 -14 6q-38 6 -148 6q-50 0 -168.5 -14t-132.5 -24q-13 -9 -22 -33t-22 -75t-24 -84q-6 -19 -19.5 -32t-20.5 -13q-44 27 -56 44v297v86zM1505 113q26 -20 26 -49t-26 -49l-162 -126 q-26 -20 -44.5 -11t-18.5 42v80h-1024v-80q0 -33 -18.5 -42t-44.5 11l-162 126q-26 20 -26 49t26 49l162 126q26 20 44.5 11t18.5 -42v-80h1024v80q0 33 18.5 42t44.5 -11z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1792 192v-128q0 -26 -19 -45t-45 -19h-1664q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h1664q26 0 45 -19t19 -45zM1408 576v-128q0 -26 -19 -45t-45 -19h-1280q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h1280q26 0 45 -19t19 -45zM1664 960v-128q0 -26 -19 -45 t-45 -19h-1536q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h1536q26 0 45 -19t19 -45zM1280 1344v-128q0 -26 -19 -45t-45 -19h-1152q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h1152q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1792 192v-128q0 -26 -19 -45t-45 -19h-1664q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h1664q26 0 45 -19t19 -45zM1408 576v-128q0 -26 -19 -45t-45 -19h-896q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h896q26 0 45 -19t19 -45zM1664 960v-128q0 -26 -19 -45t-45 -19 h-1408q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h1408q26 0 45 -19t19 -45zM1280 1344v-128q0 -26 -19 -45t-45 -19h-640q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h640q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1792 192v-128q0 -26 -19 -45t-45 -19h-1664q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h1664q26 0 45 -19t19 -45zM1792 576v-128q0 -26 -19 -45t-45 -19h-1280q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h1280q26 0 45 -19t19 -45zM1792 960v-128q0 -26 -19 -45 t-45 -19h-1536q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h1536q26 0 45 -19t19 -45zM1792 1344v-128q0 -26 -19 -45t-45 -19h-1152q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h1152q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1792 192v-128q0 -26 -19 -45t-45 -19h-1664q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h1664q26 0 45 -19t19 -45zM1792 576v-128q0 -26 -19 -45t-45 -19h-1664q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h1664q26 0 45 -19t19 -45zM1792 960v-128q0 -26 -19 -45 t-45 -19h-1664q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h1664q26 0 45 -19t19 -45zM1792 1344v-128q0 -26 -19 -45t-45 -19h-1664q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h1664q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M256 224v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-192q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5t22.5 9.5h192q13 0 22.5 -9.5t9.5 -22.5zM256 608v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-192q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5t22.5 9.5h192q13 0 22.5 -9.5 t9.5 -22.5zM256 992v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-192q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5t22.5 9.5h192q13 0 22.5 -9.5t9.5 -22.5zM1792 224v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-1344q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5t22.5 9.5h1344 q13 0 22.5 -9.5t9.5 -22.5zM256 1376v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-192q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5t22.5 9.5h192q13 0 22.5 -9.5t9.5 -22.5zM1792 608v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-1344q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5 t22.5 9.5h1344q13 0 22.5 -9.5t9.5 -22.5zM1792 992v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-1344q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5t22.5 9.5h1344q13 0 22.5 -9.5t9.5 -22.5zM1792 1376v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-1344q-13 0 -22.5 9.5t-9.5 22.5v192 q0 13 9.5 22.5t22.5 9.5h1344q13 0 22.5 -9.5t9.5 -22.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M384 992v-576q0 -13 -9.5 -22.5t-22.5 -9.5q-14 0 -23 9l-288 288q-9 9 -9 23t9 23l288 288q9 9 23 9q13 0 22.5 -9.5t9.5 -22.5zM1792 224v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-1728q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5t22.5 9.5h1728q13 0 22.5 -9.5 t9.5 -22.5zM1792 608v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-1088q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5t22.5 9.5h1088q13 0 22.5 -9.5t9.5 -22.5zM1792 992v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-1088q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5t22.5 9.5h1088 q13 0 22.5 -9.5t9.5 -22.5zM1792 1376v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-1728q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5t22.5 9.5h1728q13 0 22.5 -9.5t9.5 -22.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M352 704q0 -14 -9 -23l-288 -288q-9 -9 -23 -9q-13 0 -22.5 9.5t-9.5 22.5v576q0 13 9.5 22.5t22.5 9.5q14 0 23 -9l288 -288q9 -9 9 -23zM1792 224v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-1728q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5t22.5 9.5h1728q13 0 22.5 -9.5 t9.5 -22.5zM1792 608v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-1088q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5t22.5 9.5h1088q13 0 22.5 -9.5t9.5 -22.5zM1792 992v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-1088q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5t22.5 9.5h1088 q13 0 22.5 -9.5t9.5 -22.5zM1792 1376v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-1728q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5t22.5 9.5h1728q13 0 22.5 -9.5t9.5 -22.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1792 1184v-1088q0 -42 -39 -59q-13 -5 -25 -5q-27 0 -45 19l-403 403v-166q0 -119 -84.5 -203.5t-203.5 -84.5h-704q-119 0 -203.5 84.5t-84.5 203.5v704q0 119 84.5 203.5t203.5 84.5h704q119 0 203.5 -84.5t84.5 -203.5v-165l403 402q18 19 45 19q12 0 25 -5 q39 -17 39 -59z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M640 960q0 -80 -56 -136t-136 -56t-136 56t-56 136t56 136t136 56t136 -56t56 -136zM1664 576v-448h-1408v192l320 320l160 -160l512 512zM1760 1280h-1600q-13 0 -22.5 -9.5t-9.5 -22.5v-1216q0 -13 9.5 -22.5t22.5 -9.5h1600q13 0 22.5 9.5t9.5 22.5v1216 q0 13 -9.5 22.5t-22.5 9.5zM1920 1248v-1216q0 -66 -47 -113t-113 -47h-1600q-66 0 -113 47t-47 113v1216q0 66 47 113t113 47h1600q66 0 113 -47t47 -113z" />
|
||||
<glyph unicode="" d="M363 0l91 91l-235 235l-91 -91v-107h128v-128h107zM886 928q0 22 -22 22q-10 0 -17 -7l-542 -542q-7 -7 -7 -17q0 -22 22 -22q10 0 17 7l542 542q7 7 7 17zM832 1120l416 -416l-832 -832h-416v416zM1515 1024q0 -53 -37 -90l-166 -166l-416 416l166 165q36 38 90 38 q53 0 91 -38l235 -234q37 -39 37 -91z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M768 896q0 106 -75 181t-181 75t-181 -75t-75 -181t75 -181t181 -75t181 75t75 181zM1024 896q0 -109 -33 -179l-364 -774q-16 -33 -47.5 -52t-67.5 -19t-67.5 19t-46.5 52l-365 774q-33 70 -33 179q0 212 150 362t362 150t362 -150t150 -362z" />
|
||||
<glyph unicode="" d="M768 96v1088q-148 0 -273 -73t-198 -198t-73 -273t73 -273t198 -198t273 -73zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M512 384q0 36 -20 69q-1 1 -15.5 22.5t-25.5 38t-25 44t-21 50.5q-4 16 -21 16t-21 -16q-7 -23 -21 -50.5t-25 -44t-25.5 -38t-15.5 -22.5q-20 -33 -20 -69q0 -53 37.5 -90.5t90.5 -37.5t90.5 37.5t37.5 90.5zM1024 512q0 -212 -150 -362t-362 -150t-362 150t-150 362 q0 145 81 275q6 9 62.5 90.5t101 151t99.5 178t83 201.5q9 30 34 47t51 17t51.5 -17t33.5 -47q28 -93 83 -201.5t99.5 -178t101 -151t62.5 -90.5q81 -127 81 -275z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M888 352l116 116l-152 152l-116 -116v-56h96v-96h56zM1328 1072q-16 16 -33 -1l-350 -350q-17 -17 -1 -33t33 1l350 350q17 17 1 33zM1408 478v-190q0 -119 -84.5 -203.5t-203.5 -84.5h-832q-119 0 -203.5 84.5t-84.5 203.5v832q0 119 84.5 203.5t203.5 84.5h832 q63 0 117 -25q15 -7 18 -23q3 -17 -9 -29l-49 -49q-14 -14 -32 -8q-23 6 -45 6h-832q-66 0 -113 -47t-47 -113v-832q0 -66 47 -113t113 -47h832q66 0 113 47t47 113v126q0 13 9 22l64 64q15 15 35 7t20 -29zM1312 1216l288 -288l-672 -672h-288v288zM1756 1084l-92 -92 l-288 288l92 92q28 28 68 28t68 -28l152 -152q28 -28 28 -68t-28 -68z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1408 547v-259q0 -119 -84.5 -203.5t-203.5 -84.5h-832q-119 0 -203.5 84.5t-84.5 203.5v832q0 119 84.5 203.5t203.5 84.5h255v0q13 0 22.5 -9.5t9.5 -22.5q0 -27 -26 -32q-77 -26 -133 -60q-10 -4 -16 -4h-112q-66 0 -113 -47t-47 -113v-832q0 -66 47 -113t113 -47h832 q66 0 113 47t47 113v214q0 19 18 29q28 13 54 37q16 16 35 8q21 -9 21 -29zM1645 1043l-384 -384q-18 -19 -45 -19q-12 0 -25 5q-39 17 -39 59v192h-160q-323 0 -438 -131q-119 -137 -74 -473q3 -23 -20 -34q-8 -2 -12 -2q-16 0 -26 13q-10 14 -21 31t-39.5 68.5t-49.5 99.5 t-38.5 114t-17.5 122q0 49 3.5 91t14 90t28 88t47 81.5t68.5 74t94.5 61.5t124.5 48.5t159.5 30.5t196.5 11h160v192q0 42 39 59q13 5 25 5q26 0 45 -19l384 -384q19 -19 19 -45t-19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1408 606v-318q0 -119 -84.5 -203.5t-203.5 -84.5h-832q-119 0 -203.5 84.5t-84.5 203.5v832q0 119 84.5 203.5t203.5 84.5h832q63 0 117 -25q15 -7 18 -23q3 -17 -9 -29l-49 -49q-10 -10 -23 -10q-3 0 -9 2q-23 6 -45 6h-832q-66 0 -113 -47t-47 -113v-832 q0 -66 47 -113t113 -47h832q66 0 113 47t47 113v254q0 13 9 22l64 64q10 10 23 10q6 0 12 -3q20 -8 20 -29zM1639 1095l-814 -814q-24 -24 -57 -24t-57 24l-430 430q-24 24 -24 57t24 57l110 110q24 24 57 24t57 -24l263 -263l647 647q24 24 57 24t57 -24l110 -110 q24 -24 24 -57t-24 -57z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1792 640q0 -26 -19 -45l-256 -256q-19 -19 -45 -19t-45 19t-19 45v128h-384v-384h128q26 0 45 -19t19 -45t-19 -45l-256 -256q-19 -19 -45 -19t-45 19l-256 256q-19 19 -19 45t19 45t45 19h128v384h-384v-128q0 -26 -19 -45t-45 -19t-45 19l-256 256q-19 19 -19 45 t19 45l256 256q19 19 45 19t45 -19t19 -45v-128h384v384h-128q-26 0 -45 19t-19 45t19 45l256 256q19 19 45 19t45 -19l256 -256q19 -19 19 -45t-19 -45t-45 -19h-128v-384h384v128q0 26 19 45t45 19t45 -19l256 -256q19 -19 19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M979 1395q19 19 32 13t13 -32v-1472q0 -26 -13 -32t-32 13l-710 710q-9 9 -13 19v-678q0 -26 -19 -45t-45 -19h-128q-26 0 -45 19t-19 45v1408q0 26 19 45t45 19h128q26 0 45 -19t19 -45v-678q4 11 13 19z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1747 1395q19 19 32 13t13 -32v-1472q0 -26 -13 -32t-32 13l-710 710q-9 9 -13 19v-710q0 -26 -13 -32t-32 13l-710 710q-9 9 -13 19v-678q0 -26 -19 -45t-45 -19h-128q-26 0 -45 19t-19 45v1408q0 26 19 45t45 19h128q26 0 45 -19t19 -45v-678q4 11 13 19l710 710 q19 19 32 13t13 -32v-710q4 11 13 19z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1619 1395q19 19 32 13t13 -32v-1472q0 -26 -13 -32t-32 13l-710 710q-8 9 -13 19v-710q0 -26 -13 -32t-32 13l-710 710q-19 19 -19 45t19 45l710 710q19 19 32 13t13 -32v-710q5 11 13 19z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M1384 609l-1328 -738q-23 -13 -39.5 -3t-16.5 36v1472q0 26 16.5 36t39.5 -3l1328 -738q23 -13 23 -31t-23 -31z" />
|
||||
<glyph unicode="" d="M1536 1344v-1408q0 -26 -19 -45t-45 -19h-512q-26 0 -45 19t-19 45v1408q0 26 19 45t45 19h512q26 0 45 -19t19 -45zM640 1344v-1408q0 -26 -19 -45t-45 -19h-512q-26 0 -45 19t-19 45v1408q0 26 19 45t45 19h512q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" d="M1536 1344v-1408q0 -26 -19 -45t-45 -19h-1408q-26 0 -45 19t-19 45v1408q0 26 19 45t45 19h1408q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M45 -115q-19 -19 -32 -13t-13 32v1472q0 26 13 32t32 -13l710 -710q8 -8 13 -19v710q0 26 13 32t32 -13l710 -710q19 -19 19 -45t-19 -45l-710 -710q-19 -19 -32 -13t-13 32v710q-5 -10 -13 -19z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M45 -115q-19 -19 -32 -13t-13 32v1472q0 26 13 32t32 -13l710 -710q8 -8 13 -19v710q0 26 13 32t32 -13l710 -710q8 -8 13 -19v678q0 26 19 45t45 19h128q26 0 45 -19t19 -45v-1408q0 -26 -19 -45t-45 -19h-128q-26 0 -45 19t-19 45v678q-5 -10 -13 -19l-710 -710 q-19 -19 -32 -13t-13 32v710q-5 -10 -13 -19z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M45 -115q-19 -19 -32 -13t-13 32v1472q0 26 13 32t32 -13l710 -710q8 -8 13 -19v678q0 26 19 45t45 19h128q26 0 45 -19t19 -45v-1408q0 -26 -19 -45t-45 -19h-128q-26 0 -45 19t-19 45v678q-5 -10 -13 -19z" />
|
||||
<glyph unicode="" horiz-adv-x="1538" d="M14 557l710 710q19 19 45 19t45 -19l710 -710q19 -19 13 -32t-32 -13h-1472q-26 0 -32 13t13 32zM1473 0h-1408q-26 0 -45 19t-19 45v256q0 26 19 45t45 19h1408q26 0 45 -19t19 -45v-256q0 -26 -19 -45t-45 -19z" />
|
||||
<glyph unicode="" horiz-adv-x="1152" d="M742 -37l-652 651q-37 37 -37 90.5t37 90.5l652 651q37 37 90.5 37t90.5 -37l75 -75q37 -37 37 -90.5t-37 -90.5l-486 -486l486 -485q37 -38 37 -91t-37 -90l-75 -75q-37 -37 -90.5 -37t-90.5 37z" />
|
||||
<glyph unicode="" horiz-adv-x="1152" d="M1099 704q0 -52 -37 -91l-652 -651q-37 -37 -90 -37t-90 37l-76 75q-37 39 -37 91q0 53 37 90l486 486l-486 485q-37 39 -37 91q0 53 37 90l76 75q36 38 90 38t90 -38l652 -651q37 -37 37 -90z" />
|
||||
<glyph unicode="" d="M1216 576v128q0 26 -19 45t-45 19h-256v256q0 26 -19 45t-45 19h-128q-26 0 -45 -19t-19 -45v-256h-256q-26 0 -45 -19t-19 -45v-128q0 -26 19 -45t45 -19h256v-256q0 -26 19 -45t45 -19h128q26 0 45 19t19 45v256h256q26 0 45 19t19 45zM1536 640q0 -209 -103 -385.5 t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M1216 576v128q0 26 -19 45t-45 19h-768q-26 0 -45 -19t-19 -45v-128q0 -26 19 -45t45 -19h768q26 0 45 19t19 45zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5 t103 -385.5z" />
|
||||
<glyph unicode="" d="M1149 414q0 26 -19 45l-181 181l181 181q19 19 19 45q0 27 -19 46l-90 90q-19 19 -46 19q-26 0 -45 -19l-181 -181l-181 181q-19 19 -45 19q-27 0 -46 -19l-90 -90q-19 -19 -19 -46q0 -26 19 -45l181 -181l-181 -181q-19 -19 -19 -45q0 -27 19 -46l90 -90q19 -19 46 -19 q26 0 45 19l181 181l181 -181q19 -19 45 -19q27 0 46 19l90 90q19 19 19 46zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M1284 802q0 28 -18 46l-91 90q-19 19 -45 19t-45 -19l-408 -407l-226 226q-19 19 -45 19t-45 -19l-91 -90q-18 -18 -18 -46q0 -27 18 -45l362 -362q19 -19 45 -19q27 0 46 19l543 543q18 18 18 45zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103 t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M896 160v192q0 14 -9 23t-23 9h-192q-14 0 -23 -9t-9 -23v-192q0 -14 9 -23t23 -9h192q14 0 23 9t9 23zM1152 832q0 88 -55.5 163t-138.5 116t-170 41q-243 0 -371 -213q-15 -24 8 -42l132 -100q7 -6 19 -6q16 0 25 12q53 68 86 92q34 24 86 24q48 0 85.5 -26t37.5 -59 q0 -38 -20 -61t-68 -45q-63 -28 -115.5 -86.5t-52.5 -125.5v-36q0 -14 9 -23t23 -9h192q14 0 23 9t9 23q0 19 21.5 49.5t54.5 49.5q32 18 49 28.5t46 35t44.5 48t28 60.5t12.5 81zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5 t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M1024 160v160q0 14 -9 23t-23 9h-96v512q0 14 -9 23t-23 9h-320q-14 0 -23 -9t-9 -23v-160q0 -14 9 -23t23 -9h96v-320h-96q-14 0 -23 -9t-9 -23v-160q0 -14 9 -23t23 -9h448q14 0 23 9t9 23zM896 1056v160q0 14 -9 23t-23 9h-192q-14 0 -23 -9t-9 -23v-160q0 -14 9 -23 t23 -9h192q14 0 23 9t9 23zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M1197 512h-109q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h109q-32 108 -112.5 188.5t-188.5 112.5v-109q0 -26 -19 -45t-45 -19h-128q-26 0 -45 19t-19 45v109q-108 -32 -188.5 -112.5t-112.5 -188.5h109q26 0 45 -19t19 -45v-128q0 -26 -19 -45t-45 -19h-109 q32 -108 112.5 -188.5t188.5 -112.5v109q0 26 19 45t45 19h128q26 0 45 -19t19 -45v-109q108 32 188.5 112.5t112.5 188.5zM1536 704v-128q0 -26 -19 -45t-45 -19h-143q-37 -161 -154.5 -278.5t-278.5 -154.5v-143q0 -26 -19 -45t-45 -19h-128q-26 0 -45 19t-19 45v143 q-161 37 -278.5 154.5t-154.5 278.5h-143q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h143q37 161 154.5 278.5t278.5 154.5v143q0 26 19 45t45 19h128q26 0 45 -19t19 -45v-143q161 -37 278.5 -154.5t154.5 -278.5h143q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" d="M1097 457l-146 -146q-10 -10 -23 -10t-23 10l-137 137l-137 -137q-10 -10 -23 -10t-23 10l-146 146q-10 10 -10 23t10 23l137 137l-137 137q-10 10 -10 23t10 23l146 146q10 10 23 10t23 -10l137 -137l137 137q10 10 23 10t23 -10l146 -146q10 -10 10 -23t-10 -23 l-137 -137l137 -137q10 -10 10 -23t-10 -23zM1312 640q0 148 -73 273t-198 198t-273 73t-273 -73t-198 -198t-73 -273t73 -273t198 -198t273 -73t273 73t198 198t73 273zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5 t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M1171 723l-422 -422q-19 -19 -45 -19t-45 19l-294 294q-19 19 -19 45t19 45l102 102q19 19 45 19t45 -19l147 -147l275 275q19 19 45 19t45 -19l102 -102q19 -19 19 -45t-19 -45zM1312 640q0 148 -73 273t-198 198t-273 73t-273 -73t-198 -198t-73 -273t73 -273t198 -198 t273 -73t273 73t198 198t73 273zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M1312 643q0 161 -87 295l-754 -753q137 -89 297 -89q111 0 211.5 43.5t173.5 116.5t116 174.5t43 212.5zM313 344l755 754q-135 91 -300 91q-148 0 -273 -73t-198 -199t-73 -274q0 -162 89 -299zM1536 643q0 -157 -61 -300t-163.5 -246t-245 -164t-298.5 -61t-298.5 61 t-245 164t-163.5 246t-61 300t61 299.5t163.5 245.5t245 164t298.5 61t298.5 -61t245 -164t163.5 -245.5t61 -299.5z" />
|
||||
<glyph unicode="" d="M1536 640v-128q0 -53 -32.5 -90.5t-84.5 -37.5h-704l293 -294q38 -36 38 -90t-38 -90l-75 -76q-37 -37 -90 -37q-52 0 -91 37l-651 652q-37 37 -37 90q0 52 37 91l651 650q38 38 91 38q52 0 90 -38l75 -74q38 -38 38 -91t-38 -91l-293 -293h704q52 0 84.5 -37.5 t32.5 -90.5z" />
|
||||
<glyph unicode="" d="M1472 576q0 -54 -37 -91l-651 -651q-39 -37 -91 -37q-51 0 -90 37l-75 75q-38 38 -38 91t38 91l293 293h-704q-52 0 -84.5 37.5t-32.5 90.5v128q0 53 32.5 90.5t84.5 37.5h704l-293 294q-38 36 -38 90t38 90l75 75q38 38 90 38q53 0 91 -38l651 -651q37 -35 37 -90z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1611 565q0 -51 -37 -90l-75 -75q-38 -38 -91 -38q-54 0 -90 38l-294 293v-704q0 -52 -37.5 -84.5t-90.5 -32.5h-128q-53 0 -90.5 32.5t-37.5 84.5v704l-294 -293q-36 -38 -90 -38t-90 38l-75 75q-38 38 -38 90q0 53 38 91l651 651q35 37 90 37q54 0 91 -37l651 -651 q37 -39 37 -91z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1611 704q0 -53 -37 -90l-651 -652q-39 -37 -91 -37q-53 0 -90 37l-651 652q-38 36 -38 90q0 53 38 91l74 75q39 37 91 37q53 0 90 -37l294 -294v704q0 52 38 90t90 38h128q52 0 90 -38t38 -90v-704l294 294q37 37 90 37q52 0 91 -37l75 -75q37 -39 37 -91z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1792 896q0 -26 -19 -45l-512 -512q-19 -19 -45 -19t-45 19t-19 45v256h-224q-98 0 -175.5 -6t-154 -21.5t-133 -42.5t-105.5 -69.5t-80 -101t-48.5 -138.5t-17.5 -181q0 -55 5 -123q0 -6 2.5 -23.5t2.5 -26.5q0 -15 -8.5 -25t-23.5 -10q-16 0 -28 17q-7 9 -13 22 t-13.5 30t-10.5 24q-127 285 -127 451q0 199 53 333q162 403 875 403h224v256q0 26 19 45t45 19t45 -19l512 -512q19 -19 19 -45z" />
|
||||
<glyph unicode="" d="M755 480q0 -13 -10 -23l-332 -332l144 -144q19 -19 19 -45t-19 -45t-45 -19h-448q-26 0 -45 19t-19 45v448q0 26 19 45t45 19t45 -19l144 -144l332 332q10 10 23 10t23 -10l114 -114q10 -10 10 -23zM1536 1344v-448q0 -26 -19 -45t-45 -19t-45 19l-144 144l-332 -332 q-10 -10 -23 -10t-23 10l-114 114q-10 10 -10 23t10 23l332 332l-144 144q-19 19 -19 45t19 45t45 19h448q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" d="M768 576v-448q0 -26 -19 -45t-45 -19t-45 19l-144 144l-332 -332q-10 -10 -23 -10t-23 10l-114 114q-10 10 -10 23t10 23l332 332l-144 144q-19 19 -19 45t19 45t45 19h448q26 0 45 -19t19 -45zM1523 1248q0 -13 -10 -23l-332 -332l144 -144q19 -19 19 -45t-19 -45 t-45 -19h-448q-26 0 -45 19t-19 45v448q0 26 19 45t45 19t45 -19l144 -144l332 332q10 10 23 10t23 -10l114 -114q10 -10 10 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M1408 800v-192q0 -40 -28 -68t-68 -28h-416v-416q0 -40 -28 -68t-68 -28h-192q-40 0 -68 28t-28 68v416h-416q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h416v416q0 40 28 68t68 28h192q40 0 68 -28t28 -68v-416h416q40 0 68 -28t28 -68z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M1408 800v-192q0 -40 -28 -68t-68 -28h-1216q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h1216q40 0 68 -28t28 -68z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1482 486q46 -26 59.5 -77.5t-12.5 -97.5l-64 -110q-26 -46 -77.5 -59.5t-97.5 12.5l-266 153v-307q0 -52 -38 -90t-90 -38h-128q-52 0 -90 38t-38 90v307l-266 -153q-46 -26 -97.5 -12.5t-77.5 59.5l-64 110q-26 46 -12.5 97.5t59.5 77.5l266 154l-266 154 q-46 26 -59.5 77.5t12.5 97.5l64 110q26 46 77.5 59.5t97.5 -12.5l266 -153v307q0 52 38 90t90 38h128q52 0 90 -38t38 -90v-307l266 153q46 26 97.5 12.5t77.5 -59.5l64 -110q26 -46 12.5 -97.5t-59.5 -77.5l-266 -154z" />
|
||||
<glyph unicode="" d="M768 1408q209 0 385.5 -103t279.5 -279.5t103 -385.5t-103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103zM896 161v190q0 14 -9 23.5t-22 9.5h-192q-13 0 -23 -10t-10 -23v-190q0 -13 10 -23t23 -10h192 q13 0 22 9.5t9 23.5zM894 505l18 621q0 12 -10 18q-10 8 -24 8h-220q-14 0 -24 -8q-10 -6 -10 -18l17 -621q0 -10 10 -17.5t24 -7.5h185q14 0 23.5 7.5t10.5 17.5z" />
|
||||
<glyph unicode="" d="M928 180v56v468v192h-320v-192v-468v-56q0 -25 18 -38.5t46 -13.5h192q28 0 46 13.5t18 38.5zM472 1024h195l-126 161q-26 31 -69 31q-40 0 -68 -28t-28 -68t28 -68t68 -28zM1160 1120q0 40 -28 68t-68 28q-43 0 -69 -31l-125 -161h194q40 0 68 28t28 68zM1536 864v-320 q0 -14 -9 -23t-23 -9h-96v-416q0 -40 -28 -68t-68 -28h-1088q-40 0 -68 28t-28 68v416h-96q-14 0 -23 9t-9 23v320q0 14 9 23t23 9h440q-93 0 -158.5 65.5t-65.5 158.5t65.5 158.5t158.5 65.5q107 0 168 -77l128 -165l128 165q61 77 168 77q93 0 158.5 -65.5t65.5 -158.5 t-65.5 -158.5t-158.5 -65.5h440q14 0 23 -9t9 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1280 832q0 26 -19 45t-45 19q-172 0 -318 -49.5t-259.5 -134t-235.5 -219.5q-19 -21 -19 -45q0 -26 19 -45t45 -19q24 0 45 19q27 24 74 71t67 66q137 124 268.5 176t313.5 52q26 0 45 19t19 45zM1792 1030q0 -95 -20 -193q-46 -224 -184.5 -383t-357.5 -268 q-214 -108 -438 -108q-148 0 -286 47q-15 5 -88 42t-96 37q-16 0 -39.5 -32t-45 -70t-52.5 -70t-60 -32q-30 0 -51 11t-31 24t-27 42q-2 4 -6 11t-5.5 10t-3 9.5t-1.5 13.5q0 35 31 73.5t68 65.5t68 56t31 48q0 4 -14 38t-16 44q-9 51 -9 104q0 115 43.5 220t119 184.5 t170.5 139t204 95.5q55 18 145 25.5t179.5 9t178.5 6t163.5 24t113.5 56.5l29.5 29.5t29.5 28t27 20t36.5 16t43.5 4.5q39 0 70.5 -46t47.5 -112t24 -124t8 -96z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M1408 -160v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-1344q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h1344q13 0 22.5 -9.5t9.5 -22.5zM1152 896q0 -78 -24.5 -144t-64 -112.5t-87.5 -88t-96 -77.5t-87.5 -72t-64 -81.5t-24.5 -96.5q0 -96 67 -224l-4 1l1 -1 q-90 41 -160 83t-138.5 100t-113.5 122.5t-72.5 150.5t-27.5 184q0 78 24.5 144t64 112.5t87.5 88t96 77.5t87.5 72t64 81.5t24.5 96.5q0 94 -66 224l3 -1l-1 1q90 -41 160 -83t138.5 -100t113.5 -122.5t72.5 -150.5t27.5 -184z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1664 576q-152 236 -381 353q61 -104 61 -225q0 -185 -131.5 -316.5t-316.5 -131.5t-316.5 131.5t-131.5 316.5q0 121 61 225q-229 -117 -381 -353q133 -205 333.5 -326.5t434.5 -121.5t434.5 121.5t333.5 326.5zM944 960q0 20 -14 34t-34 14q-125 0 -214.5 -89.5 t-89.5 -214.5q0 -20 14 -34t34 -14t34 14t14 34q0 86 61 147t147 61q20 0 34 14t14 34zM1792 576q0 -34 -20 -69q-140 -230 -376.5 -368.5t-499.5 -138.5t-499.5 139t-376.5 368q-20 35 -20 69t20 69q140 229 376.5 368t499.5 139t499.5 -139t376.5 -368q20 -35 20 -69z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M555 201l78 141q-87 63 -136 159t-49 203q0 121 61 225q-229 -117 -381 -353q167 -258 427 -375zM944 960q0 20 -14 34t-34 14q-125 0 -214.5 -89.5t-89.5 -214.5q0 -20 14 -34t34 -14t34 14t14 34q0 86 61 147t147 61q20 0 34 14t14 34zM1307 1151q0 -7 -1 -9 q-105 -188 -315 -566t-316 -567l-49 -89q-10 -16 -28 -16q-12 0 -134 70q-16 10 -16 28q0 12 44 87q-143 65 -263.5 173t-208.5 245q-20 31 -20 69t20 69q153 235 380 371t496 136q89 0 180 -17l54 97q10 16 28 16q5 0 18 -6t31 -15.5t33 -18.5t31.5 -18.5t19.5 -11.5 q16 -10 16 -27zM1344 704q0 -139 -79 -253.5t-209 -164.5l280 502q8 -45 8 -84zM1792 576q0 -35 -20 -69q-39 -64 -109 -145q-150 -172 -347.5 -267t-419.5 -95l74 132q212 18 392.5 137t301.5 307q-115 179 -282 294l63 112q95 -64 182.5 -153t144.5 -184q20 -34 20 -69z " />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1024 161v190q0 14 -9.5 23.5t-22.5 9.5h-192q-13 0 -22.5 -9.5t-9.5 -23.5v-190q0 -14 9.5 -23.5t22.5 -9.5h192q13 0 22.5 9.5t9.5 23.5zM1022 535l18 459q0 12 -10 19q-13 11 -24 11h-220q-11 0 -24 -11q-10 -7 -10 -21l17 -457q0 -10 10 -16.5t24 -6.5h185 q14 0 23.5 6.5t10.5 16.5zM1008 1469l768 -1408q35 -63 -2 -126q-17 -29 -46.5 -46t-63.5 -17h-1536q-34 0 -63.5 17t-46.5 46q-37 63 -2 126l768 1408q17 31 47 49t65 18t65 -18t47 -49z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M1376 1376q44 -52 12 -148t-108 -172l-161 -161l160 -696q5 -19 -12 -33l-128 -96q-7 -6 -19 -6q-4 0 -7 1q-15 3 -21 16l-279 508l-259 -259l53 -194q5 -17 -8 -31l-96 -96q-9 -9 -23 -9h-2q-15 2 -24 13l-189 252l-252 189q-11 7 -13 23q-1 13 9 25l96 97q9 9 23 9 q6 0 8 -1l194 -53l259 259l-508 279q-14 8 -17 24q-2 16 9 27l128 128q14 13 30 8l665 -159l160 160q76 76 172 108t148 -12z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M128 -128h288v288h-288v-288zM480 -128h320v288h-320v-288zM128 224h288v320h-288v-320zM480 224h320v320h-320v-320zM128 608h288v288h-288v-288zM864 -128h320v288h-320v-288zM480 608h320v288h-320v-288zM1248 -128h288v288h-288v-288zM864 224h320v320h-320v-320z M512 1088v288q0 13 -9.5 22.5t-22.5 9.5h-64q-13 0 -22.5 -9.5t-9.5 -22.5v-288q0 -13 9.5 -22.5t22.5 -9.5h64q13 0 22.5 9.5t9.5 22.5zM1248 224h288v320h-288v-320zM864 608h320v288h-320v-288zM1248 608h288v288h-288v-288zM1280 1088v288q0 13 -9.5 22.5t-22.5 9.5h-64 q-13 0 -22.5 -9.5t-9.5 -22.5v-288q0 -13 9.5 -22.5t22.5 -9.5h64q13 0 22.5 9.5t9.5 22.5zM1664 1152v-1280q0 -52 -38 -90t-90 -38h-1408q-52 0 -90 38t-38 90v1280q0 52 38 90t90 38h128v96q0 66 47 113t113 47h64q66 0 113 -47t47 -113v-96h384v96q0 66 47 113t113 47 h64q66 0 113 -47t47 -113v-96h128q52 0 90 -38t38 -90z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M666 1055q-60 -92 -137 -273q-22 45 -37 72.5t-40.5 63.5t-51 56.5t-63 35t-81.5 14.5h-224q-14 0 -23 9t-9 23v192q0 14 9 23t23 9h224q250 0 410 -225zM1792 256q0 -14 -9 -23l-320 -320q-9 -9 -23 -9q-13 0 -22.5 9.5t-9.5 22.5v192q-32 0 -85 -0.5t-81 -1t-73 1 t-71 5t-64 10.5t-63 18.5t-58 28.5t-59 40t-55 53.5t-56 69.5q59 93 136 273q22 -45 37 -72.5t40.5 -63.5t51 -56.5t63 -35t81.5 -14.5h256v192q0 14 9 23t23 9q12 0 24 -10l319 -319q9 -9 9 -23zM1792 1152q0 -14 -9 -23l-320 -320q-9 -9 -23 -9q-13 0 -22.5 9.5t-9.5 22.5 v192h-256q-48 0 -87 -15t-69 -45t-51 -61.5t-45 -77.5q-32 -62 -78 -171q-29 -66 -49.5 -111t-54 -105t-64 -100t-74 -83t-90 -68.5t-106.5 -42t-128 -16.5h-224q-14 0 -23 9t-9 23v192q0 14 9 23t23 9h224q48 0 87 15t69 45t51 61.5t45 77.5q32 62 78 171q29 66 49.5 111 t54 105t64 100t74 83t90 68.5t106.5 42t128 16.5h256v192q0 14 9 23t23 9q12 0 24 -10l319 -319q9 -9 9 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1792 640q0 -174 -120 -321.5t-326 -233t-450 -85.5q-70 0 -145 8q-198 -175 -460 -242q-49 -14 -114 -22q-17 -2 -30.5 9t-17.5 29v1q-3 4 -0.5 12t2 10t4.5 9.5l6 9t7 8.5t8 9q7 8 31 34.5t34.5 38t31 39.5t32.5 51t27 59t26 76q-157 89 -247.5 220t-90.5 281 q0 130 71 248.5t191 204.5t286 136.5t348 50.5q244 0 450 -85.5t326 -233t120 -321.5z" />
|
||||
<glyph unicode="" d="M1536 704v-128q0 -201 -98.5 -362t-274 -251.5t-395.5 -90.5t-395.5 90.5t-274 251.5t-98.5 362v128q0 26 19 45t45 19h384q26 0 45 -19t19 -45v-128q0 -52 23.5 -90t53.5 -57t71 -30t64 -13t44 -2t44 2t64 13t71 30t53.5 57t23.5 90v128q0 26 19 45t45 19h384 q26 0 45 -19t19 -45zM512 1344v-384q0 -26 -19 -45t-45 -19h-384q-26 0 -45 19t-19 45v384q0 26 19 45t45 19h384q26 0 45 -19t19 -45zM1536 1344v-384q0 -26 -19 -45t-45 -19h-384q-26 0 -45 19t-19 45v384q0 26 19 45t45 19h384q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1611 320q0 -53 -37 -90l-75 -75q-38 -38 -91 -38q-54 0 -90 38l-486 485l-486 -485q-36 -38 -90 -38t-90 38l-75 75q-38 36 -38 90q0 53 38 91l651 651q37 37 90 37q52 0 91 -37l650 -651q38 -38 38 -91z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1611 832q0 -53 -37 -90l-651 -651q-38 -38 -91 -38q-54 0 -90 38l-651 651q-38 36 -38 90q0 53 38 91l74 75q39 37 91 37q53 0 90 -37l486 -486l486 486q37 37 90 37q52 0 91 -37l75 -75q37 -39 37 -91z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M1280 32q0 -13 -9.5 -22.5t-22.5 -9.5h-960q-8 0 -13.5 2t-9 7t-5.5 8t-3 11.5t-1 11.5v13v11v160v416h-192q-26 0 -45 19t-19 45q0 24 15 41l320 384q19 22 49 22t49 -22l320 -384q15 -17 15 -41q0 -26 -19 -45t-45 -19h-192v-384h576q16 0 25 -11l160 -192q7 -11 7 -21 zM1920 448q0 -24 -15 -41l-320 -384q-20 -23 -49 -23t-49 23l-320 384q-15 17 -15 41q0 26 19 45t45 19h192v384h-576q-16 0 -25 12l-160 192q-7 9 -7 20q0 13 9.5 22.5t22.5 9.5h960q8 0 13.5 -2t9 -7t5.5 -8t3 -11.5t1 -11.5v-13v-11v-160v-416h192q26 0 45 -19t19 -45z " />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M640 0q0 -53 -37.5 -90.5t-90.5 -37.5t-90.5 37.5t-37.5 90.5t37.5 90.5t90.5 37.5t90.5 -37.5t37.5 -90.5zM1536 0q0 -53 -37.5 -90.5t-90.5 -37.5t-90.5 37.5t-37.5 90.5t37.5 90.5t90.5 37.5t90.5 -37.5t37.5 -90.5zM1664 1088v-512q0 -24 -16 -42.5t-41 -21.5 l-1044 -122q1 -7 4.5 -21.5t6 -26.5t2.5 -22q0 -16 -24 -64h920q26 0 45 -19t19 -45t-19 -45t-45 -19h-1024q-26 0 -45 19t-19 45q0 14 11 39.5t29.5 59.5t20.5 38l-177 823h-204q-26 0 -45 19t-19 45t19 45t45 19h256q16 0 28.5 -6.5t20 -15.5t13 -24.5t7.5 -26.5 t5.5 -29.5t4.5 -25.5h1201q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1664 928v-704q0 -92 -66 -158t-158 -66h-1216q-92 0 -158 66t-66 158v960q0 92 66 158t158 66h320q92 0 158 -66t66 -158v-32h672q92 0 158 -66t66 -158z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M1879 584q0 -31 -31 -66l-336 -396q-43 -51 -120.5 -86.5t-143.5 -35.5h-1088q-34 0 -60.5 13t-26.5 43q0 31 31 66l336 396q43 51 120.5 86.5t143.5 35.5h1088q34 0 60.5 -13t26.5 -43zM1536 928v-160h-832q-94 0 -197 -47.5t-164 -119.5l-337 -396l-5 -6q0 4 -0.5 12.5 t-0.5 12.5v960q0 92 66 158t158 66h320q92 0 158 -66t66 -158v-32h544q92 0 158 -66t66 -158z" />
|
||||
<glyph unicode="" horiz-adv-x="768" d="M704 1216q0 -26 -19 -45t-45 -19h-128v-1024h128q26 0 45 -19t19 -45t-19 -45l-256 -256q-19 -19 -45 -19t-45 19l-256 256q-19 19 -19 45t19 45t45 19h128v1024h-128q-26 0 -45 19t-19 45t19 45l256 256q19 19 45 19t45 -19l256 -256q19 -19 19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1792 640q0 -26 -19 -45l-256 -256q-19 -19 -45 -19t-45 19t-19 45v128h-1024v-128q0 -26 -19 -45t-45 -19t-45 19l-256 256q-19 19 -19 45t19 45l256 256q19 19 45 19t45 -19t19 -45v-128h1024v128q0 26 19 45t45 19t45 -19l256 -256q19 -19 19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M512 512v-384h-256v384h256zM896 1024v-896h-256v896h256zM1280 768v-640h-256v640h256zM1664 1152v-1024h-256v1024h256zM1792 32v1216q0 13 -9.5 22.5t-22.5 9.5h-1600q-13 0 -22.5 -9.5t-9.5 -22.5v-1216q0 -13 9.5 -22.5t22.5 -9.5h1600q13 0 22.5 9.5t9.5 22.5z M1920 1248v-1216q0 -66 -47 -113t-113 -47h-1600q-66 0 -113 47t-47 113v1216q0 66 47 113t113 47h1600q66 0 113 -47t47 -113z" />
|
||||
<glyph unicode="" d="M1280 926q-56 -25 -121 -34q68 40 93 117q-65 -38 -134 -51q-61 66 -153 66q-87 0 -148.5 -61.5t-61.5 -148.5q0 -29 5 -48q-129 7 -242 65t-192 155q-29 -50 -29 -106q0 -114 91 -175q-47 1 -100 26v-2q0 -75 50 -133.5t123 -72.5q-29 -8 -51 -8q-13 0 -39 4 q21 -63 74.5 -104t121.5 -42q-116 -90 -261 -90q-26 0 -50 3q148 -94 322 -94q112 0 210 35.5t168 95t120.5 137t75 162t24.5 168.5q0 18 -1 27q63 45 105 109zM1536 1120v-960q0 -119 -84.5 -203.5t-203.5 -84.5h-960q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5 t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" d="M1307 618l23 219h-198v109q0 49 15.5 68.5t71.5 19.5h110v219h-175q-152 0 -218 -72t-66 -213v-131h-131v-219h131v-635h262v635h175zM1536 1120v-960q0 -119 -84.5 -203.5t-203.5 -84.5h-960q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960 q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M928 704q0 14 -9 23t-23 9q-66 0 -113 -47t-47 -113q0 -14 9 -23t23 -9t23 9t9 23q0 40 28 68t68 28q14 0 23 9t9 23zM1152 574q0 -106 -75 -181t-181 -75t-181 75t-75 181t75 181t181 75t181 -75t75 -181zM128 0h1536v128h-1536v-128zM1280 574q0 159 -112.5 271.5 t-271.5 112.5t-271.5 -112.5t-112.5 -271.5t112.5 -271.5t271.5 -112.5t271.5 112.5t112.5 271.5zM256 1216h384v128h-384v-128zM128 1024h1536v118v138h-828l-64 -128h-644v-128zM1792 1280v-1280q0 -53 -37.5 -90.5t-90.5 -37.5h-1536q-53 0 -90.5 37.5t-37.5 90.5v1280 q0 53 37.5 90.5t90.5 37.5h1536q53 0 90.5 -37.5t37.5 -90.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M832 1024q0 80 -56 136t-136 56t-136 -56t-56 -136q0 -42 19 -83q-41 19 -83 19q-80 0 -136 -56t-56 -136t56 -136t136 -56t136 56t56 136q0 42 -19 83q41 -19 83 -19q80 0 136 56t56 136zM1683 320q0 -17 -49 -66t-66 -49q-9 0 -28.5 16t-36.5 33t-38.5 40t-24.5 26 l-96 -96l220 -220q28 -28 28 -68q0 -42 -39 -81t-81 -39q-40 0 -68 28l-671 671q-176 -131 -365 -131q-163 0 -265.5 102.5t-102.5 265.5q0 160 95 313t248 248t313 95q163 0 265.5 -102.5t102.5 -265.5q0 -189 -131 -365l355 -355l96 96q-3 3 -26 24.5t-40 38.5t-33 36.5 t-16 28.5q0 17 49 66t66 49q13 0 23 -10q6 -6 46 -44.5t82 -79.5t86.5 -86t73 -78t28.5 -41z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M896 640q0 106 -75 181t-181 75t-181 -75t-75 -181t75 -181t181 -75t181 75t75 181zM1664 128q0 52 -38 90t-90 38t-90 -38t-38 -90q0 -53 37.5 -90.5t90.5 -37.5t90.5 37.5t37.5 90.5zM1664 1152q0 52 -38 90t-90 38t-90 -38t-38 -90q0 -53 37.5 -90.5t90.5 -37.5 t90.5 37.5t37.5 90.5zM1280 731v-185q0 -10 -7 -19.5t-16 -10.5l-155 -24q-11 -35 -32 -76q34 -48 90 -115q7 -10 7 -20q0 -12 -7 -19q-23 -30 -82.5 -89.5t-78.5 -59.5q-11 0 -21 7l-115 90q-37 -19 -77 -31q-11 -108 -23 -155q-7 -24 -30 -24h-186q-11 0 -20 7.5t-10 17.5 l-23 153q-34 10 -75 31l-118 -89q-7 -7 -20 -7q-11 0 -21 8q-144 133 -144 160q0 9 7 19q10 14 41 53t47 61q-23 44 -35 82l-152 24q-10 1 -17 9.5t-7 19.5v185q0 10 7 19.5t16 10.5l155 24q11 35 32 76q-34 48 -90 115q-7 11 -7 20q0 12 7 20q22 30 82 89t79 59q11 0 21 -7 l115 -90q34 18 77 32q11 108 23 154q7 24 30 24h186q11 0 20 -7.5t10 -17.5l23 -153q34 -10 75 -31l118 89q8 7 20 7q11 0 21 -8q144 -133 144 -160q0 -9 -7 -19q-12 -16 -42 -54t-45 -60q23 -48 34 -82l152 -23q10 -2 17 -10.5t7 -19.5zM1920 198v-140q0 -16 -149 -31 q-12 -27 -30 -52q51 -113 51 -138q0 -4 -4 -7q-122 -71 -124 -71q-8 0 -46 47t-52 68q-20 -2 -30 -2t-30 2q-14 -21 -52 -68t-46 -47q-2 0 -124 71q-4 3 -4 7q0 25 51 138q-18 25 -30 52q-149 15 -149 31v140q0 16 149 31q13 29 30 52q-51 113 -51 138q0 4 4 7q4 2 35 20 t59 34t30 16q8 0 46 -46.5t52 -67.5q20 2 30 2t30 -2q51 71 92 112l6 2q4 0 124 -70q4 -3 4 -7q0 -25 -51 -138q17 -23 30 -52q149 -15 149 -31zM1920 1222v-140q0 -16 -149 -31q-12 -27 -30 -52q51 -113 51 -138q0 -4 -4 -7q-122 -71 -124 -71q-8 0 -46 47t-52 68 q-20 -2 -30 -2t-30 2q-14 -21 -52 -68t-46 -47q-2 0 -124 71q-4 3 -4 7q0 25 51 138q-18 25 -30 52q-149 15 -149 31v140q0 16 149 31q13 29 30 52q-51 113 -51 138q0 4 4 7q4 2 35 20t59 34t30 16q8 0 46 -46.5t52 -67.5q20 2 30 2t30 -2q51 71 92 112l6 2q4 0 124 -70 q4 -3 4 -7q0 -25 -51 -138q17 -23 30 -52q149 -15 149 -31z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1408 768q0 -139 -94 -257t-256.5 -186.5t-353.5 -68.5q-86 0 -176 16q-124 -88 -278 -128q-36 -9 -86 -16h-3q-11 0 -20.5 8t-11.5 21q-1 3 -1 6.5t0.5 6.5t2 6l2.5 5t3.5 5.5t4 5t4.5 5t4 4.5q5 6 23 25t26 29.5t22.5 29t25 38.5t20.5 44q-124 72 -195 177t-71 224 q0 139 94 257t256.5 186.5t353.5 68.5t353.5 -68.5t256.5 -186.5t94 -257zM1792 512q0 -120 -71 -224.5t-195 -176.5q10 -24 20.5 -44t25 -38.5t22.5 -29t26 -29.5t23 -25q1 -1 4 -4.5t4.5 -5t4 -5t3.5 -5.5l2.5 -5t2 -6t0.5 -6.5t-1 -6.5q-3 -14 -13 -22t-22 -7 q-50 7 -86 16q-154 40 -278 128q-90 -16 -176 -16q-271 0 -472 132q58 -4 88 -4q161 0 309 45t264 129q125 92 192 212t67 254q0 77 -23 152q129 -71 204 -178t75 -230z" />
|
||||
<glyph unicode="" d="M256 192q0 26 -19 45t-45 19t-45 -19t-19 -45t19 -45t45 -19t45 19t19 45zM1408 768q0 51 -39 89.5t-89 38.5h-352q0 58 48 159.5t48 160.5q0 98 -32 145t-128 47q-26 -26 -38 -85t-30.5 -125.5t-59.5 -109.5q-22 -23 -77 -91q-4 -5 -23 -30t-31.5 -41t-34.5 -42.5 t-40 -44t-38.5 -35.5t-40 -27t-35.5 -9h-32v-640h32q13 0 31.5 -3t33 -6.5t38 -11t35 -11.5t35.5 -12.5t29 -10.5q211 -73 342 -73h121q192 0 192 167q0 26 -5 56q30 16 47.5 52.5t17.5 73.5t-18 69q53 50 53 119q0 25 -10 55.5t-25 47.5q32 1 53.5 47t21.5 81zM1536 769 q0 -89 -49 -163q9 -33 9 -69q0 -77 -38 -144q3 -21 3 -43q0 -101 -60 -178q1 -139 -85 -219.5t-227 -80.5h-36h-93q-96 0 -189.5 22.5t-216.5 65.5q-116 40 -138 40h-288q-53 0 -90.5 37.5t-37.5 90.5v640q0 53 37.5 90.5t90.5 37.5h274q36 24 137 155q58 75 107 128 q24 25 35.5 85.5t30.5 126.5t62 108q39 37 90 37q84 0 151 -32.5t102 -101.5t35 -186q0 -93 -48 -192h176q104 0 180 -76t76 -179z" />
|
||||
<glyph unicode="" d="M256 1088q0 26 -19 45t-45 19t-45 -19t-19 -45t19 -45t45 -19t45 19t19 45zM1408 512q0 35 -21.5 81t-53.5 47q15 17 25 47.5t10 55.5q0 69 -53 119q18 32 18 69t-17.5 73.5t-47.5 52.5q5 30 5 56q0 85 -49 126t-136 41h-128q-131 0 -342 -73q-5 -2 -29 -10.5 t-35.5 -12.5t-35 -11.5t-38 -11t-33 -6.5t-31.5 -3h-32v-640h32q16 0 35.5 -9t40 -27t38.5 -35.5t40 -44t34.5 -42.5t31.5 -41t23 -30q55 -68 77 -91q41 -43 59.5 -109.5t30.5 -125.5t38 -85q96 0 128 47t32 145q0 59 -48 160.5t-48 159.5h352q50 0 89 38.5t39 89.5z M1536 511q0 -103 -76 -179t-180 -76h-176q48 -99 48 -192q0 -118 -35 -186q-35 -69 -102 -101.5t-151 -32.5q-51 0 -90 37q-34 33 -54 82t-25.5 90.5t-17.5 84.5t-31 64q-48 50 -107 127q-101 131 -137 155h-274q-53 0 -90.5 37.5t-37.5 90.5v640q0 53 37.5 90.5t90.5 37.5 h288q22 0 138 40q128 44 223 66t200 22h112q140 0 226.5 -79t85.5 -216v-5q60 -77 60 -178q0 -22 -3 -43q38 -67 38 -144q0 -36 -9 -69q49 -74 49 -163z" />
|
||||
<glyph unicode="" horiz-adv-x="896" d="M832 1504v-1339l-449 -236q-22 -12 -40 -12q-21 0 -31.5 14.5t-10.5 35.5q0 6 2 20l86 500l-364 354q-25 27 -25 48q0 37 56 46l502 73l225 455q19 41 49 41z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1664 940q0 81 -21.5 143t-55 98.5t-81.5 59.5t-94 31t-98 8t-112 -25.5t-110.5 -64t-86.5 -72t-60 -61.5q-18 -22 -49 -22t-49 22q-24 28 -60 61.5t-86.5 72t-110.5 64t-112 25.5t-98 -8t-94 -31t-81.5 -59.5t-55 -98.5t-21.5 -143q0 -168 187 -355l581 -560l580 559 q188 188 188 356zM1792 940q0 -221 -229 -450l-623 -600q-18 -18 -44 -18t-44 18l-624 602q-10 8 -27.5 26t-55.5 65.5t-68 97.5t-53.5 121t-23.5 138q0 220 127 344t351 124q62 0 126.5 -21.5t120 -58t95.5 -68.5t76 -68q36 36 76 68t95.5 68.5t120 58t126.5 21.5 q224 0 351 -124t127 -344z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M640 96q0 -4 1 -20t0.5 -26.5t-3 -23.5t-10 -19.5t-20.5 -6.5h-320q-119 0 -203.5 84.5t-84.5 203.5v704q0 119 84.5 203.5t203.5 84.5h320q13 0 22.5 -9.5t9.5 -22.5q0 -4 1 -20t0.5 -26.5t-3 -23.5t-10 -19.5t-20.5 -6.5h-320q-66 0 -113 -47t-47 -113v-704 q0 -66 47 -113t113 -47h288h11h13t11.5 -1t11.5 -3t8 -5.5t7 -9t2 -13.5zM1568 640q0 -26 -19 -45l-544 -544q-19 -19 -45 -19t-45 19t-19 45v288h-448q-26 0 -45 19t-19 45v384q0 26 19 45t45 19h448v288q0 26 19 45t45 19t45 -19l544 -544q19 -19 19 -45z" />
|
||||
<glyph unicode="" d="M237 122h231v694h-231v-694zM483 1030q-1 52 -36 86t-93 34t-94.5 -34t-36.5 -86q0 -51 35.5 -85.5t92.5 -34.5h1q59 0 95 34.5t36 85.5zM1068 122h231v398q0 154 -73 233t-193 79q-136 0 -209 -117h2v101h-231q3 -66 0 -694h231v388q0 38 7 56q15 35 45 59.5t74 24.5 q116 0 116 -157v-371zM1536 1120v-960q0 -119 -84.5 -203.5t-203.5 -84.5h-960q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1152" d="M480 672v448q0 14 -9 23t-23 9t-23 -9t-9 -23v-448q0 -14 9 -23t23 -9t23 9t9 23zM1152 320q0 -26 -19 -45t-45 -19h-429l-51 -483q-2 -12 -10.5 -20.5t-20.5 -8.5h-1q-27 0 -32 27l-76 485h-404q-26 0 -45 19t-19 45q0 123 78.5 221.5t177.5 98.5v512q-52 0 -90 38 t-38 90t38 90t90 38h640q52 0 90 -38t38 -90t-38 -90t-90 -38v-512q99 0 177.5 -98.5t78.5 -221.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1408 608v-320q0 -119 -84.5 -203.5t-203.5 -84.5h-832q-119 0 -203.5 84.5t-84.5 203.5v832q0 119 84.5 203.5t203.5 84.5h704q14 0 23 -9t9 -23v-64q0 -14 -9 -23t-23 -9h-704q-66 0 -113 -47t-47 -113v-832q0 -66 47 -113t113 -47h832q66 0 113 47t47 113v320 q0 14 9 23t23 9h64q14 0 23 -9t9 -23zM1792 1472v-512q0 -26 -19 -45t-45 -19t-45 19l-176 176l-652 -652q-10 -10 -23 -10t-23 10l-114 114q-10 10 -10 23t10 23l652 652l-176 176q-19 19 -19 45t19 45t45 19h512q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" d="M1184 640q0 -26 -19 -45l-544 -544q-19 -19 -45 -19t-45 19t-19 45v288h-448q-26 0 -45 19t-19 45v384q0 26 19 45t45 19h448v288q0 26 19 45t45 19t45 -19l544 -544q19 -19 19 -45zM1536 992v-704q0 -119 -84.5 -203.5t-203.5 -84.5h-320q-13 0 -22.5 9.5t-9.5 22.5 q0 4 -1 20t-0.5 26.5t3 23.5t10 19.5t20.5 6.5h320q66 0 113 47t47 113v704q0 66 -47 113t-113 47h-288h-11h-13t-11.5 1t-11.5 3t-8 5.5t-7 9t-2 13.5q0 4 -1 20t-0.5 26.5t3 23.5t10 19.5t20.5 6.5h320q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M458 653q-74 162 -74 371h-256v-96q0 -78 94.5 -162t235.5 -113zM1536 928v96h-256q0 -209 -74 -371q141 29 235.5 113t94.5 162zM1664 1056v-128q0 -71 -41.5 -143t-112 -130t-173 -97.5t-215.5 -44.5q-42 -54 -95 -95q-38 -34 -52.5 -72.5t-14.5 -89.5q0 -54 30.5 -91 t97.5 -37q75 0 133.5 -45.5t58.5 -114.5v-64q0 -14 -9 -23t-23 -9h-832q-14 0 -23 9t-9 23v64q0 69 58.5 114.5t133.5 45.5q67 0 97.5 37t30.5 91q0 51 -14.5 89.5t-52.5 72.5q-53 41 -95 95q-113 5 -215.5 44.5t-173 97.5t-112 130t-41.5 143v128q0 40 28 68t68 28h288v96 q0 66 47 113t113 47h576q66 0 113 -47t47 -113v-96h288q40 0 68 -28t28 -68z" />
|
||||
<glyph unicode="" d="M394 184q-8 -9 -20 3q-13 11 -4 19q8 9 20 -3q12 -11 4 -19zM352 245q9 -12 0 -19q-8 -6 -17 7t0 18q9 7 17 -6zM291 305q-5 -7 -13 -2q-10 5 -7 12q3 5 13 2q10 -5 7 -12zM322 271q-6 -7 -16 3q-9 11 -2 16q6 6 16 -3q9 -11 2 -16zM451 159q-4 -12 -19 -6q-17 4 -13 15 t19 7q16 -5 13 -16zM514 154q0 -11 -16 -11q-17 -2 -17 11q0 11 16 11q17 2 17 -11zM572 164q2 -10 -14 -14t-18 8t14 15q16 2 18 -9zM1536 1120v-960q0 -119 -84.5 -203.5t-203.5 -84.5h-224q-16 0 -24.5 1t-19.5 5t-16 14.5t-5 27.5v239q0 97 -52 142q57 6 102.5 18t94 39 t81 66.5t53 105t20.5 150.5q0 121 -79 206q37 91 -8 204q-28 9 -81 -11t-92 -44l-38 -24q-93 26 -192 26t-192 -26q-16 11 -42.5 27t-83.5 38.5t-86 13.5q-44 -113 -7 -204q-79 -85 -79 -206q0 -85 20.5 -150t52.5 -105t80.5 -67t94 -39t102.5 -18q-40 -36 -49 -103 q-21 -10 -45 -15t-57 -5t-65.5 21.5t-55.5 62.5q-19 32 -48.5 52t-49.5 24l-20 3q-21 0 -29 -4.5t-5 -11.5t9 -14t13 -12l7 -5q22 -10 43.5 -38t31.5 -51l10 -23q13 -38 44 -61.5t67 -30t69.5 -7t55.5 3.5l23 4q0 -38 0.5 -103t0.5 -68q0 -22 -11 -33.5t-22 -13t-33 -1.5 h-224q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1280 64q0 26 -19 45t-45 19t-45 -19t-19 -45t19 -45t45 -19t45 19t19 45zM1536 64q0 26 -19 45t-45 19t-45 -19t-19 -45t19 -45t45 -19t45 19t19 45zM1664 288v-320q0 -40 -28 -68t-68 -28h-1472q-40 0 -68 28t-28 68v320q0 40 28 68t68 28h427q21 -56 70.5 -92 t110.5 -36h256q61 0 110.5 36t70.5 92h427q40 0 68 -28t28 -68zM1339 936q-17 -40 -59 -40h-256v-448q0 -26 -19 -45t-45 -19h-256q-26 0 -45 19t-19 45v448h-256q-42 0 -59 40q-17 39 14 69l448 448q18 19 45 19t45 -19l448 -448q31 -30 14 -69z" />
|
||||
<glyph unicode="" d="M1407 710q0 44 -7 113.5t-18 96.5q-12 30 -17 44t-9 36.5t-4 48.5q0 23 5 68.5t5 67.5q0 37 -10 55q-4 1 -13 1q-19 0 -58 -4.5t-59 -4.5q-60 0 -176 24t-175 24q-43 0 -94.5 -11.5t-85 -23.5t-89.5 -34q-137 -54 -202 -103q-96 -73 -159.5 -189.5t-88 -236t-24.5 -248.5 q0 -40 12.5 -120t12.5 -121q0 -23 -11 -66.5t-11 -65.5t12 -36.5t34 -14.5q24 0 72.5 11t73.5 11q57 0 169.5 -15.5t169.5 -15.5q181 0 284 36q129 45 235.5 152.5t166 245.5t59.5 275zM1535 712q0 -165 -70 -327.5t-196 -288t-281 -180.5q-124 -44 -326 -44 q-57 0 -170 14.5t-169 14.5q-24 0 -72.5 -14.5t-73.5 -14.5q-73 0 -123.5 55.5t-50.5 128.5q0 24 11 68t11 67q0 40 -12.5 120.5t-12.5 121.5q0 111 18 217.5t54.5 209.5t100.5 194t150 156q78 59 232 120q194 78 316 78q60 0 175.5 -24t173.5 -24q19 0 57 5t58 5 q81 0 118 -50.5t37 -134.5q0 -23 -5 -68t-5 -68q0 -10 1 -18.5t3 -17t4 -13.5t6.5 -16t6.5 -17q16 -40 25 -118.5t9 -136.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M1408 296q0 -27 -10 -70.5t-21 -68.5q-21 -50 -122 -106q-94 -51 -186 -51q-27 0 -52.5 3.5t-57.5 12.5t-47.5 14.5t-55.5 20.5t-49 18q-98 35 -175 83q-128 79 -264.5 215.5t-215.5 264.5q-48 77 -83 175q-3 9 -18 49t-20.5 55.5t-14.5 47.5t-12.5 57.5t-3.5 52.5 q0 92 51 186q56 101 106 122q25 11 68.5 21t70.5 10q14 0 21 -3q18 -6 53 -76q11 -19 30 -54t35 -63.5t31 -53.5q3 -4 17.5 -25t21.5 -35.5t7 -28.5q0 -20 -28.5 -50t-62 -55t-62 -53t-28.5 -46q0 -9 5 -22.5t8.5 -20.5t14 -24t11.5 -19q76 -137 174 -235t235 -174 q2 -1 19 -11.5t24 -14t20.5 -8.5t22.5 -5q18 0 46 28.5t53 62t55 62t50 28.5q14 0 28.5 -7t35.5 -21.5t25 -17.5q25 -15 53.5 -31t63.5 -35t54 -30q70 -35 76 -53q3 -7 3 -21z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M1120 1280h-832q-66 0 -113 -47t-47 -113v-832q0 -66 47 -113t113 -47h832q66 0 113 47t47 113v832q0 66 -47 113t-113 47zM1408 1120v-832q0 -119 -84.5 -203.5t-203.5 -84.5h-832q-119 0 -203.5 84.5t-84.5 203.5v832q0 119 84.5 203.5t203.5 84.5h832 q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1280" d="M1152 1280h-1024v-1242l423 406l89 85l89 -85l423 -406v1242zM1164 1408q23 0 44 -9q33 -13 52.5 -41t19.5 -62v-1289q0 -34 -19.5 -62t-52.5 -41q-19 -8 -44 -8q-48 0 -83 32l-441 424l-441 -424q-36 -33 -83 -33q-23 0 -44 9q-33 13 -52.5 41t-19.5 62v1289 q0 34 19.5 62t52.5 41q21 9 44 9h1048z" />
|
||||
<glyph unicode="" d="M1280 343q0 11 -2 16q-3 8 -38.5 29.5t-88.5 49.5l-53 29q-5 3 -19 13t-25 15t-21 5q-18 0 -47 -32.5t-57 -65.5t-44 -33q-7 0 -16.5 3.5t-15.5 6.5t-17 9.5t-14 8.5q-99 55 -170.5 126.5t-126.5 170.5q-2 3 -8.5 14t-9.5 17t-6.5 15.5t-3.5 16.5q0 13 20.5 33.5t45 38.5 t45 39.5t20.5 36.5q0 10 -5 21t-15 25t-13 19q-3 6 -15 28.5t-25 45.5t-26.5 47.5t-25 40.5t-16.5 18t-16 2q-48 0 -101 -22q-46 -21 -80 -94.5t-34 -130.5q0 -16 2.5 -34t5 -30.5t9 -33t10 -29.5t12.5 -33t11 -30q60 -164 216.5 -320.5t320.5 -216.5q6 -2 30 -11t33 -12.5 t29.5 -10t33 -9t30.5 -5t34 -2.5q57 0 130.5 34t94.5 80q22 53 22 101zM1536 1120v-960q0 -119 -84.5 -203.5t-203.5 -84.5h-960q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1620 1128q-67 -98 -162 -167q1 -14 1 -42q0 -130 -38 -259.5t-115.5 -248.5t-184.5 -210.5t-258 -146t-323 -54.5q-271 0 -496 145q35 -4 78 -4q225 0 401 138q-105 2 -188 64.5t-114 159.5q33 -5 61 -5q43 0 85 11q-112 23 -185.5 111.5t-73.5 205.5v4q68 -38 146 -41 q-66 44 -105 115t-39 154q0 88 44 163q121 -149 294.5 -238.5t371.5 -99.5q-8 38 -8 74q0 134 94.5 228.5t228.5 94.5q140 0 236 -102q109 21 205 78q-37 -115 -142 -178q93 10 186 50z" />
|
||||
<glyph unicode="" horiz-adv-x="768" d="M511 980h257l-30 -284h-227v-824h-341v824h-170v284h170v171q0 182 86 275.5t283 93.5h227v-284h-142q-39 0 -62.5 -6.5t-34 -23.5t-13.5 -34.5t-3 -49.5v-142z" />
|
||||
<glyph unicode="" d="M1536 640q0 -251 -146.5 -451.5t-378.5 -277.5q-27 -5 -39.5 7t-12.5 30v211q0 97 -52 142q57 6 102.5 18t94 39t81 66.5t53 105t20.5 150.5q0 121 -79 206q37 91 -8 204q-28 9 -81 -11t-92 -44l-38 -24q-93 26 -192 26t-192 -26q-16 11 -42.5 27t-83.5 38.5t-86 13.5 q-44 -113 -7 -204q-79 -85 -79 -206q0 -85 20.5 -150t52.5 -105t80.5 -67t94 -39t102.5 -18q-40 -36 -49 -103q-21 -10 -45 -15t-57 -5t-65.5 21.5t-55.5 62.5q-19 32 -48.5 52t-49.5 24l-20 3q-21 0 -29 -4.5t-5 -11.5t9 -14t13 -12l7 -5q22 -10 43.5 -38t31.5 -51l10 -23 q13 -38 44 -61.5t67 -30t69.5 -7t55.5 3.5l23 4q0 -38 0.5 -89t0.5 -54q0 -18 -13 -30t-40 -7q-232 77 -378.5 277.5t-146.5 451.5q0 209 103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1664 960v-256q0 -26 -19 -45t-45 -19h-64q-26 0 -45 19t-19 45v256q0 106 -75 181t-181 75t-181 -75t-75 -181v-192h96q40 0 68 -28t28 -68v-576q0 -40 -28 -68t-68 -28h-960q-40 0 -68 28t-28 68v576q0 40 28 68t68 28h672v192q0 185 131.5 316.5t316.5 131.5 t316.5 -131.5t131.5 -316.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M1760 1408q66 0 113 -47t47 -113v-1216q0 -66 -47 -113t-113 -47h-1600q-66 0 -113 47t-47 113v1216q0 66 47 113t113 47h1600zM160 1280q-13 0 -22.5 -9.5t-9.5 -22.5v-224h1664v224q0 13 -9.5 22.5t-22.5 9.5h-1600zM1760 0q13 0 22.5 9.5t9.5 22.5v608h-1664v-608 q0 -13 9.5 -22.5t22.5 -9.5h1600zM256 128v128h256v-128h-256zM640 128v128h384v-128h-384z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M384 192q0 -80 -56 -136t-136 -56t-136 56t-56 136t56 136t136 56t136 -56t56 -136zM896 69q2 -28 -17 -48q-18 -21 -47 -21h-135q-25 0 -43 16.5t-20 41.5q-22 229 -184.5 391.5t-391.5 184.5q-25 2 -41.5 20t-16.5 43v135q0 29 21 47q17 17 43 17h5q160 -13 306 -80.5 t259 -181.5q114 -113 181.5 -259t80.5 -306zM1408 67q2 -27 -18 -47q-18 -20 -46 -20h-143q-26 0 -44.5 17.5t-19.5 42.5q-12 215 -101 408.5t-231.5 336t-336 231.5t-408.5 102q-25 1 -42.5 19.5t-17.5 43.5v143q0 28 20 46q18 18 44 18h3q262 -13 501.5 -120t425.5 -294 q187 -186 294 -425.5t120 -501.5z" />
|
||||
<glyph unicode="" d="M1040 320q0 -33 -23.5 -56.5t-56.5 -23.5t-56.5 23.5t-23.5 56.5t23.5 56.5t56.5 23.5t56.5 -23.5t23.5 -56.5zM1296 320q0 -33 -23.5 -56.5t-56.5 -23.5t-56.5 23.5t-23.5 56.5t23.5 56.5t56.5 23.5t56.5 -23.5t23.5 -56.5zM1408 160v320q0 13 -9.5 22.5t-22.5 9.5 h-1216q-13 0 -22.5 -9.5t-9.5 -22.5v-320q0 -13 9.5 -22.5t22.5 -9.5h1216q13 0 22.5 9.5t9.5 22.5zM178 640h1180l-157 482q-4 13 -16 21.5t-26 8.5h-782q-14 0 -26 -8.5t-16 -21.5zM1536 480v-320q0 -66 -47 -113t-113 -47h-1216q-66 0 -113 47t-47 113v320q0 25 16 75 l197 606q17 53 63 86t101 33h782q55 0 101 -33t63 -86l197 -606q16 -50 16 -75z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1664 896q53 0 90.5 -37.5t37.5 -90.5t-37.5 -90.5t-90.5 -37.5v-384q0 -52 -38 -90t-90 -38q-417 347 -812 380q-58 -19 -91 -66t-31 -100.5t40 -92.5q-20 -33 -23 -65.5t6 -58t33.5 -55t48 -50t61.5 -50.5q-29 -58 -111.5 -83t-168.5 -11.5t-132 55.5q-7 23 -29.5 87.5 t-32 94.5t-23 89t-15 101t3.5 98.5t22 110.5h-122q-66 0 -113 47t-47 113v192q0 66 47 113t113 47h480q435 0 896 384q52 0 90 -38t38 -90v-384zM1536 292v954q-394 -302 -768 -343v-270q377 -42 768 -341z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M848 -160q0 16 -16 16q-59 0 -101.5 42.5t-42.5 101.5q0 16 -16 16t-16 -16q0 -73 51.5 -124.5t124.5 -51.5q16 0 16 16zM183 128h1298q-164 181 -246.5 411.5t-82.5 484.5q0 256 -320 256t-320 -256q0 -254 -82.5 -484.5t-246.5 -411.5zM1664 128q0 -52 -38 -90t-90 -38 h-448q0 -106 -75 -181t-181 -75t-181 75t-75 181h-448q-52 0 -90 38t-38 90q190 161 287 397.5t97 498.5q0 165 96 262t264 117q-8 18 -8 37q0 40 28 68t68 28t68 -28t28 -68q0 -19 -8 -37q168 -20 264 -117t96 -262q0 -262 97 -498.5t287 -397.5z" />
|
||||
<glyph unicode="" d="M1376 640l138 -135q30 -28 20 -70q-12 -41 -52 -51l-188 -48l53 -186q12 -41 -19 -70q-29 -31 -70 -19l-186 53l-48 -188q-10 -40 -51 -52q-12 -2 -19 -2q-31 0 -51 22l-135 138l-135 -138q-28 -30 -70 -20q-41 11 -51 52l-48 188l-186 -53q-41 -12 -70 19q-31 29 -19 70 l53 186l-188 48q-40 10 -52 51q-10 42 20 70l138 135l-138 135q-30 28 -20 70q12 41 52 51l188 48l-53 186q-12 41 19 70q29 31 70 19l186 -53l48 188q10 41 51 51q41 12 70 -19l135 -139l135 139q29 30 70 19q41 -10 51 -51l48 -188l186 53q41 12 70 -19q31 -29 19 -70 l-53 -186l188 -48q40 -10 52 -51q10 -42 -20 -70z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M256 192q0 26 -19 45t-45 19t-45 -19t-19 -45t19 -45t45 -19t45 19t19 45zM1664 768q0 51 -39 89.5t-89 38.5h-576q0 20 15 48.5t33 55t33 68t15 84.5q0 67 -44.5 97.5t-115.5 30.5q-24 0 -90 -139q-24 -44 -37 -65q-40 -64 -112 -145q-71 -81 -101 -106 q-69 -57 -140 -57h-32v-640h32q72 0 167 -32t193.5 -64t179.5 -32q189 0 189 167q0 26 -5 56q30 16 47.5 52.5t17.5 73.5t-18 69q53 50 53 119q0 25 -10 55.5t-25 47.5h331q52 0 90 38t38 90zM1792 769q0 -105 -75.5 -181t-180.5 -76h-169q-4 -62 -37 -119q3 -21 3 -43 q0 -101 -60 -178q1 -139 -85 -219.5t-227 -80.5q-133 0 -322 69q-164 59 -223 59h-288q-53 0 -90.5 37.5t-37.5 90.5v640q0 53 37.5 90.5t90.5 37.5h288q10 0 21.5 4.5t23.5 14t22.5 18t24 22.5t20.5 21.5t19 21.5t14 17q65 74 100 129q13 21 33 62t37 72t40.5 63t55 49.5 t69.5 17.5q125 0 206.5 -67t81.5 -189q0 -68 -22 -128h374q104 0 180 -76t76 -179z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1376 128h32v640h-32q-35 0 -67.5 12t-62.5 37t-50 46t-49 54q-2 3 -3.5 4.5t-4 4.5t-4.5 5q-72 81 -112 145q-14 22 -38 68q-1 3 -10.5 22.5t-18.5 36t-20 35.5t-21.5 30.5t-18.5 11.5q-71 0 -115.5 -30.5t-44.5 -97.5q0 -43 15 -84.5t33 -68t33 -55t15 -48.5h-576 q-50 0 -89 -38.5t-39 -89.5q0 -52 38 -90t90 -38h331q-15 -17 -25 -47.5t-10 -55.5q0 -69 53 -119q-18 -32 -18 -69t17.5 -73.5t47.5 -52.5q-4 -24 -4 -56q0 -85 48.5 -126t135.5 -41q84 0 183 32t194 64t167 32zM1664 192q0 26 -19 45t-45 19t-45 -19t-19 -45t19 -45 t45 -19t45 19t19 45zM1792 768v-640q0 -53 -37.5 -90.5t-90.5 -37.5h-288q-59 0 -223 -59q-190 -69 -317 -69q-142 0 -230 77.5t-87 217.5l1 5q-61 76 -61 178q0 22 3 43q-33 57 -37 119h-169q-105 0 -180.5 76t-75.5 181q0 103 76 179t180 76h374q-22 60 -22 128 q0 122 81.5 189t206.5 67q38 0 69.5 -17.5t55 -49.5t40.5 -63t37 -72t33 -62q35 -55 100 -129q2 -3 14 -17t19 -21.5t20.5 -21.5t24 -22.5t22.5 -18t23.5 -14t21.5 -4.5h288q53 0 90.5 -37.5t37.5 -90.5z" />
|
||||
<glyph unicode="" d="M1280 -64q0 26 -19 45t-45 19t-45 -19t-19 -45t19 -45t45 -19t45 19t19 45zM1408 700q0 189 -167 189q-26 0 -56 -5q-16 30 -52.5 47.5t-73.5 17.5t-69 -18q-50 53 -119 53q-25 0 -55.5 -10t-47.5 -25v331q0 52 -38 90t-90 38q-51 0 -89.5 -39t-38.5 -89v-576 q-20 0 -48.5 15t-55 33t-68 33t-84.5 15q-67 0 -97.5 -44.5t-30.5 -115.5q0 -24 139 -90q44 -24 65 -37q64 -40 145 -112q81 -71 106 -101q57 -69 57 -140v-32h640v32q0 72 32 167t64 193.5t32 179.5zM1536 705q0 -133 -69 -322q-59 -164 -59 -223v-288q0 -53 -37.5 -90.5 t-90.5 -37.5h-640q-53 0 -90.5 37.5t-37.5 90.5v288q0 10 -4.5 21.5t-14 23.5t-18 22.5t-22.5 24t-21.5 20.5t-21.5 19t-17 14q-74 65 -129 100q-21 13 -62 33t-72 37t-63 40.5t-49.5 55t-17.5 69.5q0 125 67 206.5t189 81.5q68 0 128 -22v374q0 104 76 180t179 76 q105 0 181 -75.5t76 -180.5v-169q62 -4 119 -37q21 3 43 3q101 0 178 -60q139 1 219.5 -85t80.5 -227z" />
|
||||
<glyph unicode="" d="M1408 576q0 84 -32 183t-64 194t-32 167v32h-640v-32q0 -35 -12 -67.5t-37 -62.5t-46 -50t-54 -49q-9 -8 -14 -12q-81 -72 -145 -112q-22 -14 -68 -38q-3 -1 -22.5 -10.5t-36 -18.5t-35.5 -20t-30.5 -21.5t-11.5 -18.5q0 -71 30.5 -115.5t97.5 -44.5q43 0 84.5 15t68 33 t55 33t48.5 15v-576q0 -50 38.5 -89t89.5 -39q52 0 90 38t38 90v331q46 -35 103 -35q69 0 119 53q32 -18 69 -18t73.5 17.5t52.5 47.5q24 -4 56 -4q85 0 126 48.5t41 135.5zM1280 1344q0 26 -19 45t-45 19t-45 -19t-19 -45t19 -45t45 -19t45 19t19 45zM1536 580 q0 -142 -77.5 -230t-217.5 -87l-5 1q-76 -61 -178 -61q-22 0 -43 3q-54 -30 -119 -37v-169q0 -105 -76 -180.5t-181 -75.5q-103 0 -179 76t-76 180v374q-54 -22 -128 -22q-121 0 -188.5 81.5t-67.5 206.5q0 38 17.5 69.5t49.5 55t63 40.5t72 37t62 33q55 35 129 100 q3 2 17 14t21.5 19t21.5 20.5t22.5 24t18 22.5t14 23.5t4.5 21.5v288q0 53 37.5 90.5t90.5 37.5h640q53 0 90.5 -37.5t37.5 -90.5v-288q0 -59 59 -223q69 -190 69 -317z" />
|
||||
<glyph unicode="" d="M1280 576v128q0 26 -19 45t-45 19h-502l189 189q19 19 19 45t-19 45l-91 91q-18 18 -45 18t-45 -18l-362 -362l-91 -91q-18 -18 -18 -45t18 -45l91 -91l362 -362q18 -18 45 -18t45 18l91 91q18 18 18 45t-18 45l-189 189h502q26 0 45 19t19 45zM1536 640 q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M1285 640q0 27 -18 45l-91 91l-362 362q-18 18 -45 18t-45 -18l-91 -91q-18 -18 -18 -45t18 -45l189 -189h-502q-26 0 -45 -19t-19 -45v-128q0 -26 19 -45t45 -19h502l-189 -189q-19 -19 -19 -45t19 -45l91 -91q18 -18 45 -18t45 18l362 362l91 91q18 18 18 45zM1536 640 q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M1284 641q0 27 -18 45l-362 362l-91 91q-18 18 -45 18t-45 -18l-91 -91l-362 -362q-18 -18 -18 -45t18 -45l91 -91q18 -18 45 -18t45 18l189 189v-502q0 -26 19 -45t45 -19h128q26 0 45 19t19 45v502l189 -189q19 -19 45 -19t45 19l91 91q18 18 18 45zM1536 640 q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M1284 639q0 27 -18 45l-91 91q-18 18 -45 18t-45 -18l-189 -189v502q0 26 -19 45t-45 19h-128q-26 0 -45 -19t-19 -45v-502l-189 189q-19 19 -45 19t-45 -19l-91 -91q-18 -18 -18 -45t18 -45l362 -362l91 -91q18 -18 45 -18t45 18l91 91l362 362q18 18 18 45zM1536 640 q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M768 1408q209 0 385.5 -103t279.5 -279.5t103 -385.5t-103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103zM1042 887q-2 -1 -9.5 -9.5t-13.5 -9.5q2 0 4.5 5t5 11t3.5 7q6 7 22 15q14 6 52 12q34 8 51 -11 q-2 2 9.5 13t14.5 12q3 2 15 4.5t15 7.5l2 22q-12 -1 -17.5 7t-6.5 21q0 -2 -6 -8q0 7 -4.5 8t-11.5 -1t-9 -1q-10 3 -15 7.5t-8 16.5t-4 15q-2 5 -9.5 10.5t-9.5 10.5q-1 2 -2.5 5.5t-3 6.5t-4 5.5t-5.5 2.5t-7 -5t-7.5 -10t-4.5 -5q-3 2 -6 1.5t-4.5 -1t-4.5 -3t-5 -3.5 q-3 -2 -8.5 -3t-8.5 -2q15 5 -1 11q-10 4 -16 3q9 4 7.5 12t-8.5 14h5q-1 4 -8.5 8.5t-17.5 8.5t-13 6q-8 5 -34 9.5t-33 0.5q-5 -6 -4.5 -10.5t4 -14t3.5 -12.5q1 -6 -5.5 -13t-6.5 -12q0 -7 14 -15.5t10 -21.5q-3 -8 -16 -16t-16 -12q-5 -8 -1.5 -18.5t10.5 -16.5 q2 -2 1.5 -4t-3.5 -4.5t-5.5 -4t-6.5 -3.5l-3 -2q-11 -5 -20.5 6t-13.5 26q-7 25 -16 30q-23 8 -29 -1q-5 13 -41 26q-25 9 -58 4q6 1 0 15q-7 15 -19 12q3 6 4 17.5t1 13.5q3 13 12 23q1 1 7 8.5t9.5 13.5t0.5 6q35 -4 50 11q5 5 11.5 17t10.5 17q9 6 14 5.5t14.5 -5.5 t14.5 -5q14 -1 15.5 11t-7.5 20q12 -1 3 17q-5 7 -8 9q-12 4 -27 -5q-8 -4 2 -8q-1 1 -9.5 -10.5t-16.5 -17.5t-16 5q-1 1 -5.5 13.5t-9.5 13.5q-8 0 -16 -15q3 8 -11 15t-24 8q19 12 -8 27q-7 4 -20.5 5t-19.5 -4q-5 -7 -5.5 -11.5t5 -8t10.5 -5.5t11.5 -4t8.5 -3 q14 -10 8 -14q-2 -1 -8.5 -3.5t-11.5 -4.5t-6 -4q-3 -4 0 -14t-2 -14q-5 5 -9 17.5t-7 16.5q7 -9 -25 -6l-10 1q-4 0 -16 -2t-20.5 -1t-13.5 8q-4 8 0 20q1 4 4 2q-4 3 -11 9.5t-10 8.5q-46 -15 -94 -41q6 -1 12 1q5 2 13 6.5t10 5.5q34 14 42 7l5 5q14 -16 20 -25 q-7 4 -30 1q-20 -6 -22 -12q7 -12 5 -18q-4 3 -11.5 10t-14.5 11t-15 5q-16 0 -22 -1q-146 -80 -235 -222q7 -7 12 -8q4 -1 5 -9t2.5 -11t11.5 3q9 -8 3 -19q1 1 44 -27q19 -17 21 -21q3 -11 -10 -18q-1 2 -9 9t-9 4q-3 -5 0.5 -18.5t10.5 -12.5q-7 0 -9.5 -16t-2.5 -35.5 t-1 -23.5l2 -1q-3 -12 5.5 -34.5t21.5 -19.5q-13 -3 20 -43q6 -8 8 -9q3 -2 12 -7.5t15 -10t10 -10.5q4 -5 10 -22.5t14 -23.5q-2 -6 9.5 -20t10.5 -23q-1 0 -2.5 -1t-2.5 -1q3 -7 15.5 -14t15.5 -13q1 -3 2 -10t3 -11t8 -2q2 20 -24 62q-15 25 -17 29q-3 5 -5.5 15.5 t-4.5 14.5q2 0 6 -1.5t8.5 -3.5t7.5 -4t2 -3q-3 -7 2 -17.5t12 -18.5t17 -19t12 -13q6 -6 14 -19.5t0 -13.5q9 0 20 -10t17 -20q5 -8 8 -26t5 -24q2 -7 8.5 -13.5t12.5 -9.5l16 -8t13 -7q5 -2 18.5 -10.5t21.5 -11.5q10 -4 16 -4t14.5 2.5t13.5 3.5q15 2 29 -15t21 -21 q36 -19 55 -11q-2 -1 0.5 -7.5t8 -15.5t9 -14.5t5.5 -8.5q5 -6 18 -15t18 -15q6 4 7 9q-3 -8 7 -20t18 -10q14 3 14 32q-31 -15 -49 18q0 1 -2.5 5.5t-4 8.5t-2.5 8.5t0 7.5t5 3q9 0 10 3.5t-2 12.5t-4 13q-1 8 -11 20t-12 15q-5 -9 -16 -8t-16 9q0 -1 -1.5 -5.5t-1.5 -6.5 q-13 0 -15 1q1 3 2.5 17.5t3.5 22.5q1 4 5.5 12t7.5 14.5t4 12.5t-4.5 9.5t-17.5 2.5q-19 -1 -26 -20q-1 -3 -3 -10.5t-5 -11.5t-9 -7q-7 -3 -24 -2t-24 5q-13 8 -22.5 29t-9.5 37q0 10 2.5 26.5t3 25t-5.5 24.5q3 2 9 9.5t10 10.5q2 1 4.5 1.5t4.5 0t4 1.5t3 6q-1 1 -4 3 q-3 3 -4 3q7 -3 28.5 1.5t27.5 -1.5q15 -11 22 2q0 1 -2.5 9.5t-0.5 13.5q5 -27 29 -9q3 -3 15.5 -5t17.5 -5q3 -2 7 -5.5t5.5 -4.5t5 0.5t8.5 6.5q10 -14 12 -24q11 -40 19 -44q7 -3 11 -2t4.5 9.5t0 14t-1.5 12.5l-1 8v18l-1 8q-15 3 -18.5 12t1.5 18.5t15 18.5q1 1 8 3.5 t15.5 6.5t12.5 8q21 19 15 35q7 0 11 9q-1 0 -5 3t-7.5 5t-4.5 2q9 5 2 16q5 3 7.5 11t7.5 10q9 -12 21 -2q7 8 1 16q5 7 20.5 10.5t18.5 9.5q7 -2 8 2t1 12t3 12q4 5 15 9t13 5l17 11q3 4 0 4q18 -2 31 11q10 11 -6 20q3 6 -3 9.5t-15 5.5q3 1 11.5 0.5t10.5 1.5 q15 10 -7 16q-17 5 -43 -12zM879 10q206 36 351 189q-3 3 -12.5 4.5t-12.5 3.5q-18 7 -24 8q1 7 -2.5 13t-8 9t-12.5 8t-11 7q-2 2 -7 6t-7 5.5t-7.5 4.5t-8.5 2t-10 -1l-3 -1q-3 -1 -5.5 -2.5t-5.5 -3t-4 -3t0 -2.5q-21 17 -36 22q-5 1 -11 5.5t-10.5 7t-10 1.5t-11.5 -7 q-5 -5 -6 -15t-2 -13q-7 5 0 17.5t2 18.5q-3 6 -10.5 4.5t-12 -4.5t-11.5 -8.5t-9 -6.5t-8.5 -5.5t-8.5 -7.5q-3 -4 -6 -12t-5 -11q-2 4 -11.5 6.5t-9.5 5.5q2 -10 4 -35t5 -38q7 -31 -12 -48q-27 -25 -29 -40q-4 -22 12 -26q0 -7 -8 -20.5t-7 -21.5q0 -6 2 -16z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M384 64q0 26 -19 45t-45 19t-45 -19t-19 -45t19 -45t45 -19t45 19t19 45zM1028 484l-682 -682q-37 -37 -90 -37q-52 0 -91 37l-106 108q-38 36 -38 90q0 53 38 91l681 681q39 -98 114.5 -173.5t173.5 -114.5zM1662 919q0 -39 -23 -106q-47 -134 -164.5 -217.5 t-258.5 -83.5q-185 0 -316.5 131.5t-131.5 316.5t131.5 316.5t316.5 131.5q58 0 121.5 -16.5t107.5 -46.5q16 -11 16 -28t-16 -28l-293 -169v-224l193 -107q5 3 79 48.5t135.5 81t70.5 35.5q15 0 23.5 -10t8.5 -25z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1024 128h640v128h-640v-128zM640 640h1024v128h-1024v-128zM1280 1152h384v128h-384v-128zM1792 320v-256q0 -26 -19 -45t-45 -19h-1664q-26 0 -45 19t-19 45v256q0 26 19 45t45 19h1664q26 0 45 -19t19 -45zM1792 832v-256q0 -26 -19 -45t-45 -19h-1664q-26 0 -45 19 t-19 45v256q0 26 19 45t45 19h1664q26 0 45 -19t19 -45zM1792 1344v-256q0 -26 -19 -45t-45 -19h-1664q-26 0 -45 19t-19 45v256q0 26 19 45t45 19h1664q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M1403 1241q17 -41 -14 -70l-493 -493v-742q0 -42 -39 -59q-13 -5 -25 -5q-27 0 -45 19l-256 256q-19 19 -19 45v486l-493 493q-31 29 -14 70q17 39 59 39h1280q42 0 59 -39z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M640 1280h512v128h-512v-128zM1792 640v-480q0 -66 -47 -113t-113 -47h-1472q-66 0 -113 47t-47 113v480h672v-160q0 -26 19 -45t45 -19h320q26 0 45 19t19 45v160h672zM1024 640v-128h-256v128h256zM1792 1120v-384h-1792v384q0 66 47 113t113 47h352v160q0 40 28 68 t68 28h576q40 0 68 -28t28 -68v-160h352q66 0 113 -47t47 -113z" />
|
||||
<glyph unicode="" d="M1283 995l-355 -355l355 -355l144 144q29 31 70 14q39 -17 39 -59v-448q0 -26 -19 -45t-45 -19h-448q-42 0 -59 40q-17 39 14 69l144 144l-355 355l-355 -355l144 -144q31 -30 14 -69q-17 -40 -59 -40h-448q-26 0 -45 19t-19 45v448q0 42 40 59q39 17 69 -14l144 -144 l355 355l-355 355l-144 -144q-19 -19 -45 -19q-12 0 -24 5q-40 17 -40 59v448q0 26 19 45t45 19h448q42 0 59 -40q17 -39 -14 -69l-144 -144l355 -355l355 355l-144 144q-31 30 -14 69q17 40 59 40h448q26 0 45 -19t19 -45v-448q0 -42 -39 -59q-13 -5 -25 -5q-26 0 -45 19z " />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M593 640q-162 -5 -265 -128h-134q-82 0 -138 40.5t-56 118.5q0 353 124 353q6 0 43.5 -21t97.5 -42.5t119 -21.5q67 0 133 23q-5 -37 -5 -66q0 -139 81 -256zM1664 3q0 -120 -73 -189.5t-194 -69.5h-874q-121 0 -194 69.5t-73 189.5q0 53 3.5 103.5t14 109t26.5 108.5 t43 97.5t62 81t85.5 53.5t111.5 20q10 0 43 -21.5t73 -48t107 -48t135 -21.5t135 21.5t107 48t73 48t43 21.5q61 0 111.5 -20t85.5 -53.5t62 -81t43 -97.5t26.5 -108.5t14 -109t3.5 -103.5zM640 1280q0 -106 -75 -181t-181 -75t-181 75t-75 181t75 181t181 75t181 -75 t75 -181zM1344 896q0 -159 -112.5 -271.5t-271.5 -112.5t-271.5 112.5t-112.5 271.5t112.5 271.5t271.5 112.5t271.5 -112.5t112.5 -271.5zM1920 671q0 -78 -56 -118.5t-138 -40.5h-134q-103 123 -265 128q81 117 81 256q0 29 -5 66q66 -23 133 -23q59 0 119 21.5t97.5 42.5 t43.5 21q124 0 124 -353zM1792 1280q0 -106 -75 -181t-181 -75t-181 75t-75 181t75 181t181 75t181 -75t75 -181z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1456 320q0 40 -28 68l-208 208q-28 28 -68 28q-42 0 -72 -32q3 -3 19 -18.5t21.5 -21.5t15 -19t13 -25.5t3.5 -27.5q0 -40 -28 -68t-68 -28q-15 0 -27.5 3.5t-25.5 13t-19 15t-21.5 21.5t-18.5 19q-33 -31 -33 -73q0 -40 28 -68l206 -207q27 -27 68 -27q40 0 68 26 l147 146q28 28 28 67zM753 1025q0 40 -28 68l-206 207q-28 28 -68 28q-39 0 -68 -27l-147 -146q-28 -28 -28 -67q0 -40 28 -68l208 -208q27 -27 68 -27q42 0 72 31q-3 3 -19 18.5t-21.5 21.5t-15 19t-13 25.5t-3.5 27.5q0 40 28 68t68 28q15 0 27.5 -3.5t25.5 -13t19 -15 t21.5 -21.5t18.5 -19q33 31 33 73zM1648 320q0 -120 -85 -203l-147 -146q-83 -83 -203 -83q-121 0 -204 85l-206 207q-83 83 -83 203q0 123 88 209l-88 88q-86 -88 -208 -88q-120 0 -204 84l-208 208q-84 84 -84 204t85 203l147 146q83 83 203 83q121 0 204 -85l206 -207 q83 -83 83 -203q0 -123 -88 -209l88 -88q86 88 208 88q120 0 204 -84l208 -208q84 -84 84 -204z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M1920 384q0 -159 -112.5 -271.5t-271.5 -112.5h-1088q-185 0 -316.5 131.5t-131.5 316.5q0 132 71 241.5t187 163.5q-2 28 -2 43q0 212 150 362t362 150q158 0 286.5 -88t187.5 -230q70 62 166 62q106 0 181 -75t75 -181q0 -75 -41 -138q129 -30 213 -134.5t84 -239.5z " />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1527 88q56 -89 21.5 -152.5t-140.5 -63.5h-1152q-106 0 -140.5 63.5t21.5 152.5l503 793v399h-64q-26 0 -45 19t-19 45t19 45t45 19h512q26 0 45 -19t19 -45t-19 -45t-45 -19h-64v-399zM748 813l-272 -429h712l-272 429l-20 31v37v399h-128v-399v-37z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M960 640q26 0 45 -19t19 -45t-19 -45t-45 -19t-45 19t-19 45t19 45t45 19zM1260 576l507 -398q28 -20 25 -56q-5 -35 -35 -51l-128 -64q-13 -7 -29 -7q-17 0 -31 8l-690 387l-110 -66q-8 -4 -12 -5q14 -49 10 -97q-7 -77 -56 -147.5t-132 -123.5q-132 -84 -277 -84 q-136 0 -222 78q-90 84 -79 207q7 76 56 147t131 124q132 84 278 84q83 0 151 -31q9 13 22 22l122 73l-122 73q-13 9 -22 22q-68 -31 -151 -31q-146 0 -278 84q-82 53 -131 124t-56 147q-5 59 15.5 113t63.5 93q85 79 222 79q145 0 277 -84q83 -52 132 -123t56 -148 q4 -48 -10 -97q4 -1 12 -5l110 -66l690 387q14 8 31 8q16 0 29 -7l128 -64q30 -16 35 -51q3 -36 -25 -56zM579 836q46 42 21 108t-106 117q-92 59 -192 59q-74 0 -113 -36q-46 -42 -21 -108t106 -117q92 -59 192 -59q74 0 113 36zM494 91q81 51 106 117t-21 108 q-39 36 -113 36q-100 0 -192 -59q-81 -51 -106 -117t21 -108q39 -36 113 -36q100 0 192 59zM672 704l96 -58v11q0 36 33 56l14 8l-79 47l-26 -26q-3 -3 -10 -11t-12 -12q-2 -2 -4 -3.5t-3 -2.5zM896 480l96 -32l736 576l-128 64l-768 -431v-113l-160 -96l9 -8q2 -2 7 -6 q4 -4 11 -12t11 -12l26 -26zM1600 64l128 64l-520 408l-177 -138q-2 -3 -13 -7z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1696 1152q40 0 68 -28t28 -68v-1216q0 -40 -28 -68t-68 -28h-960q-40 0 -68 28t-28 68v288h-544q-40 0 -68 28t-28 68v672q0 40 20 88t48 76l408 408q28 28 76 48t88 20h416q40 0 68 -28t28 -68v-328q68 40 128 40h416zM1152 939l-299 -299h299v299zM512 1323l-299 -299 h299v299zM708 676l316 316v416h-384v-416q0 -40 -28 -68t-68 -28h-416v-640h512v256q0 40 20 88t48 76zM1664 -128v1152h-384v-416q0 -40 -28 -68t-68 -28h-416v-640h896z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M1404 151q0 -117 -79 -196t-196 -79q-135 0 -235 100l-777 776q-113 115 -113 271q0 159 110 270t269 111q158 0 273 -113l605 -606q10 -10 10 -22q0 -16 -30.5 -46.5t-46.5 -30.5q-13 0 -23 10l-606 607q-79 77 -181 77q-106 0 -179 -75t-73 -181q0 -105 76 -181 l776 -777q63 -63 145 -63q64 0 106 42t42 106q0 82 -63 145l-581 581q-26 24 -60 24q-29 0 -48 -19t-19 -48q0 -32 25 -59l410 -410q10 -10 10 -22q0 -16 -31 -47t-47 -31q-12 0 -22 10l-410 410q-63 61 -63 149q0 82 57 139t139 57q88 0 149 -63l581 -581q100 -98 100 -235 z" />
|
||||
<glyph unicode="" d="M384 0h768v384h-768v-384zM1280 0h128v896q0 14 -10 38.5t-20 34.5l-281 281q-10 10 -34 20t-39 10v-416q0 -40 -28 -68t-68 -28h-576q-40 0 -68 28t-28 68v416h-128v-1280h128v416q0 40 28 68t68 28h832q40 0 68 -28t28 -68v-416zM896 928v320q0 13 -9.5 22.5t-22.5 9.5 h-192q-13 0 -22.5 -9.5t-9.5 -22.5v-320q0 -13 9.5 -22.5t22.5 -9.5h192q13 0 22.5 9.5t9.5 22.5zM1536 896v-928q0 -40 -28 -68t-68 -28h-1344q-40 0 -68 28t-28 68v1344q0 40 28 68t68 28h928q40 0 88 -20t76 -48l280 -280q28 -28 48 -76t20 -88z" />
|
||||
<glyph unicode="" d="M1536 1120v-960q0 -119 -84.5 -203.5t-203.5 -84.5h-960q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" d="M1536 192v-128q0 -26 -19 -45t-45 -19h-1408q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h1408q26 0 45 -19t19 -45zM1536 704v-128q0 -26 -19 -45t-45 -19h-1408q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h1408q26 0 45 -19t19 -45zM1536 1216v-128q0 -26 -19 -45 t-45 -19h-1408q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h1408q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M384 128q0 -80 -56 -136t-136 -56t-136 56t-56 136t56 136t136 56t136 -56t56 -136zM384 640q0 -80 -56 -136t-136 -56t-136 56t-56 136t56 136t136 56t136 -56t56 -136zM1792 224v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-1216q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5 t22.5 9.5h1216q13 0 22.5 -9.5t9.5 -22.5zM384 1152q0 -80 -56 -136t-136 -56t-136 56t-56 136t56 136t136 56t136 -56t56 -136zM1792 736v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-1216q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5t22.5 9.5h1216q13 0 22.5 -9.5t9.5 -22.5z M1792 1248v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-1216q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5t22.5 9.5h1216q13 0 22.5 -9.5t9.5 -22.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M381 -84q0 -80 -54.5 -126t-135.5 -46q-106 0 -172 66l57 88q49 -45 106 -45q29 0 50.5 14.5t21.5 42.5q0 64 -105 56l-26 56q8 10 32.5 43.5t42.5 54t37 38.5v1q-16 0 -48.5 -1t-48.5 -1v-53h-106v152h333v-88l-95 -115q51 -12 81 -49t30 -88zM383 543v-159h-362 q-6 36 -6 54q0 51 23.5 93t56.5 68t66 47.5t56.5 43.5t23.5 45q0 25 -14.5 38.5t-39.5 13.5q-46 0 -81 -58l-85 59q24 51 71.5 79.5t105.5 28.5q73 0 123 -41.5t50 -112.5q0 -50 -34 -91.5t-75 -64.5t-75.5 -50.5t-35.5 -52.5h127v60h105zM1792 224v-192q0 -13 -9.5 -22.5 t-22.5 -9.5h-1216q-13 0 -22.5 9.5t-9.5 22.5v192q0 14 9 23t23 9h1216q13 0 22.5 -9.5t9.5 -22.5zM384 1123v-99h-335v99h107q0 41 0.5 122t0.5 121v12h-2q-8 -17 -50 -54l-71 76l136 127h106v-404h108zM1792 736v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-1216q-13 0 -22.5 9.5 t-9.5 22.5v192q0 14 9 23t23 9h1216q13 0 22.5 -9.5t9.5 -22.5zM1792 1248v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-1216q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5t22.5 9.5h1216q13 0 22.5 -9.5t9.5 -22.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1760 640q14 0 23 -9t9 -23v-64q0 -14 -9 -23t-23 -9h-1728q-14 0 -23 9t-9 23v64q0 14 9 23t23 9h1728zM483 704q-28 35 -51 80q-48 97 -48 188q0 181 134 309q133 127 393 127q50 0 167 -19q66 -12 177 -48q10 -38 21 -118q14 -123 14 -183q0 -18 -5 -45l-12 -3l-84 6 l-14 2q-50 149 -103 205q-88 91 -210 91q-114 0 -182 -59q-67 -58 -67 -146q0 -73 66 -140t279 -129q69 -20 173 -66q58 -28 95 -52h-743zM990 448h411q7 -39 7 -92q0 -111 -41 -212q-23 -55 -71 -104q-37 -35 -109 -81q-80 -48 -153 -66q-80 -21 -203 -21q-114 0 -195 23 l-140 40q-57 16 -72 28q-8 8 -8 22v13q0 108 -2 156q-1 30 0 68l2 37v44l102 2q15 -34 30 -71t22.5 -56t12.5 -27q35 -57 80 -94q43 -36 105 -57q59 -22 132 -22q64 0 139 27q77 26 122 86q47 61 47 129q0 84 -81 157q-34 29 -137 71z" />
|
||||
<glyph unicode="" d="M48 1313q-37 2 -45 4l-3 88q13 1 40 1q60 0 112 -4q132 -7 166 -7q86 0 168 3q116 4 146 5q56 0 86 2l-1 -14l2 -64v-9q-60 -9 -124 -9q-60 0 -79 -25q-13 -14 -13 -132q0 -13 0.5 -32.5t0.5 -25.5l1 -229l14 -280q6 -124 51 -202q35 -59 96 -92q88 -47 177 -47 q104 0 191 28q56 18 99 51q48 36 65 64q36 56 53 114q21 73 21 229q0 79 -3.5 128t-11 122.5t-13.5 159.5l-4 59q-5 67 -24 88q-34 35 -77 34l-100 -2l-14 3l2 86h84l205 -10q76 -3 196 10l18 -2q6 -38 6 -51q0 -7 -4 -31q-45 -12 -84 -13q-73 -11 -79 -17q-15 -15 -15 -41 q0 -7 1.5 -27t1.5 -31q8 -19 22 -396q6 -195 -15 -304q-15 -76 -41 -122q-38 -65 -112 -123q-75 -57 -182 -89q-109 -33 -255 -33q-167 0 -284 46q-119 47 -179 122q-61 76 -83 195q-16 80 -16 237v333q0 188 -17 213q-25 36 -147 39zM1536 -96v64q0 14 -9 23t-23 9h-1472 q-14 0 -23 -9t-9 -23v-64q0 -14 9 -23t23 -9h1472q14 0 23 9t9 23z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M512 160v192q0 14 -9 23t-23 9h-320q-14 0 -23 -9t-9 -23v-192q0 -14 9 -23t23 -9h320q14 0 23 9t9 23zM512 544v192q0 14 -9 23t-23 9h-320q-14 0 -23 -9t-9 -23v-192q0 -14 9 -23t23 -9h320q14 0 23 9t9 23zM1024 160v192q0 14 -9 23t-23 9h-320q-14 0 -23 -9t-9 -23 v-192q0 -14 9 -23t23 -9h320q14 0 23 9t9 23zM512 928v192q0 14 -9 23t-23 9h-320q-14 0 -23 -9t-9 -23v-192q0 -14 9 -23t23 -9h320q14 0 23 9t9 23zM1024 544v192q0 14 -9 23t-23 9h-320q-14 0 -23 -9t-9 -23v-192q0 -14 9 -23t23 -9h320q14 0 23 9t9 23zM1536 160v192 q0 14 -9 23t-23 9h-320q-14 0 -23 -9t-9 -23v-192q0 -14 9 -23t23 -9h320q14 0 23 9t9 23zM1024 928v192q0 14 -9 23t-23 9h-320q-14 0 -23 -9t-9 -23v-192q0 -14 9 -23t23 -9h320q14 0 23 9t9 23zM1536 544v192q0 14 -9 23t-23 9h-320q-14 0 -23 -9t-9 -23v-192 q0 -14 9 -23t23 -9h320q14 0 23 9t9 23zM1536 928v192q0 14 -9 23t-23 9h-320q-14 0 -23 -9t-9 -23v-192q0 -14 9 -23t23 -9h320q14 0 23 9t9 23zM1664 1248v-1088q0 -66 -47 -113t-113 -47h-1344q-66 0 -113 47t-47 113v1088q0 66 47 113t113 47h1344q66 0 113 -47t47 -113 z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1190 955l293 293l-107 107l-293 -293zM1637 1248q0 -27 -18 -45l-1286 -1286q-18 -18 -45 -18t-45 18l-198 198q-18 18 -18 45t18 45l1286 1286q18 18 45 18t45 -18l198 -198q18 -18 18 -45zM286 1438l98 -30l-98 -30l-30 -98l-30 98l-98 30l98 30l30 98zM636 1276 l196 -60l-196 -60l-60 -196l-60 196l-196 60l196 60l60 196zM1566 798l98 -30l-98 -30l-30 -98l-30 98l-98 30l98 30l30 98zM926 1438l98 -30l-98 -30l-30 -98l-30 98l-98 30l98 30l30 98z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M640 128q0 52 -38 90t-90 38t-90 -38t-38 -90t38 -90t90 -38t90 38t38 90zM256 640h384v256h-158q-13 0 -22 -9l-195 -195q-9 -9 -9 -22v-30zM1536 128q0 52 -38 90t-90 38t-90 -38t-38 -90t38 -90t90 -38t90 38t38 90zM1792 1216v-1024q0 -15 -4 -26.5t-13.5 -18.5 t-16.5 -11.5t-23.5 -6t-22.5 -2t-25.5 0t-22.5 0.5q0 -106 -75 -181t-181 -75t-181 75t-75 181h-384q0 -106 -75 -181t-181 -75t-181 75t-75 181h-64q-3 0 -22.5 -0.5t-25.5 0t-22.5 2t-23.5 6t-16.5 11.5t-13.5 18.5t-4 26.5q0 26 19 45t45 19v320q0 8 -0.5 35t0 38 t2.5 34.5t6.5 37t14 30.5t22.5 30l198 198q19 19 50.5 32t58.5 13h160v192q0 26 19 45t45 19h1024q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" d="M1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103q-111 0 -218 32q59 93 78 164q9 34 54 211q20 -39 73 -67.5t114 -28.5q121 0 216 68.5t147 188.5t52 270q0 114 -59.5 214t-172.5 163t-255 63q-105 0 -196 -29t-154.5 -77t-109 -110.5t-67 -129.5t-21.5 -134 q0 -104 40 -183t117 -111q30 -12 38 20q2 7 8 31t8 30q6 23 -11 43q-51 61 -51 151q0 151 104.5 259.5t273.5 108.5q151 0 235.5 -82t84.5 -213q0 -170 -68.5 -289t-175.5 -119q-61 0 -98 43.5t-23 104.5q8 35 26.5 93.5t30 103t11.5 75.5q0 50 -27 83t-77 33 q-62 0 -105 -57t-43 -142q0 -73 25 -122l-99 -418q-17 -70 -13 -177q-206 91 -333 281t-127 423q0 209 103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M1248 1408q119 0 203.5 -84.5t84.5 -203.5v-960q0 -119 -84.5 -203.5t-203.5 -84.5h-725q85 122 108 210q9 34 53 209q21 -39 73.5 -67t112.5 -28q181 0 295.5 147.5t114.5 373.5q0 84 -35 162.5t-96.5 139t-152.5 97t-197 36.5q-104 0 -194.5 -28.5t-153 -76.5 t-107.5 -109.5t-66.5 -128t-21.5 -132.5q0 -102 39.5 -180t116.5 -110q13 -5 23.5 0t14.5 19q10 44 15 61q6 23 -11 42q-50 62 -50 150q0 150 103.5 256.5t270.5 106.5q149 0 232.5 -81t83.5 -210q0 -168 -67.5 -286t-173.5 -118q-60 0 -97 43.5t-23 103.5q8 34 26.5 92.5 t29.5 102t11 74.5q0 49 -26.5 81.5t-75.5 32.5q-61 0 -103.5 -56.5t-42.5 -139.5q0 -72 24 -121l-98 -414q-24 -100 -7 -254h-183q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960z" />
|
||||
<glyph unicode="" d="M678 -57q0 -38 -10 -71h-380q-95 0 -171.5 56.5t-103.5 147.5q24 45 69 77.5t100 49.5t107 24t107 7q32 0 49 -2q6 -4 30.5 -21t33 -23t31 -23t32 -25.5t27.5 -25.5t26.5 -29.5t21 -30.5t17.5 -34.5t9.5 -36t4.5 -40.5zM385 294q-234 -7 -385 -85v433q103 -118 273 -118 q32 0 70 5q-21 -61 -21 -86q0 -67 63 -149zM558 805q0 -100 -43.5 -160.5t-140.5 -60.5q-51 0 -97 26t-78 67.5t-56 93.5t-35.5 104t-11.5 99q0 96 51.5 165t144.5 69q66 0 119 -41t84 -104t47 -130t16 -128zM1536 896v-736q0 -119 -84.5 -203.5t-203.5 -84.5h-468 q39 73 39 157q0 66 -22 122.5t-55.5 93t-72 71t-72 59.5t-55.5 54.5t-22 59.5q0 36 23 68t56 61.5t65.5 64.5t55.5 93t23 131t-26.5 145.5t-75.5 118.5q-6 6 -14 11t-12.5 7.5t-10 9.5t-10.5 17h135l135 64h-437q-138 0 -244.5 -38.5t-182.5 -133.5q0 126 81 213t207 87h960 q119 0 203.5 -84.5t84.5 -203.5v-96h-256v256h-128v-256h-256v-128h256v-256h128v256h256z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M876 71q0 21 -4.5 40.5t-9.5 36t-17.5 34.5t-21 30.5t-26.5 29.5t-27.5 25.5t-32 25.5t-31 23t-33 23t-30.5 21q-17 2 -50 2q-54 0 -106 -7t-108 -25t-98 -46t-69 -75t-27 -107q0 -68 35.5 -121.5t93 -84t120.5 -45.5t127 -15q59 0 112.5 12.5t100.5 39t74.5 73.5 t27.5 110zM756 933q0 60 -16.5 127.5t-47 130.5t-84 104t-119.5 41q-93 0 -144 -69t-51 -165q0 -47 11.5 -99t35.5 -104t56 -93.5t78 -67.5t97 -26q97 0 140.5 60.5t43.5 160.5zM625 1408h437l-135 -79h-135q71 -45 110 -126t39 -169q0 -74 -23 -131.5t-56 -92.5t-66 -64.5 t-56 -61t-23 -67.5q0 -26 16.5 -51t43 -48t58.5 -48t64 -55.5t58.5 -66t43 -85t16.5 -106.5q0 -160 -140 -282q-152 -131 -420 -131q-59 0 -119.5 10t-122 33.5t-108.5 58t-77 89t-30 121.5q0 61 37 135q32 64 96 110.5t145 71t155 36t150 13.5q-64 83 -64 149q0 12 2 23.5 t5 19.5t8 21.5t7 21.5q-40 -5 -70 -5q-149 0 -255.5 98t-106.5 246q0 140 95 250.5t234 141.5q94 20 187 20zM1664 1152v-128h-256v-256h-128v256h-256v128h256v256h128v-256h256z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M768 384h384v96h-128v448h-114l-148 -137l77 -80q42 37 55 57h2v-288h-128v-96zM1280 640q0 -70 -21 -142t-59.5 -134t-101.5 -101t-138 -39t-138 39t-101.5 101t-59.5 134t-21 142t21 142t59.5 134t101.5 101t138 39t138 -39t101.5 -101t59.5 -134t21 -142zM1792 384 v512q-106 0 -181 75t-75 181h-1152q0 -106 -75 -181t-181 -75v-512q106 0 181 -75t75 -181h1152q0 106 75 181t181 75zM1920 1216v-1152q0 -26 -19 -45t-45 -19h-1792q-26 0 -45 19t-19 45v1152q0 26 19 45t45 19h1792q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M1024 832q0 -26 -19 -45l-448 -448q-19 -19 -45 -19t-45 19l-448 448q-19 19 -19 45t19 45t45 19h896q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M1024 320q0 -26 -19 -45t-45 -19h-896q-26 0 -45 19t-19 45t19 45l448 448q19 19 45 19t45 -19l448 -448q19 -19 19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="640" d="M640 1088v-896q0 -26 -19 -45t-45 -19t-45 19l-448 448q-19 19 -19 45t19 45l448 448q19 19 45 19t45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="640" d="M576 640q0 -26 -19 -45l-448 -448q-19 -19 -45 -19t-45 19t-19 45v896q0 26 19 45t45 19t45 -19l448 -448q19 -19 19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M160 0h608v1152h-640v-1120q0 -13 9.5 -22.5t22.5 -9.5zM1536 32v1120h-640v-1152h608q13 0 22.5 9.5t9.5 22.5zM1664 1248v-1216q0 -66 -47 -113t-113 -47h-1344q-66 0 -113 47t-47 113v1216q0 66 47 113t113 47h1344q66 0 113 -47t47 -113z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M1024 448q0 -26 -19 -45l-448 -448q-19 -19 -45 -19t-45 19l-448 448q-19 19 -19 45t19 45t45 19h896q26 0 45 -19t19 -45zM1024 832q0 -26 -19 -45t-45 -19h-896q-26 0 -45 19t-19 45t19 45l448 448q19 19 45 19t45 -19l448 -448q19 -19 19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M1024 448q0 -26 -19 -45l-448 -448q-19 -19 -45 -19t-45 19l-448 448q-19 19 -19 45t19 45t45 19h896q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M1024 832q0 -26 -19 -45t-45 -19h-896q-26 0 -45 19t-19 45t19 45l448 448q19 19 45 19t45 -19l448 -448q19 -19 19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1792 826v-794q0 -66 -47 -113t-113 -47h-1472q-66 0 -113 47t-47 113v794q44 -49 101 -87q362 -246 497 -345q57 -42 92.5 -65.5t94.5 -48t110 -24.5h1h1q51 0 110 24.5t94.5 48t92.5 65.5q170 123 498 345q57 39 100 87zM1792 1120q0 -79 -49 -151t-122 -123 q-376 -261 -468 -325q-10 -7 -42.5 -30.5t-54 -38t-52 -32.5t-57.5 -27t-50 -9h-1h-1q-23 0 -50 9t-57.5 27t-52 32.5t-54 38t-42.5 30.5q-91 64 -262 182.5t-205 142.5q-62 42 -117 115.5t-55 136.5q0 78 41.5 130t118.5 52h1472q65 0 112.5 -47t47.5 -113z" />
|
||||
<glyph unicode="" d="M349 911v-991h-330v991h330zM370 1217q1 -73 -50.5 -122t-135.5 -49h-2q-82 0 -132 49t-50 122q0 74 51.5 122.5t134.5 48.5t133 -48.5t51 -122.5zM1536 488v-568h-329v530q0 105 -40.5 164.5t-126.5 59.5q-63 0 -105.5 -34.5t-63.5 -85.5q-11 -30 -11 -81v-553h-329 q2 399 2 647t-1 296l-1 48h329v-144h-2q20 32 41 56t56.5 52t87 43.5t114.5 15.5q171 0 275 -113.5t104 -332.5z" />
|
||||
<glyph unicode="" d="M1536 640q0 -156 -61 -298t-164 -245t-245 -164t-298 -61q-172 0 -327 72.5t-264 204.5q-7 10 -6.5 22.5t8.5 20.5l137 138q10 9 25 9q16 -2 23 -12q73 -95 179 -147t225 -52q104 0 198.5 40.5t163.5 109.5t109.5 163.5t40.5 198.5t-40.5 198.5t-109.5 163.5 t-163.5 109.5t-198.5 40.5q-98 0 -188 -35.5t-160 -101.5l137 -138q31 -30 14 -69q-17 -40 -59 -40h-448q-26 0 -45 19t-19 45v448q0 42 40 59q39 17 69 -14l130 -129q107 101 244.5 156.5t284.5 55.5q156 0 298 -61t245 -164t164 -245t61 -298z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1771 0q0 -53 -37 -90l-107 -108q-39 -37 -91 -37q-53 0 -90 37l-363 364q-38 36 -38 90q0 53 43 96l-256 256l-126 -126q-14 -14 -34 -14t-34 14q2 -2 12.5 -12t12.5 -13t10 -11.5t10 -13.5t6 -13.5t5.5 -16.5t1.5 -18q0 -38 -28 -68q-3 -3 -16.5 -18t-19 -20.5 t-18.5 -16.5t-22 -15.5t-22 -9t-26 -4.5q-40 0 -68 28l-408 408q-28 28 -28 68q0 13 4.5 26t9 22t15.5 22t16.5 18.5t20.5 19t18 16.5q30 28 68 28q10 0 18 -1.5t16.5 -5.5t13.5 -6t13.5 -10t11.5 -10t13 -12.5t12 -12.5q-14 14 -14 34t14 34l348 348q14 14 34 14t34 -14 q-2 2 -12.5 12t-12.5 13t-10 11.5t-10 13.5t-6 13.5t-5.5 16.5t-1.5 18q0 38 28 68q3 3 16.5 18t19 20.5t18.5 16.5t22 15.5t22 9t26 4.5q40 0 68 -28l408 -408q28 -28 28 -68q0 -13 -4.5 -26t-9 -22t-15.5 -22t-16.5 -18.5t-20.5 -19t-18 -16.5q-30 -28 -68 -28 q-10 0 -18 1.5t-16.5 5.5t-13.5 6t-13.5 10t-11.5 10t-13 12.5t-12 12.5q14 -14 14 -34t-14 -34l-126 -126l256 -256q43 43 96 43q52 0 91 -37l363 -363q37 -39 37 -91z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M384 384q0 53 -37.5 90.5t-90.5 37.5t-90.5 -37.5t-37.5 -90.5t37.5 -90.5t90.5 -37.5t90.5 37.5t37.5 90.5zM576 832q0 53 -37.5 90.5t-90.5 37.5t-90.5 -37.5t-37.5 -90.5t37.5 -90.5t90.5 -37.5t90.5 37.5t37.5 90.5zM1004 351l101 382q6 26 -7.5 48.5t-38.5 29.5 t-48 -6.5t-30 -39.5l-101 -382q-60 -5 -107 -43.5t-63 -98.5q-20 -77 20 -146t117 -89t146 20t89 117q16 60 -6 117t-72 91zM1664 384q0 53 -37.5 90.5t-90.5 37.5t-90.5 -37.5t-37.5 -90.5t37.5 -90.5t90.5 -37.5t90.5 37.5t37.5 90.5zM1024 1024q0 53 -37.5 90.5 t-90.5 37.5t-90.5 -37.5t-37.5 -90.5t37.5 -90.5t90.5 -37.5t90.5 37.5t37.5 90.5zM1472 832q0 53 -37.5 90.5t-90.5 37.5t-90.5 -37.5t-37.5 -90.5t37.5 -90.5t90.5 -37.5t90.5 37.5t37.5 90.5zM1792 384q0 -261 -141 -483q-19 -29 -54 -29h-1402q-35 0 -54 29 q-141 221 -141 483q0 182 71 348t191 286t286 191t348 71t348 -71t286 -191t191 -286t71 -348z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M896 1152q-204 0 -381.5 -69.5t-282 -187.5t-104.5 -255q0 -112 71.5 -213.5t201.5 -175.5l87 -50l-27 -96q-24 -91 -70 -172q152 63 275 171l43 38l57 -6q69 -8 130 -8q204 0 381.5 69.5t282 187.5t104.5 255t-104.5 255t-282 187.5t-381.5 69.5zM1792 640 q0 -174 -120 -321.5t-326 -233t-450 -85.5q-70 0 -145 8q-198 -175 -460 -242q-49 -14 -114 -22h-5q-15 0 -27 10.5t-16 27.5v1q-3 4 -0.5 12t2 10t4.5 9.5l6 9t7 8.5t8 9q7 8 31 34.5t34.5 38t31 39.5t32.5 51t27 59t26 76q-157 89 -247.5 220t-90.5 281q0 174 120 321.5 t326 233t450 85.5t450 -85.5t326 -233t120 -321.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M704 1152q-153 0 -286 -52t-211.5 -141t-78.5 -191q0 -82 53 -158t149 -132l97 -56l-35 -84q34 20 62 39l44 31l53 -10q78 -14 153 -14q153 0 286 52t211.5 141t78.5 191t-78.5 191t-211.5 141t-286 52zM704 1280q191 0 353.5 -68.5t256.5 -186.5t94 -257t-94 -257 t-256.5 -186.5t-353.5 -68.5q-86 0 -176 16q-124 -88 -278 -128q-36 -9 -86 -16h-3q-11 0 -20.5 8t-11.5 21q-1 3 -1 6.5t0.5 6.5t2 6l2.5 5t3.5 5.5t4 5t4.5 5t4 4.5q5 6 23 25t26 29.5t22.5 29t25 38.5t20.5 44q-124 72 -195 177t-71 224q0 139 94 257t256.5 186.5 t353.5 68.5zM1526 111q10 -24 20.5 -44t25 -38.5t22.5 -29t26 -29.5t23 -25q1 -1 4 -4.5t4.5 -5t4 -5t3.5 -5.5l2.5 -5t2 -6t0.5 -6.5t-1 -6.5q-3 -14 -13 -22t-22 -7q-50 7 -86 16q-154 40 -278 128q-90 -16 -176 -16q-271 0 -472 132q58 -4 88 -4q161 0 309 45t264 129 q125 92 192 212t67 254q0 77 -23 152q129 -71 204 -178t75 -230q0 -120 -71 -224.5t-195 -176.5z" />
|
||||
<glyph unicode="" horiz-adv-x="896" d="M885 970q18 -20 7 -44l-540 -1157q-13 -25 -42 -25q-4 0 -14 2q-17 5 -25.5 19t-4.5 30l197 808l-406 -101q-4 -1 -12 -1q-18 0 -31 11q-18 15 -13 39l201 825q4 14 16 23t28 9h328q19 0 32 -12.5t13 -29.5q0 -8 -5 -18l-171 -463l396 98q8 2 12 2q19 0 34 -15z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1792 288v-320q0 -40 -28 -68t-68 -28h-320q-40 0 -68 28t-28 68v320q0 40 28 68t68 28h96v192h-512v-192h96q40 0 68 -28t28 -68v-320q0 -40 -28 -68t-68 -28h-320q-40 0 -68 28t-28 68v320q0 40 28 68t68 28h96v192h-512v-192h96q40 0 68 -28t28 -68v-320 q0 -40 -28 -68t-68 -28h-320q-40 0 -68 28t-28 68v320q0 40 28 68t68 28h96v192q0 52 38 90t90 38h512v192h-96q-40 0 -68 28t-28 68v320q0 40 28 68t68 28h320q40 0 68 -28t28 -68v-320q0 -40 -28 -68t-68 -28h-96v-192h512q52 0 90 -38t38 -90v-192h96q40 0 68 -28t28 -68 z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M896 708v-580q0 -104 -76 -180t-180 -76t-180 76t-76 180q0 26 19 45t45 19t45 -19t19 -45q0 -50 39 -89t89 -39t89 39t39 89v580q33 11 64 11t64 -11zM1664 681q0 -13 -9.5 -22.5t-22.5 -9.5q-11 0 -23 10q-49 46 -93 69t-102 23q-68 0 -128 -37t-103 -97 q-7 -10 -17.5 -28t-14.5 -24q-11 -17 -28 -17q-18 0 -29 17q-4 6 -14.5 24t-17.5 28q-43 60 -102.5 97t-127.5 37t-127.5 -37t-102.5 -97q-7 -10 -17.5 -28t-14.5 -24q-11 -17 -29 -17q-17 0 -28 17q-4 6 -14.5 24t-17.5 28q-43 60 -103 97t-128 37q-58 0 -102 -23t-93 -69 q-12 -10 -23 -10q-13 0 -22.5 9.5t-9.5 22.5q0 5 1 7q45 183 172.5 319.5t298 204.5t360.5 68q140 0 274.5 -40t246.5 -113.5t194.5 -187t115.5 -251.5q1 -2 1 -7zM896 1408v-98q-42 2 -64 2t-64 -2v98q0 26 19 45t45 19t45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M768 -128h896v640h-416q-40 0 -68 28t-28 68v416h-384v-1152zM1024 1312v64q0 13 -9.5 22.5t-22.5 9.5h-704q-13 0 -22.5 -9.5t-9.5 -22.5v-64q0 -13 9.5 -22.5t22.5 -9.5h704q13 0 22.5 9.5t9.5 22.5zM1280 640h299l-299 299v-299zM1792 512v-672q0 -40 -28 -68t-68 -28 h-960q-40 0 -68 28t-28 68v160h-544q-40 0 -68 28t-28 68v1344q0 40 28 68t68 28h1088q40 0 68 -28t28 -68v-328q21 -13 36 -28l408 -408q28 -28 48 -76t20 -88z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M736 960q0 -13 -9.5 -22.5t-22.5 -9.5t-22.5 9.5t-9.5 22.5q0 46 -54 71t-106 25q-13 0 -22.5 9.5t-9.5 22.5t9.5 22.5t22.5 9.5q50 0 99.5 -16t87 -54t37.5 -90zM896 960q0 72 -34.5 134t-90 101.5t-123 62t-136.5 22.5t-136.5 -22.5t-123 -62t-90 -101.5t-34.5 -134 q0 -101 68 -180q10 -11 30.5 -33t30.5 -33q128 -153 141 -298h228q13 145 141 298q10 11 30.5 33t30.5 33q68 79 68 180zM1024 960q0 -155 -103 -268q-45 -49 -74.5 -87t-59.5 -95.5t-34 -107.5q47 -28 47 -82q0 -37 -25 -64q25 -27 25 -64q0 -52 -45 -81q13 -23 13 -47 q0 -46 -31.5 -71t-77.5 -25q-20 -44 -60 -70t-87 -26t-87 26t-60 70q-46 0 -77.5 25t-31.5 71q0 24 13 47q-45 29 -45 81q0 37 25 64q-25 27 -25 64q0 54 47 82q-4 50 -34 107.5t-59.5 95.5t-74.5 87q-103 113 -103 268q0 99 44.5 184.5t117 142t164 89t186.5 32.5 t186.5 -32.5t164 -89t117 -142t44.5 -184.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1792 352v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-1376v-192q0 -13 -9.5 -22.5t-22.5 -9.5q-12 0 -24 10l-319 320q-9 9 -9 22q0 14 9 23l320 320q9 9 23 9q13 0 22.5 -9.5t9.5 -22.5v-192h1376q13 0 22.5 -9.5t9.5 -22.5zM1792 896q0 -14 -9 -23l-320 -320q-9 -9 -23 -9 q-13 0 -22.5 9.5t-9.5 22.5v192h-1376q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5t22.5 9.5h1376v192q0 14 9 23t23 9q12 0 24 -10l319 -319q9 -9 9 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M1280 608q0 14 -9 23t-23 9h-224v352q0 13 -9.5 22.5t-22.5 9.5h-192q-13 0 -22.5 -9.5t-9.5 -22.5v-352h-224q-13 0 -22.5 -9.5t-9.5 -22.5q0 -14 9 -23l352 -352q9 -9 23 -9t23 9l351 351q10 12 10 24zM1920 384q0 -159 -112.5 -271.5t-271.5 -112.5h-1088 q-185 0 -316.5 131.5t-131.5 316.5q0 130 70 240t188 165q-2 30 -2 43q0 212 150 362t362 150q156 0 285.5 -87t188.5 -231q71 62 166 62q106 0 181 -75t75 -181q0 -76 -41 -138q130 -31 213.5 -135.5t83.5 -238.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M1280 672q0 14 -9 23l-352 352q-9 9 -23 9t-23 -9l-351 -351q-10 -12 -10 -24q0 -14 9 -23t23 -9h224v-352q0 -13 9.5 -22.5t22.5 -9.5h192q13 0 22.5 9.5t9.5 22.5v352h224q13 0 22.5 9.5t9.5 22.5zM1920 384q0 -159 -112.5 -271.5t-271.5 -112.5h-1088 q-185 0 -316.5 131.5t-131.5 316.5q0 130 70 240t188 165q-2 30 -2 43q0 212 150 362t362 150q156 0 285.5 -87t188.5 -231q71 62 166 62q106 0 181 -75t75 -181q0 -76 -41 -138q130 -31 213.5 -135.5t83.5 -238.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M384 192q0 -26 -19 -45t-45 -19t-45 19t-19 45t19 45t45 19t45 -19t19 -45zM1408 131q0 -121 -73 -190t-194 -69h-874q-121 0 -194 69t-73 190q0 68 5.5 131t24 138t47.5 132.5t81 103t120 60.5q-22 -52 -22 -120v-203q-58 -20 -93 -70t-35 -111q0 -80 56 -136t136 -56 t136 56t56 136q0 61 -35.5 111t-92.5 70v203q0 62 25 93q132 -104 295 -104t295 104q25 -31 25 -93v-64q-106 0 -181 -75t-75 -181v-89q-32 -29 -32 -71q0 -40 28 -68t68 -28t68 28t28 68q0 42 -32 71v89q0 52 38 90t90 38t90 -38t38 -90v-89q-32 -29 -32 -71q0 -40 28 -68 t68 -28t68 28t28 68q0 42 -32 71v89q0 68 -34.5 127.5t-93.5 93.5q0 10 0.5 42.5t0 48t-2.5 41.5t-7 47t-13 40q68 -15 120 -60.5t81 -103t47.5 -132.5t24 -138t5.5 -131zM1088 1024q0 -159 -112.5 -271.5t-271.5 -112.5t-271.5 112.5t-112.5 271.5t112.5 271.5t271.5 112.5 t271.5 -112.5t112.5 -271.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M1280 832q0 26 -19 45t-45 19t-45 -19t-19 -45t19 -45t45 -19t45 19t19 45zM1408 832q0 -62 -35.5 -111t-92.5 -70v-395q0 -159 -131.5 -271.5t-316.5 -112.5t-316.5 112.5t-131.5 271.5v132q-164 20 -274 128t-110 252v512q0 26 19 45t45 19q6 0 16 -2q17 30 47 48 t65 18q53 0 90.5 -37.5t37.5 -90.5t-37.5 -90.5t-90.5 -37.5q-33 0 -64 18v-402q0 -106 94 -181t226 -75t226 75t94 181v402q-31 -18 -64 -18q-53 0 -90.5 37.5t-37.5 90.5t37.5 90.5t90.5 37.5q35 0 65 -18t47 -48q10 2 16 2q26 0 45 -19t19 -45v-512q0 -144 -110 -252 t-274 -128v-132q0 -106 94 -181t226 -75t226 75t94 181v395q-57 21 -92.5 70t-35.5 111q0 80 56 136t136 56t136 -56t56 -136z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M640 1152h512v128h-512v-128zM288 1152v-1280h-64q-92 0 -158 66t-66 158v832q0 92 66 158t158 66h64zM1408 1152v-1280h-1024v1280h128v160q0 40 28 68t68 28h576q40 0 68 -28t28 -68v-160h128zM1792 928v-832q0 -92 -66 -158t-158 -66h-64v1280h64q92 0 158 -66 t66 -158z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M848 -160q0 16 -16 16q-59 0 -101.5 42.5t-42.5 101.5q0 16 -16 16t-16 -16q0 -73 51.5 -124.5t124.5 -51.5q16 0 16 16zM1664 128q0 -52 -38 -90t-90 -38h-448q0 -106 -75 -181t-181 -75t-181 75t-75 181h-448q-52 0 -90 38t-38 90q190 161 287 397.5t97 498.5 q0 165 96 262t264 117q-8 18 -8 37q0 40 28 68t68 28t68 -28t28 -68q0 -19 -8 -37q168 -20 264 -117t96 -262q0 -262 97 -498.5t287 -397.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M1664 896q0 80 -56 136t-136 56h-64v-384h64q80 0 136 56t56 136zM0 128h1792q0 -106 -75 -181t-181 -75h-1280q-106 0 -181 75t-75 181zM1856 896q0 -159 -112.5 -271.5t-271.5 -112.5h-64v-32q0 -92 -66 -158t-158 -66h-704q-92 0 -158 66t-66 158v736q0 26 19 45 t45 19h1152q159 0 271.5 -112.5t112.5 -271.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M640 1472v-640q0 -61 -35.5 -111t-92.5 -70v-779q0 -52 -38 -90t-90 -38h-128q-52 0 -90 38t-38 90v779q-57 20 -92.5 70t-35.5 111v640q0 26 19 45t45 19t45 -19t19 -45v-416q0 -26 19 -45t45 -19t45 19t19 45v416q0 26 19 45t45 19t45 -19t19 -45v-416q0 -26 19 -45 t45 -19t45 19t19 45v416q0 26 19 45t45 19t45 -19t19 -45zM1408 1472v-1600q0 -52 -38 -90t-90 -38h-128q-52 0 -90 38t-38 90v512h-224q-13 0 -22.5 9.5t-9.5 22.5v800q0 132 94 226t226 94h256q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1280" d="M1024 352v-64q0 -14 -9 -23t-23 -9h-704q-14 0 -23 9t-9 23v64q0 14 9 23t23 9h704q14 0 23 -9t9 -23zM1024 608v-64q0 -14 -9 -23t-23 -9h-704q-14 0 -23 9t-9 23v64q0 14 9 23t23 9h704q14 0 23 -9t9 -23zM128 0h1024v768h-416q-40 0 -68 28t-28 68v416h-512v-1280z M768 896h376q-10 29 -22 41l-313 313q-12 12 -41 22v-376zM1280 864v-896q0 -40 -28 -68t-68 -28h-1088q-40 0 -68 28t-28 68v1344q0 40 28 68t68 28h640q40 0 88 -20t76 -48l312 -312q28 -28 48 -76t20 -88z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M384 224v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5zM384 480v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5z M640 480v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5zM384 736v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5z M1152 224v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5zM896 480v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5z M640 736v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5zM384 992v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5z M1152 480v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5zM896 736v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5z M640 992v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5zM384 1248v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5z M1152 736v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5zM896 992v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5z M640 1248v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5zM1152 992v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5z M896 1248v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5zM1152 1248v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5z M896 -128h384v1536h-1152v-1536h384v224q0 13 9.5 22.5t22.5 9.5h320q13 0 22.5 -9.5t9.5 -22.5v-224zM1408 1472v-1664q0 -26 -19 -45t-45 -19h-1280q-26 0 -45 19t-19 45v1664q0 26 19 45t45 19h1280q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M384 224v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5zM384 480v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5z M640 480v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5zM384 736v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5z M1152 224v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5zM896 480v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5z M640 736v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5zM1152 480v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5z M896 736v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5zM1152 736v-64q0 -13 -9.5 -22.5t-22.5 -9.5h-64q-13 0 -22.5 9.5t-9.5 22.5v64q0 13 9.5 22.5t22.5 9.5h64q13 0 22.5 -9.5t9.5 -22.5z M896 -128h384v1152h-256v-32q0 -40 -28 -68t-68 -28h-448q-40 0 -68 28t-28 68v32h-256v-1152h384v224q0 13 9.5 22.5t22.5 9.5h320q13 0 22.5 -9.5t9.5 -22.5v-224zM896 1056v320q0 13 -9.5 22.5t-22.5 9.5h-64q-13 0 -22.5 -9.5t-9.5 -22.5v-96h-128v96q0 13 -9.5 22.5 t-22.5 9.5h-64q-13 0 -22.5 -9.5t-9.5 -22.5v-320q0 -13 9.5 -22.5t22.5 -9.5h64q13 0 22.5 9.5t9.5 22.5v96h128v-96q0 -13 9.5 -22.5t22.5 -9.5h64q13 0 22.5 9.5t9.5 22.5zM1408 1088v-1280q0 -26 -19 -45t-45 -19h-1280q-26 0 -45 19t-19 45v1280q0 26 19 45t45 19h320 v288q0 40 28 68t68 28h448q40 0 68 -28t28 -68v-288h320q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M640 128q0 53 -37.5 90.5t-90.5 37.5t-90.5 -37.5t-37.5 -90.5t37.5 -90.5t90.5 -37.5t90.5 37.5t37.5 90.5zM256 640h384v256h-158q-14 -2 -22 -9l-195 -195q-7 -12 -9 -22v-30zM1536 128q0 53 -37.5 90.5t-90.5 37.5t-90.5 -37.5t-37.5 -90.5t37.5 -90.5t90.5 -37.5 t90.5 37.5t37.5 90.5zM1664 800v192q0 14 -9 23t-23 9h-224v224q0 14 -9 23t-23 9h-192q-14 0 -23 -9t-9 -23v-224h-224q-14 0 -23 -9t-9 -23v-192q0 -14 9 -23t23 -9h224v-224q0 -14 9 -23t23 -9h192q14 0 23 9t9 23v224h224q14 0 23 9t9 23zM1920 1344v-1152 q0 -26 -19 -45t-45 -19h-192q0 -106 -75 -181t-181 -75t-181 75t-75 181h-384q0 -106 -75 -181t-181 -75t-181 75t-75 181h-128q-26 0 -45 19t-19 45t19 45t45 19v416q0 26 13 58t32 51l198 198q19 19 51 32t58 13h160v320q0 26 19 45t45 19h1152q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1280 416v192q0 14 -9 23t-23 9h-224v224q0 14 -9 23t-23 9h-192q-14 0 -23 -9t-9 -23v-224h-224q-14 0 -23 -9t-9 -23v-192q0 -14 9 -23t23 -9h224v-224q0 -14 9 -23t23 -9h192q14 0 23 9t9 23v224h224q14 0 23 9t9 23zM640 1152h512v128h-512v-128zM256 1152v-1280h-32 q-92 0 -158 66t-66 158v832q0 92 66 158t158 66h32zM1440 1152v-1280h-1088v1280h160v160q0 40 28 68t68 28h576q40 0 68 -28t28 -68v-160h160zM1792 928v-832q0 -92 -66 -158t-158 -66h-32v1280h32q92 0 158 -66t66 -158z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M1920 576q-1 -32 -288 -96l-352 -32l-224 -64h-64l-293 -352h69q26 0 45 -4.5t19 -11.5t-19 -11.5t-45 -4.5h-96h-160h-64v32h64v416h-160l-192 -224h-96l-32 32v192h32v32h128v8l-192 24v128l192 24v8h-128v32h-32v192l32 32h96l192 -224h160v416h-64v32h64h160h96 q26 0 45 -4.5t19 -11.5t-19 -11.5t-45 -4.5h-69l293 -352h64l224 -64l352 -32q261 -58 287 -93z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M640 640v384h-256v-256q0 -53 37.5 -90.5t90.5 -37.5h128zM1664 192v-192h-1152v192l128 192h-128q-159 0 -271.5 112.5t-112.5 271.5v320l-64 64l32 128h480l32 128h960l32 -192l-64 -32v-800z" />
|
||||
<glyph unicode="" d="M1280 192v896q0 26 -19 45t-45 19h-128q-26 0 -45 -19t-19 -45v-320h-512v320q0 26 -19 45t-45 19h-128q-26 0 -45 -19t-19 -45v-896q0 -26 19 -45t45 -19h128q26 0 45 19t19 45v320h512v-320q0 -26 19 -45t45 -19h128q26 0 45 19t19 45zM1536 1120v-960 q0 -119 -84.5 -203.5t-203.5 -84.5h-960q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" d="M1280 576v128q0 26 -19 45t-45 19h-320v320q0 26 -19 45t-45 19h-128q-26 0 -45 -19t-19 -45v-320h-320q-26 0 -45 -19t-19 -45v-128q0 -26 19 -45t45 -19h320v-320q0 -26 19 -45t45 -19h128q26 0 45 19t19 45v320h320q26 0 45 19t19 45zM1536 1120v-960 q0 -119 -84.5 -203.5t-203.5 -84.5h-960q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M627 160q0 -13 -10 -23l-50 -50q-10 -10 -23 -10t-23 10l-466 466q-10 10 -10 23t10 23l466 466q10 10 23 10t23 -10l50 -50q10 -10 10 -23t-10 -23l-393 -393l393 -393q10 -10 10 -23zM1011 160q0 -13 -10 -23l-50 -50q-10 -10 -23 -10t-23 10l-466 466q-10 10 -10 23 t10 23l466 466q10 10 23 10t23 -10l50 -50q10 -10 10 -23t-10 -23l-393 -393l393 -393q10 -10 10 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M595 576q0 -13 -10 -23l-466 -466q-10 -10 -23 -10t-23 10l-50 50q-10 10 -10 23t10 23l393 393l-393 393q-10 10 -10 23t10 23l50 50q10 10 23 10t23 -10l466 -466q10 -10 10 -23zM979 576q0 -13 -10 -23l-466 -466q-10 -10 -23 -10t-23 10l-50 50q-10 10 -10 23t10 23 l393 393l-393 393q-10 10 -10 23t10 23l50 50q10 10 23 10t23 -10l466 -466q10 -10 10 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1152" d="M1075 224q0 -13 -10 -23l-50 -50q-10 -10 -23 -10t-23 10l-393 393l-393 -393q-10 -10 -23 -10t-23 10l-50 50q-10 10 -10 23t10 23l466 466q10 10 23 10t23 -10l466 -466q10 -10 10 -23zM1075 608q0 -13 -10 -23l-50 -50q-10 -10 -23 -10t-23 10l-393 393l-393 -393 q-10 -10 -23 -10t-23 10l-50 50q-10 10 -10 23t10 23l466 466q10 10 23 10t23 -10l466 -466q10 -10 10 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1152" d="M1075 672q0 -13 -10 -23l-466 -466q-10 -10 -23 -10t-23 10l-466 466q-10 10 -10 23t10 23l50 50q10 10 23 10t23 -10l393 -393l393 393q10 10 23 10t23 -10l50 -50q10 -10 10 -23zM1075 1056q0 -13 -10 -23l-466 -466q-10 -10 -23 -10t-23 10l-466 466q-10 10 -10 23 t10 23l50 50q10 10 23 10t23 -10l393 -393l393 393q10 10 23 10t23 -10l50 -50q10 -10 10 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="640" d="M627 992q0 -13 -10 -23l-393 -393l393 -393q10 -10 10 -23t-10 -23l-50 -50q-10 -10 -23 -10t-23 10l-466 466q-10 10 -10 23t10 23l466 466q10 10 23 10t23 -10l50 -50q10 -10 10 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="640" d="M595 576q0 -13 -10 -23l-466 -466q-10 -10 -23 -10t-23 10l-50 50q-10 10 -10 23t10 23l393 393l-393 393q-10 10 -10 23t10 23l50 50q10 10 23 10t23 -10l466 -466q10 -10 10 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1152" d="M1075 352q0 -13 -10 -23l-50 -50q-10 -10 -23 -10t-23 10l-393 393l-393 -393q-10 -10 -23 -10t-23 10l-50 50q-10 10 -10 23t10 23l466 466q10 10 23 10t23 -10l466 -466q10 -10 10 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1152" d="M1075 800q0 -13 -10 -23l-466 -466q-10 -10 -23 -10t-23 10l-466 466q-10 10 -10 23t10 23l50 50q10 10 23 10t23 -10l393 -393l393 393q10 10 23 10t23 -10l50 -50q10 -10 10 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M1792 544v832q0 13 -9.5 22.5t-22.5 9.5h-1600q-13 0 -22.5 -9.5t-9.5 -22.5v-832q0 -13 9.5 -22.5t22.5 -9.5h1600q13 0 22.5 9.5t9.5 22.5zM1920 1376v-1088q0 -66 -47 -113t-113 -47h-544q0 -37 16 -77.5t32 -71t16 -43.5q0 -26 -19 -45t-45 -19h-512q-26 0 -45 19 t-19 45q0 14 16 44t32 70t16 78h-544q-66 0 -113 47t-47 113v1088q0 66 47 113t113 47h1600q66 0 113 -47t47 -113z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M416 256q-66 0 -113 47t-47 113v704q0 66 47 113t113 47h1088q66 0 113 -47t47 -113v-704q0 -66 -47 -113t-113 -47h-1088zM384 1120v-704q0 -13 9.5 -22.5t22.5 -9.5h1088q13 0 22.5 9.5t9.5 22.5v704q0 13 -9.5 22.5t-22.5 9.5h-1088q-13 0 -22.5 -9.5t-9.5 -22.5z M1760 192h160v-96q0 -40 -47 -68t-113 -28h-1600q-66 0 -113 28t-47 68v96h160h1600zM1040 96q16 0 16 16t-16 16h-160q-16 0 -16 -16t16 -16h160z" />
|
||||
<glyph unicode="" horiz-adv-x="1152" d="M640 128q0 26 -19 45t-45 19t-45 -19t-19 -45t19 -45t45 -19t45 19t19 45zM1024 288v960q0 13 -9.5 22.5t-22.5 9.5h-832q-13 0 -22.5 -9.5t-9.5 -22.5v-960q0 -13 9.5 -22.5t22.5 -9.5h832q13 0 22.5 9.5t9.5 22.5zM1152 1248v-1088q0 -66 -47 -113t-113 -47h-832 q-66 0 -113 47t-47 113v1088q0 66 47 113t113 47h832q66 0 113 -47t47 -113z" />
|
||||
<glyph unicode="" horiz-adv-x="768" d="M464 128q0 33 -23.5 56.5t-56.5 23.5t-56.5 -23.5t-23.5 -56.5t23.5 -56.5t56.5 -23.5t56.5 23.5t23.5 56.5zM672 288v704q0 13 -9.5 22.5t-22.5 9.5h-512q-13 0 -22.5 -9.5t-9.5 -22.5v-704q0 -13 9.5 -22.5t22.5 -9.5h512q13 0 22.5 9.5t9.5 22.5zM480 1136 q0 16 -16 16h-160q-16 0 -16 -16t16 -16h160q16 0 16 16zM768 1152v-1024q0 -52 -38 -90t-90 -38h-512q-52 0 -90 38t-38 90v1024q0 52 38 90t90 38h512q52 0 90 -38t38 -90z" />
|
||||
<glyph unicode="" d="M768 1184q-148 0 -273 -73t-198 -198t-73 -273t73 -273t198 -198t273 -73t273 73t198 198t73 273t-73 273t-198 198t-273 73zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103 t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M768 576v-384q0 -80 -56 -136t-136 -56h-384q-80 0 -136 56t-56 136v704q0 104 40.5 198.5t109.5 163.5t163.5 109.5t198.5 40.5h64q26 0 45 -19t19 -45v-128q0 -26 -19 -45t-45 -19h-64q-106 0 -181 -75t-75 -181v-32q0 -40 28 -68t68 -28h224q80 0 136 -56t56 -136z M1664 576v-384q0 -80 -56 -136t-136 -56h-384q-80 0 -136 56t-56 136v704q0 104 40.5 198.5t109.5 163.5t163.5 109.5t198.5 40.5h64q26 0 45 -19t19 -45v-128q0 -26 -19 -45t-45 -19h-64q-106 0 -181 -75t-75 -181v-32q0 -40 28 -68t68 -28h224q80 0 136 -56t56 -136z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M768 1216v-704q0 -104 -40.5 -198.5t-109.5 -163.5t-163.5 -109.5t-198.5 -40.5h-64q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h64q106 0 181 75t75 181v32q0 40 -28 68t-68 28h-224q-80 0 -136 56t-56 136v384q0 80 56 136t136 56h384q80 0 136 -56t56 -136zM1664 1216 v-704q0 -104 -40.5 -198.5t-109.5 -163.5t-163.5 -109.5t-198.5 -40.5h-64q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h64q106 0 181 75t75 181v32q0 40 -28 68t-68 28h-224q-80 0 -136 56t-56 136v384q0 80 56 136t136 56h384q80 0 136 -56t56 -136z" />
|
||||
<glyph unicode="" horiz-adv-x="1568" d="M496 192q0 -60 -42.5 -102t-101.5 -42q-60 0 -102 42t-42 102t42 102t102 42q59 0 101.5 -42t42.5 -102zM928 0q0 -53 -37.5 -90.5t-90.5 -37.5t-90.5 37.5t-37.5 90.5t37.5 90.5t90.5 37.5t90.5 -37.5t37.5 -90.5zM320 640q0 -66 -47 -113t-113 -47t-113 47t-47 113 t47 113t113 47t113 -47t47 -113zM1360 192q0 -46 -33 -79t-79 -33t-79 33t-33 79t33 79t79 33t79 -33t33 -79zM528 1088q0 -73 -51.5 -124.5t-124.5 -51.5t-124.5 51.5t-51.5 124.5t51.5 124.5t124.5 51.5t124.5 -51.5t51.5 -124.5zM992 1280q0 -80 -56 -136t-136 -56 t-136 56t-56 136t56 136t136 56t136 -56t56 -136zM1536 640q0 -40 -28 -68t-68 -28t-68 28t-28 68t28 68t68 28t68 -28t28 -68zM1328 1088q0 -33 -23.5 -56.5t-56.5 -23.5t-56.5 23.5t-23.5 56.5t23.5 56.5t56.5 23.5t56.5 -23.5t23.5 -56.5z" />
|
||||
<glyph unicode="" d="M1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1792 416q0 -166 -127 -451q-3 -7 -10.5 -24t-13.5 -30t-13 -22q-12 -17 -28 -17q-15 0 -23.5 10t-8.5 25q0 9 2.5 26.5t2.5 23.5q5 68 5 123q0 101 -17.5 181t-48.5 138.5t-80 101t-105.5 69.5t-133 42.5t-154 21.5t-175.5 6h-224v-256q0 -26 -19 -45t-45 -19t-45 19 l-512 512q-19 19 -19 45t19 45l512 512q19 19 45 19t45 -19t19 -45v-256h224q713 0 875 -403q53 -134 53 -333z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M640 320q0 -40 -12.5 -82t-43 -76t-72.5 -34t-72.5 34t-43 76t-12.5 82t12.5 82t43 76t72.5 34t72.5 -34t43 -76t12.5 -82zM1280 320q0 -40 -12.5 -82t-43 -76t-72.5 -34t-72.5 34t-43 76t-12.5 82t12.5 82t43 76t72.5 34t72.5 -34t43 -76t12.5 -82zM1440 320 q0 120 -69 204t-187 84q-41 0 -195 -21q-71 -11 -157 -11t-157 11q-152 21 -195 21q-118 0 -187 -84t-69 -204q0 -88 32 -153.5t81 -103t122 -60t140 -29.5t149 -7h168q82 0 149 7t140 29.5t122 60t81 103t32 153.5zM1664 496q0 -207 -61 -331q-38 -77 -105.5 -133t-141 -86 t-170 -47.5t-171.5 -22t-167 -4.5q-78 0 -142 3t-147.5 12.5t-152.5 30t-137 51.5t-121 81t-86 115q-62 123 -62 331q0 237 136 396q-27 82 -27 170q0 116 51 218q108 0 190 -39.5t189 -123.5q147 35 309 35q148 0 280 -32q105 82 187 121t189 39q51 -102 51 -218 q0 -87 -27 -168q136 -160 136 -398z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1536 224v704q0 40 -28 68t-68 28h-704q-40 0 -68 28t-28 68v64q0 40 -28 68t-68 28h-320q-40 0 -68 -28t-28 -68v-960q0 -40 28 -68t68 -28h1216q40 0 68 28t28 68zM1664 928v-704q0 -92 -66 -158t-158 -66h-1216q-92 0 -158 66t-66 158v960q0 92 66 158t158 66h320 q92 0 158 -66t66 -158v-32h672q92 0 158 -66t66 -158z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M1781 605q0 35 -53 35h-1088q-40 0 -85.5 -21.5t-71.5 -52.5l-294 -363q-18 -24 -18 -40q0 -35 53 -35h1088q40 0 86 22t71 53l294 363q18 22 18 39zM640 768h768v160q0 40 -28 68t-68 28h-576q-40 0 -68 28t-28 68v64q0 40 -28 68t-68 28h-320q-40 0 -68 -28t-28 -68 v-853l256 315q44 53 116 87.5t140 34.5zM1909 605q0 -62 -46 -120l-295 -363q-43 -53 -116 -87.5t-140 -34.5h-1088q-92 0 -158 66t-66 158v960q0 92 66 158t158 66h320q92 0 158 -66t66 -158v-32h544q92 0 158 -66t66 -158v-160h192q54 0 99 -24.5t67 -70.5q15 -32 15 -68z " />
|
||||
<glyph unicode="" horiz-adv-x="1792" />
|
||||
<glyph unicode="" horiz-adv-x="1792" />
|
||||
<glyph unicode="" d="M1134 461q-37 -121 -138 -195t-228 -74t-228 74t-138 195q-8 25 4 48.5t38 31.5q25 8 48.5 -4t31.5 -38q25 -80 92.5 -129.5t151.5 -49.5t151.5 49.5t92.5 129.5q8 26 32 38t49 4t37 -31.5t4 -48.5zM640 896q0 -53 -37.5 -90.5t-90.5 -37.5t-90.5 37.5t-37.5 90.5 t37.5 90.5t90.5 37.5t90.5 -37.5t37.5 -90.5zM1152 896q0 -53 -37.5 -90.5t-90.5 -37.5t-90.5 37.5t-37.5 90.5t37.5 90.5t90.5 37.5t90.5 -37.5t37.5 -90.5zM1408 640q0 130 -51 248.5t-136.5 204t-204 136.5t-248.5 51t-248.5 -51t-204 -136.5t-136.5 -204t-51 -248.5 t51 -248.5t136.5 -204t204 -136.5t248.5 -51t248.5 51t204 136.5t136.5 204t51 248.5zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M1134 307q8 -25 -4 -48.5t-37 -31.5t-49 4t-32 38q-25 80 -92.5 129.5t-151.5 49.5t-151.5 -49.5t-92.5 -129.5q-8 -26 -31.5 -38t-48.5 -4q-26 8 -38 31.5t-4 48.5q37 121 138 195t228 74t228 -74t138 -195zM640 896q0 -53 -37.5 -90.5t-90.5 -37.5t-90.5 37.5 t-37.5 90.5t37.5 90.5t90.5 37.5t90.5 -37.5t37.5 -90.5zM1152 896q0 -53 -37.5 -90.5t-90.5 -37.5t-90.5 37.5t-37.5 90.5t37.5 90.5t90.5 37.5t90.5 -37.5t37.5 -90.5zM1408 640q0 130 -51 248.5t-136.5 204t-204 136.5t-248.5 51t-248.5 -51t-204 -136.5t-136.5 -204 t-51 -248.5t51 -248.5t136.5 -204t204 -136.5t248.5 -51t248.5 51t204 136.5t136.5 204t51 248.5zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M1152 448q0 -26 -19 -45t-45 -19h-640q-26 0 -45 19t-19 45t19 45t45 19h640q26 0 45 -19t19 -45zM640 896q0 -53 -37.5 -90.5t-90.5 -37.5t-90.5 37.5t-37.5 90.5t37.5 90.5t90.5 37.5t90.5 -37.5t37.5 -90.5zM1152 896q0 -53 -37.5 -90.5t-90.5 -37.5t-90.5 37.5 t-37.5 90.5t37.5 90.5t90.5 37.5t90.5 -37.5t37.5 -90.5zM1408 640q0 130 -51 248.5t-136.5 204t-204 136.5t-248.5 51t-248.5 -51t-204 -136.5t-136.5 -204t-51 -248.5t51 -248.5t136.5 -204t204 -136.5t248.5 -51t248.5 51t204 136.5t136.5 204t51 248.5zM1536 640 q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M832 448v128q0 14 -9 23t-23 9h-192v192q0 14 -9 23t-23 9h-128q-14 0 -23 -9t-9 -23v-192h-192q-14 0 -23 -9t-9 -23v-128q0 -14 9 -23t23 -9h192v-192q0 -14 9 -23t23 -9h128q14 0 23 9t9 23v192h192q14 0 23 9t9 23zM1408 384q0 53 -37.5 90.5t-90.5 37.5t-90.5 -37.5 t-37.5 -90.5t37.5 -90.5t90.5 -37.5t90.5 37.5t37.5 90.5zM1664 640q0 53 -37.5 90.5t-90.5 37.5t-90.5 -37.5t-37.5 -90.5t37.5 -90.5t90.5 -37.5t90.5 37.5t37.5 90.5zM1920 512q0 -212 -150 -362t-362 -150q-192 0 -338 128h-220q-146 -128 -338 -128q-212 0 -362 150 t-150 362t150 362t362 150h896q212 0 362 -150t150 -362z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M384 368v-96q0 -16 -16 -16h-96q-16 0 -16 16v96q0 16 16 16h96q16 0 16 -16zM512 624v-96q0 -16 -16 -16h-224q-16 0 -16 16v96q0 16 16 16h224q16 0 16 -16zM384 880v-96q0 -16 -16 -16h-96q-16 0 -16 16v96q0 16 16 16h96q16 0 16 -16zM1408 368v-96q0 -16 -16 -16 h-864q-16 0 -16 16v96q0 16 16 16h864q16 0 16 -16zM768 624v-96q0 -16 -16 -16h-96q-16 0 -16 16v96q0 16 16 16h96q16 0 16 -16zM640 880v-96q0 -16 -16 -16h-96q-16 0 -16 16v96q0 16 16 16h96q16 0 16 -16zM1024 624v-96q0 -16 -16 -16h-96q-16 0 -16 16v96q0 16 16 16 h96q16 0 16 -16zM896 880v-96q0 -16 -16 -16h-96q-16 0 -16 16v96q0 16 16 16h96q16 0 16 -16zM1280 624v-96q0 -16 -16 -16h-96q-16 0 -16 16v96q0 16 16 16h96q16 0 16 -16zM1664 368v-96q0 -16 -16 -16h-96q-16 0 -16 16v96q0 16 16 16h96q16 0 16 -16zM1152 880v-96 q0 -16 -16 -16h-96q-16 0 -16 16v96q0 16 16 16h96q16 0 16 -16zM1408 880v-96q0 -16 -16 -16h-96q-16 0 -16 16v96q0 16 16 16h96q16 0 16 -16zM1664 880v-352q0 -16 -16 -16h-224q-16 0 -16 16v96q0 16 16 16h112v240q0 16 16 16h96q16 0 16 -16zM1792 128v896h-1664v-896 h1664zM1920 1024v-896q0 -53 -37.5 -90.5t-90.5 -37.5h-1664q-53 0 -90.5 37.5t-37.5 90.5v896q0 53 37.5 90.5t90.5 37.5h1664q53 0 90.5 -37.5t37.5 -90.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1664 491v616q-169 -91 -306 -91q-82 0 -145 32q-100 49 -184 76.5t-178 27.5q-173 0 -403 -127v-599q245 113 433 113q55 0 103.5 -7.5t98 -26t77 -31t82.5 -39.5l28 -14q44 -22 101 -22q120 0 293 92zM320 1280q0 -35 -17.5 -64t-46.5 -46v-1266q0 -14 -9 -23t-23 -9 h-64q-14 0 -23 9t-9 23v1266q-29 17 -46.5 46t-17.5 64q0 53 37.5 90.5t90.5 37.5t90.5 -37.5t37.5 -90.5zM1792 1216v-763q0 -39 -35 -57q-10 -5 -17 -9q-218 -116 -369 -116q-88 0 -158 35l-28 14q-64 33 -99 48t-91 29t-114 14q-102 0 -235.5 -44t-228.5 -102 q-15 -9 -33 -9q-16 0 -32 8q-32 19 -32 56v742q0 35 31 55q35 21 78.5 42.5t114 52t152.5 49.5t155 19q112 0 209 -31t209 -86q38 -19 89 -19q122 0 310 112q22 12 31 17q31 16 62 -2q31 -20 31 -55z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M832 536v192q-181 -16 -384 -117v-185q205 96 384 110zM832 954v197q-172 -8 -384 -126v-189q215 111 384 118zM1664 491v184q-235 -116 -384 -71v224q-20 6 -39 15q-5 3 -33 17t-34.5 17t-31.5 15t-34.5 15.5t-32.5 13t-36 12.5t-35 8.5t-39.5 7.5t-39.5 4t-44 2 q-23 0 -49 -3v-222h19q102 0 192.5 -29t197.5 -82q19 -9 39 -15v-188q42 -17 91 -17q120 0 293 92zM1664 918v189q-169 -91 -306 -91q-45 0 -78 8v-196q148 -42 384 90zM320 1280q0 -35 -17.5 -64t-46.5 -46v-1266q0 -14 -9 -23t-23 -9h-64q-14 0 -23 9t-9 23v1266 q-29 17 -46.5 46t-17.5 64q0 53 37.5 90.5t90.5 37.5t90.5 -37.5t37.5 -90.5zM1792 1216v-763q0 -39 -35 -57q-10 -5 -17 -9q-218 -116 -369 -116q-88 0 -158 35l-28 14q-64 33 -99 48t-91 29t-114 14q-102 0 -235.5 -44t-228.5 -102q-15 -9 -33 -9q-16 0 -32 8 q-32 19 -32 56v742q0 35 31 55q35 21 78.5 42.5t114 52t152.5 49.5t155 19q112 0 209 -31t209 -86q38 -19 89 -19q122 0 310 112q22 12 31 17q31 16 62 -2q31 -20 31 -55z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M585 553l-466 -466q-10 -10 -23 -10t-23 10l-50 50q-10 10 -10 23t10 23l393 393l-393 393q-10 10 -10 23t10 23l50 50q10 10 23 10t23 -10l466 -466q10 -10 10 -23t-10 -23zM1664 96v-64q0 -14 -9 -23t-23 -9h-960q-14 0 -23 9t-9 23v64q0 14 9 23t23 9h960q14 0 23 -9 t9 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M617 137l-50 -50q-10 -10 -23 -10t-23 10l-466 466q-10 10 -10 23t10 23l466 466q10 10 23 10t23 -10l50 -50q10 -10 10 -23t-10 -23l-393 -393l393 -393q10 -10 10 -23t-10 -23zM1208 1204l-373 -1291q-4 -13 -15.5 -19.5t-23.5 -2.5l-62 17q-13 4 -19.5 15.5t-2.5 24.5 l373 1291q4 13 15.5 19.5t23.5 2.5l62 -17q13 -4 19.5 -15.5t2.5 -24.5zM1865 553l-466 -466q-10 -10 -23 -10t-23 10l-50 50q-10 10 -10 23t10 23l393 393l-393 393q-10 10 -10 23t10 23l50 50q10 10 23 10t23 -10l466 -466q10 -10 10 -23t-10 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M640 454v-70q0 -42 -39 -59q-13 -5 -25 -5q-27 0 -45 19l-512 512q-19 19 -19 45t19 45l512 512q29 31 70 14q39 -17 39 -59v-69l-397 -398q-19 -19 -19 -45t19 -45zM1792 416q0 -58 -17 -133.5t-38.5 -138t-48 -125t-40.5 -90.5l-20 -40q-8 -17 -28 -17q-6 0 -9 1 q-25 8 -23 34q43 400 -106 565q-64 71 -170.5 110.5t-267.5 52.5v-251q0 -42 -39 -59q-13 -5 -25 -5q-27 0 -45 19l-512 512q-19 19 -19 45t19 45l512 512q29 31 70 14q39 -17 39 -59v-262q411 -28 599 -221q169 -173 169 -509z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1186 579l257 250l-356 52l-66 10l-30 60l-159 322v-963l59 -31l318 -168l-60 355l-12 66zM1638 841l-363 -354l86 -500q5 -33 -6 -51.5t-34 -18.5q-17 0 -40 12l-449 236l-449 -236q-23 -12 -40 -12q-23 0 -34 18.5t-6 51.5l86 500l-364 354q-32 32 -23 59.5t54 34.5 l502 73l225 455q20 41 49 41q28 0 49 -41l225 -455l502 -73q45 -7 54 -34.5t-24 -59.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M1401 1187l-640 -1280q-17 -35 -57 -35q-5 0 -15 2q-22 5 -35.5 22.5t-13.5 39.5v576h-576q-22 0 -39.5 13.5t-22.5 35.5t4 42t29 30l1280 640q13 7 29 7q27 0 45 -19q15 -14 18.5 -34.5t-6.5 -39.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M557 256h595v595zM512 301l595 595h-595v-595zM1664 224v-192q0 -14 -9 -23t-23 -9h-224v-224q0 -14 -9 -23t-23 -9h-192q-14 0 -23 9t-9 23v224h-864q-14 0 -23 9t-9 23v864h-224q-14 0 -23 9t-9 23v192q0 14 9 23t23 9h224v224q0 14 9 23t23 9h192q14 0 23 -9t9 -23 v-224h851l246 247q10 9 23 9t23 -9q9 -10 9 -23t-9 -23l-247 -246v-851h224q14 0 23 -9t9 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M288 64q0 40 -28 68t-68 28t-68 -28t-28 -68t28 -68t68 -28t68 28t28 68zM288 1216q0 40 -28 68t-68 28t-68 -28t-28 -68t28 -68t68 -28t68 28t28 68zM928 1088q0 40 -28 68t-68 28t-68 -28t-28 -68t28 -68t68 -28t68 28t28 68zM1024 1088q0 -52 -26 -96.5t-70 -69.5 q-2 -287 -226 -414q-68 -38 -203 -81q-128 -40 -169.5 -71t-41.5 -100v-26q44 -25 70 -69.5t26 -96.5q0 -80 -56 -136t-136 -56t-136 56t-56 136q0 52 26 96.5t70 69.5v820q-44 25 -70 69.5t-26 96.5q0 80 56 136t136 56t136 -56t56 -136q0 -52 -26 -96.5t-70 -69.5v-497 q54 26 154 57q55 17 87.5 29.5t70.5 31t59 39.5t40.5 51t28 69.5t8.5 91.5q-44 25 -70 69.5t-26 96.5q0 80 56 136t136 56t136 -56t56 -136z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M439 265l-256 -256q-10 -9 -23 -9q-12 0 -23 9q-9 10 -9 23t9 23l256 256q10 9 23 9t23 -9q9 -10 9 -23t-9 -23zM608 224v-320q0 -14 -9 -23t-23 -9t-23 9t-9 23v320q0 14 9 23t23 9t23 -9t9 -23zM384 448q0 -14 -9 -23t-23 -9h-320q-14 0 -23 9t-9 23t9 23t23 9h320 q14 0 23 -9t9 -23zM1648 320q0 -120 -85 -203l-147 -146q-83 -83 -203 -83q-121 0 -204 85l-334 335q-21 21 -42 56l239 18l273 -274q27 -27 68 -27.5t68 26.5l147 146q28 28 28 67q0 40 -28 68l-274 275l18 239q35 -21 56 -42l336 -336q84 -86 84 -204zM1031 1044l-239 -18 l-273 274q-28 28 -68 28q-39 0 -68 -27l-147 -146q-28 -28 -28 -67q0 -40 28 -68l274 -274l-18 -240q-35 21 -56 42l-336 336q-84 86 -84 204q0 120 85 203l147 146q83 83 203 83q121 0 204 -85l334 -335q21 -21 42 -56zM1664 960q0 -14 -9 -23t-23 -9h-320q-14 0 -23 9 t-9 23t9 23t23 9h320q14 0 23 -9t9 -23zM1120 1504v-320q0 -14 -9 -23t-23 -9t-23 9t-9 23v320q0 14 9 23t23 9t23 -9t9 -23zM1527 1353l-256 -256q-11 -9 -23 -9t-23 9q-9 10 -9 23t9 23l256 256q10 9 23 9t23 -9q9 -10 9 -23t-9 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M704 280v-240q0 -16 -12 -28t-28 -12h-240q-16 0 -28 12t-12 28v240q0 16 12 28t28 12h240q16 0 28 -12t12 -28zM1020 880q0 -54 -15.5 -101t-35 -76.5t-55 -59.5t-57.5 -43.5t-61 -35.5q-41 -23 -68.5 -65t-27.5 -67q0 -17 -12 -32.5t-28 -15.5h-240q-15 0 -25.5 18.5 t-10.5 37.5v45q0 83 65 156.5t143 108.5q59 27 84 56t25 76q0 42 -46.5 74t-107.5 32q-65 0 -108 -29q-35 -25 -107 -115q-13 -16 -31 -16q-12 0 -25 8l-164 125q-13 10 -15.5 25t5.5 28q160 266 464 266q80 0 161 -31t146 -83t106 -127.5t41 -158.5z" />
|
||||
<glyph unicode="" horiz-adv-x="640" d="M640 192v-128q0 -26 -19 -45t-45 -19h-512q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h64v384h-64q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h384q26 0 45 -19t19 -45v-576h64q26 0 45 -19t19 -45zM512 1344v-192q0 -26 -19 -45t-45 -19h-256q-26 0 -45 19t-19 45v192 q0 26 19 45t45 19h256q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="640" d="M512 288v-224q0 -26 -19 -45t-45 -19h-256q-26 0 -45 19t-19 45v224q0 26 19 45t45 19h256q26 0 45 -19t19 -45zM542 1344l-28 -768q-1 -26 -20.5 -45t-45.5 -19h-256q-26 0 -45.5 19t-20.5 45l-28 768q-1 26 17.5 45t44.5 19h320q26 0 44.5 -19t17.5 -45z" />
|
||||
<glyph unicode="" d="M897 167v-167h-248l-159 252l-24 42q-8 9 -11 21h-3l-9 -21q-10 -20 -25 -44l-155 -250h-258v167h128l197 291l-185 272h-137v168h276l139 -228q2 -4 23 -42q8 -9 11 -21h3q3 9 11 21l25 42l140 228h257v-168h-125l-184 -267l204 -296h109zM1534 846v-206h-514l-3 27 q-4 28 -4 46q0 64 26 117t65 86.5t84 65t84 54.5t65 54t26 64q0 38 -29.5 62.5t-70.5 24.5q-51 0 -97 -39q-14 -11 -36 -38l-105 92q26 37 63 66q83 65 188 65q110 0 178 -59.5t68 -158.5q0 -56 -24.5 -103t-62 -76.5t-81.5 -58.5t-82 -50.5t-65.5 -51.5t-30.5 -63h232v80 h126z" />
|
||||
<glyph unicode="" d="M897 167v-167h-248l-159 252l-24 42q-8 9 -11 21h-3l-9 -21q-10 -20 -25 -44l-155 -250h-258v167h128l197 291l-185 272h-137v168h276l139 -228q2 -4 23 -42q8 -9 11 -21h3q3 9 11 21l25 42l140 228h257v-168h-125l-184 -267l204 -296h109zM1536 -50v-206h-514l-4 27 q-3 45 -3 46q0 64 26 117t65 86.5t84 65t84 54.5t65 54t26 64q0 38 -29.5 62.5t-70.5 24.5q-51 0 -97 -39q-14 -11 -36 -38l-105 92q26 37 63 66q80 65 188 65q110 0 178 -59.5t68 -158.5q0 -66 -34.5 -118.5t-84 -86t-99.5 -62.5t-87 -63t-41 -73h232v80h126z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M896 128l336 384h-768l-336 -384h768zM1909 1205q15 -34 9.5 -71.5t-30.5 -65.5l-896 -1024q-38 -44 -96 -44h-768q-38 0 -69.5 20.5t-47.5 54.5q-15 34 -9.5 71.5t30.5 65.5l896 1024q38 44 96 44h768q38 0 69.5 -20.5t47.5 -54.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1664 438q0 -81 -44.5 -135t-123.5 -54q-41 0 -77.5 17.5t-59 38t-56.5 38t-71 17.5q-110 0 -110 -124q0 -39 16 -115t15 -115v-5q-22 0 -33 -1q-34 -3 -97.5 -11.5t-115.5 -13.5t-98 -5q-61 0 -103 26.5t-42 83.5q0 37 17.5 71t38 56.5t38 59t17.5 77.5q0 79 -54 123.5 t-135 44.5q-84 0 -143 -45.5t-59 -127.5q0 -43 15 -83t33.5 -64.5t33.5 -53t15 -50.5q0 -45 -46 -89q-37 -35 -117 -35q-95 0 -245 24q-9 2 -27.5 4t-27.5 4l-13 2q-1 0 -3 1q-2 0 -2 1v1024q2 -1 17.5 -3.5t34 -5t21.5 -3.5q150 -24 245 -24q80 0 117 35q46 44 46 89 q0 22 -15 50.5t-33.5 53t-33.5 64.5t-15 83q0 82 59 127.5t144 45.5q80 0 134 -44.5t54 -123.5q0 -41 -17.5 -77.5t-38 -59t-38 -56.5t-17.5 -71q0 -57 42 -83.5t103 -26.5q64 0 180 15t163 17v-2q-1 -2 -3.5 -17.5t-5 -34t-3.5 -21.5q-24 -150 -24 -245q0 -80 35 -117 q44 -46 89 -46q22 0 50.5 15t53 33.5t64.5 33.5t83 15q82 0 127.5 -59t45.5 -143z" />
|
||||
<glyph unicode="" horiz-adv-x="1152" d="M1152 832v-128q0 -221 -147.5 -384.5t-364.5 -187.5v-132h256q26 0 45 -19t19 -45t-19 -45t-45 -19h-640q-26 0 -45 19t-19 45t19 45t45 19h256v132q-217 24 -364.5 187.5t-147.5 384.5v128q0 26 19 45t45 19t45 -19t19 -45v-128q0 -185 131.5 -316.5t316.5 -131.5 t316.5 131.5t131.5 316.5v128q0 26 19 45t45 19t45 -19t19 -45zM896 1216v-512q0 -132 -94 -226t-226 -94t-226 94t-94 226v512q0 132 94 226t226 94t226 -94t94 -226z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M271 591l-101 -101q-42 103 -42 214v128q0 26 19 45t45 19t45 -19t19 -45v-128q0 -53 15 -113zM1385 1193l-361 -361v-128q0 -132 -94 -226t-226 -94q-55 0 -109 19l-96 -96q97 -51 205 -51q185 0 316.5 131.5t131.5 316.5v128q0 26 19 45t45 19t45 -19t19 -45v-128 q0 -221 -147.5 -384.5t-364.5 -187.5v-132h256q26 0 45 -19t19 -45t-19 -45t-45 -19h-640q-26 0 -45 19t-19 45t19 45t45 19h256v132q-125 13 -235 81l-254 -254q-10 -10 -23 -10t-23 10l-82 82q-10 10 -10 23t10 23l1234 1234q10 10 23 10t23 -10l82 -82q10 -10 10 -23 t-10 -23zM1005 1325l-621 -621v512q0 132 94 226t226 94q102 0 184.5 -59t116.5 -152z" />
|
||||
<glyph unicode="" horiz-adv-x="1280" d="M1088 576v640h-448v-1137q119 63 213 137q235 184 235 360zM1280 1344v-768q0 -86 -33.5 -170.5t-83 -150t-118 -127.5t-126.5 -103t-121 -77.5t-89.5 -49.5t-42.5 -20q-12 -6 -26 -6t-26 6q-16 7 -42.5 20t-89.5 49.5t-121 77.5t-126.5 103t-118 127.5t-83 150 t-33.5 170.5v768q0 26 19 45t45 19h1152q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M128 -128h1408v1024h-1408v-1024zM512 1088v288q0 14 -9 23t-23 9h-64q-14 0 -23 -9t-9 -23v-288q0 -14 9 -23t23 -9h64q14 0 23 9t9 23zM1280 1088v288q0 14 -9 23t-23 9h-64q-14 0 -23 -9t-9 -23v-288q0 -14 9 -23t23 -9h64q14 0 23 9t9 23zM1664 1152v-1280 q0 -52 -38 -90t-90 -38h-1408q-52 0 -90 38t-38 90v1280q0 52 38 90t90 38h128v96q0 66 47 113t113 47h64q66 0 113 -47t47 -113v-96h384v96q0 66 47 113t113 47h64q66 0 113 -47t47 -113v-96h128q52 0 90 -38t38 -90z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M512 1344q0 26 -19 45t-45 19t-45 -19t-19 -45t19 -45t45 -19t45 19t19 45zM1408 1376v-320q0 -16 -12 -25q-8 -7 -20 -7q-4 0 -7 1l-448 96q-11 2 -18 11t-7 20h-256v-102q111 -23 183.5 -111t72.5 -203v-800q0 -26 -19 -45t-45 -19h-512q-26 0 -45 19t-19 45v800 q0 106 62.5 190.5t161.5 114.5v111h-32q-59 0 -115 -23.5t-91.5 -53t-66 -66.5t-40.5 -53.5t-14 -24.5q-17 -35 -57 -35q-16 0 -29 7q-23 12 -31.5 37t3.5 49q5 10 14.5 26t37.5 53.5t60.5 70t85 67t108.5 52.5q-25 42 -25 86q0 66 47 113t113 47t113 -47t47 -113 q0 -33 -14 -64h302q0 11 7 20t18 11l448 96q3 1 7 1q12 0 20 -7q12 -9 12 -25z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1440 1088q0 40 -28 68t-68 28t-68 -28t-28 -68t28 -68t68 -28t68 28t28 68zM1664 1376q0 -249 -75.5 -430.5t-253.5 -360.5q-81 -80 -195 -176l-20 -379q-2 -16 -16 -26l-384 -224q-7 -4 -16 -4q-12 0 -23 9l-64 64q-13 14 -8 32l85 276l-281 281l-276 -85q-3 -1 -9 -1 q-14 0 -23 9l-64 64q-17 19 -5 39l224 384q10 14 26 16l379 20q96 114 176 195q188 187 358 258t431 71q14 0 24 -9.5t10 -22.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1745 763l-164 -763h-334l178 832q13 56 -15 88q-27 33 -83 33h-169l-204 -953h-334l204 953h-286l-204 -953h-334l204 953l-153 327h1276q101 0 189.5 -40.5t147.5 -113.5q60 -73 81 -168.5t0 -194.5z" />
|
||||
<glyph unicode="" d="M909 141l102 102q19 19 19 45t-19 45l-307 307l307 307q19 19 19 45t-19 45l-102 102q-19 19 -45 19t-45 -19l-454 -454q-19 -19 -19 -45t19 -45l454 -454q19 -19 45 -19t45 19zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5 t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M717 141l454 454q19 19 19 45t-19 45l-454 454q-19 19 -45 19t-45 -19l-102 -102q-19 -19 -19 -45t19 -45l307 -307l-307 -307q-19 -19 -19 -45t19 -45l102 -102q19 -19 45 -19t45 19zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5 t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M1165 397l102 102q19 19 19 45t-19 45l-454 454q-19 19 -45 19t-45 -19l-454 -454q-19 -19 -19 -45t19 -45l102 -102q19 -19 45 -19t45 19l307 307l307 -307q19 -19 45 -19t45 19zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5 t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M813 237l454 454q19 19 19 45t-19 45l-102 102q-19 19 -45 19t-45 -19l-307 -307l-307 307q-19 19 -45 19t-45 -19l-102 -102q-19 -19 -19 -45t19 -45l454 -454q19 -19 45 -19t45 19zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5 t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M1130 939l16 175h-884l47 -534h612l-22 -228l-197 -53l-196 53l-13 140h-175l22 -278l362 -100h4v1l359 99l50 544h-644l-15 181h674zM0 1408h1408l-128 -1438l-578 -162l-574 162z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M275 1408h1505l-266 -1333l-804 -267l-698 267l71 356h297l-29 -147l422 -161l486 161l68 339h-1208l58 297h1209l38 191h-1208z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M960 1280q0 26 -19 45t-45 19t-45 -19t-19 -45t19 -45t45 -19t45 19t19 45zM1792 352v-352q0 -22 -20 -30q-8 -2 -12 -2q-13 0 -23 9l-93 93q-119 -143 -318.5 -226.5t-429.5 -83.5t-429.5 83.5t-318.5 226.5l-93 -93q-9 -9 -23 -9q-4 0 -12 2q-20 8 -20 30v352 q0 14 9 23t23 9h352q22 0 30 -20q8 -19 -7 -35l-100 -100q67 -91 189.5 -153.5t271.5 -82.5v647h-192q-26 0 -45 19t-19 45v128q0 26 19 45t45 19h192v163q-58 34 -93 92.5t-35 128.5q0 106 75 181t181 75t181 -75t75 -181q0 -70 -35 -128.5t-93 -92.5v-163h192q26 0 45 -19 t19 -45v-128q0 -26 -19 -45t-45 -19h-192v-647q149 20 271.5 82.5t189.5 153.5l-100 100q-15 16 -7 35q8 20 30 20h352q14 0 23 -9t9 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1152" d="M1056 768q40 0 68 -28t28 -68v-576q0 -40 -28 -68t-68 -28h-960q-40 0 -68 28t-28 68v576q0 40 28 68t68 28h32v320q0 185 131.5 316.5t316.5 131.5t316.5 -131.5t131.5 -316.5q0 -26 -19 -45t-45 -19h-64q-26 0 -45 19t-19 45q0 106 -75 181t-181 75t-181 -75t-75 -181 v-320h736z" />
|
||||
<glyph unicode="" d="M1024 640q0 -106 -75 -181t-181 -75t-181 75t-75 181t75 181t181 75t181 -75t75 -181zM1152 640q0 159 -112.5 271.5t-271.5 112.5t-271.5 -112.5t-112.5 -271.5t112.5 -271.5t271.5 -112.5t271.5 112.5t112.5 271.5zM1280 640q0 -212 -150 -362t-362 -150t-362 150 t-150 362t150 362t362 150t362 -150t150 -362zM1408 640q0 130 -51 248.5t-136.5 204t-204 136.5t-248.5 51t-248.5 -51t-204 -136.5t-136.5 -204t-51 -248.5t51 -248.5t136.5 -204t204 -136.5t248.5 -51t248.5 51t204 136.5t136.5 204t51 248.5zM1536 640 q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M384 800v-192q0 -40 -28 -68t-68 -28h-192q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h192q40 0 68 -28t28 -68zM896 800v-192q0 -40 -28 -68t-68 -28h-192q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h192q40 0 68 -28t28 -68zM1408 800v-192q0 -40 -28 -68t-68 -28h-192 q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h192q40 0 68 -28t28 -68z" />
|
||||
<glyph unicode="" horiz-adv-x="384" d="M384 288v-192q0 -40 -28 -68t-68 -28h-192q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h192q40 0 68 -28t28 -68zM384 800v-192q0 -40 -28 -68t-68 -28h-192q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h192q40 0 68 -28t28 -68zM384 1312v-192q0 -40 -28 -68t-68 -28h-192 q-40 0 -68 28t-28 68v192q0 40 28 68t68 28h192q40 0 68 -28t28 -68z" />
|
||||
<glyph unicode="" d="M512 256q0 53 -37.5 90.5t-90.5 37.5t-90.5 -37.5t-37.5 -90.5t37.5 -90.5t90.5 -37.5t90.5 37.5t37.5 90.5zM863 162q-13 232 -177 396t-396 177q-14 1 -24 -9t-10 -23v-128q0 -13 8.5 -22t21.5 -10q154 -11 264 -121t121 -264q1 -13 10 -21.5t22 -8.5h128q13 0 23 10 t9 24zM1247 161q-5 154 -56 297.5t-139.5 260t-205 205t-260 139.5t-297.5 56q-14 1 -23 -9q-10 -10 -10 -23v-128q0 -13 9 -22t22 -10q204 -7 378 -111.5t278.5 -278.5t111.5 -378q1 -13 10 -22t22 -9h128q13 0 23 10q11 9 9 23zM1536 1120v-960q0 -119 -84.5 -203.5 t-203.5 -84.5h-960q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" d="M768 1408q209 0 385.5 -103t279.5 -279.5t103 -385.5t-103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103zM1152 585q32 18 32 55t-32 55l-544 320q-31 19 -64 1q-32 -19 -32 -56v-640q0 -37 32 -56 q16 -8 32 -8q17 0 32 9z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1024 1084l316 -316l-572 -572l-316 316zM813 105l618 618q19 19 19 45t-19 45l-362 362q-18 18 -45 18t-45 -18l-618 -618q-19 -19 -19 -45t19 -45l362 -362q18 -18 45 -18t45 18zM1702 742l-907 -908q-37 -37 -90.5 -37t-90.5 37l-126 126q56 56 56 136t-56 136 t-136 56t-136 -56l-125 126q-37 37 -37 90.5t37 90.5l907 906q37 37 90.5 37t90.5 -37l125 -125q-56 -56 -56 -136t56 -136t136 -56t136 56l126 -125q37 -37 37 -90.5t-37 -90.5z" />
|
||||
<glyph unicode="" d="M1280 576v128q0 26 -19 45t-45 19h-896q-26 0 -45 -19t-19 -45v-128q0 -26 19 -45t45 -19h896q26 0 45 19t19 45zM1536 1120v-960q0 -119 -84.5 -203.5t-203.5 -84.5h-960q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5 t84.5 -203.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M1152 736v-64q0 -14 -9 -23t-23 -9h-832q-14 0 -23 9t-9 23v64q0 14 9 23t23 9h832q14 0 23 -9t9 -23zM1280 288v832q0 66 -47 113t-113 47h-832q-66 0 -113 -47t-47 -113v-832q0 -66 47 -113t113 -47h832q66 0 113 47t47 113zM1408 1120v-832q0 -119 -84.5 -203.5 t-203.5 -84.5h-832q-119 0 -203.5 84.5t-84.5 203.5v832q0 119 84.5 203.5t203.5 84.5h832q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M1018 933q-18 -37 -58 -37h-192v-864q0 -14 -9 -23t-23 -9h-704q-21 0 -29 18q-8 20 4 35l160 192q9 11 25 11h320v640h-192q-40 0 -58 37q-17 37 9 68l320 384q18 22 49 22t49 -22l320 -384q27 -32 9 -68z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M32 1280h704q13 0 22.5 -9.5t9.5 -23.5v-863h192q40 0 58 -37t-9 -69l-320 -384q-18 -22 -49 -22t-49 22l-320 384q-26 31 -9 69q18 37 58 37h192v640h-320q-14 0 -25 11l-160 192q-13 14 -4 34q9 19 29 19z" />
|
||||
<glyph unicode="" d="M685 237l614 614q19 19 19 45t-19 45l-102 102q-19 19 -45 19t-45 -19l-467 -467l-211 211q-19 19 -45 19t-45 -19l-102 -102q-19 -19 -19 -45t19 -45l358 -358q19 -19 45 -19t45 19zM1536 1120v-960q0 -119 -84.5 -203.5t-203.5 -84.5h-960q-119 0 -203.5 84.5 t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" d="M404 428l152 -152l-52 -52h-56v96h-96v56zM818 818q14 -13 -3 -30l-291 -291q-17 -17 -30 -3q-14 13 3 30l291 291q17 17 30 3zM544 128l544 544l-288 288l-544 -544v-288h288zM1152 736l92 92q28 28 28 68t-28 68l-152 152q-28 28 -68 28t-68 -28l-92 -92zM1536 1120 v-960q0 -119 -84.5 -203.5t-203.5 -84.5h-960q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" d="M1280 608v480q0 26 -19 45t-45 19h-480q-42 0 -59 -39q-17 -41 14 -70l144 -144l-534 -534q-19 -19 -19 -45t19 -45l102 -102q19 -19 45 -19t45 19l534 534l144 -144q18 -19 45 -19q12 0 25 5q39 17 39 59zM1536 1120v-960q0 -119 -84.5 -203.5t-203.5 -84.5h-960 q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" d="M1005 435l352 352q19 19 19 45t-19 45l-352 352q-30 31 -69 14q-40 -17 -40 -59v-160q-119 0 -216 -19.5t-162.5 -51t-114 -79t-76.5 -95.5t-44.5 -109t-21.5 -111.5t-5 -110.5q0 -181 167 -404q10 -12 25 -12q7 0 13 3q22 9 19 33q-44 354 62 473q46 52 130 75.5 t224 23.5v-160q0 -42 40 -59q12 -5 24 -5q26 0 45 19zM1536 1120v-960q0 -119 -84.5 -203.5t-203.5 -84.5h-960q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" d="M640 448l256 128l-256 128v-256zM1024 1039v-542l-512 -256v542zM1312 640q0 148 -73 273t-198 198t-273 73t-273 -73t-198 -198t-73 -273t73 -273t198 -198t273 -73t273 73t198 198t73 273zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103 t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M1145 861q18 -35 -5 -66l-320 -448q-19 -27 -52 -27t-52 27l-320 448q-23 31 -5 66q17 35 57 35h640q40 0 57 -35zM1280 160v960q0 13 -9.5 22.5t-22.5 9.5h-960q-13 0 -22.5 -9.5t-9.5 -22.5v-960q0 -13 9.5 -22.5t22.5 -9.5h960q13 0 22.5 9.5t9.5 22.5zM1536 1120 v-960q0 -119 -84.5 -203.5t-203.5 -84.5h-960q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" d="M1145 419q-17 -35 -57 -35h-640q-40 0 -57 35q-18 35 5 66l320 448q19 27 52 27t52 -27l320 -448q23 -31 5 -66zM1280 160v960q0 13 -9.5 22.5t-22.5 9.5h-960q-13 0 -22.5 -9.5t-9.5 -22.5v-960q0 -13 9.5 -22.5t22.5 -9.5h960q13 0 22.5 9.5t9.5 22.5zM1536 1120v-960 q0 -119 -84.5 -203.5t-203.5 -84.5h-960q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" d="M1088 640q0 -33 -27 -52l-448 -320q-31 -23 -66 -5q-35 17 -35 57v640q0 40 35 57q35 18 66 -5l448 -320q27 -19 27 -52zM1280 160v960q0 14 -9 23t-23 9h-960q-14 0 -23 -9t-9 -23v-960q0 -14 9 -23t23 -9h960q14 0 23 9t9 23zM1536 1120v-960q0 -119 -84.5 -203.5 t-203.5 -84.5h-960q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M976 229l35 -159q3 -12 -3 -22.5t-17 -14.5l-5 -1q-4 -2 -10.5 -3.5t-16 -4.5t-21.5 -5.5t-25.5 -5t-30 -5t-33.5 -4.5t-36.5 -3t-38.5 -1q-234 0 -409 130.5t-238 351.5h-95q-13 0 -22.5 9.5t-9.5 22.5v113q0 13 9.5 22.5t22.5 9.5h66q-2 57 1 105h-67q-14 0 -23 9 t-9 23v114q0 14 9 23t23 9h98q67 210 243.5 338t400.5 128q102 0 194 -23q11 -3 20 -15q6 -11 3 -24l-43 -159q-3 -13 -14 -19.5t-24 -2.5l-4 1q-4 1 -11.5 2.5l-17.5 3.5t-22.5 3.5t-26 3t-29 2.5t-29.5 1q-126 0 -226 -64t-150 -176h468q16 0 25 -12q10 -12 7 -26 l-24 -114q-5 -26 -32 -26h-488q-3 -37 0 -105h459q15 0 25 -12q9 -12 6 -27l-24 -112q-2 -11 -11 -18.5t-20 -7.5h-387q48 -117 149.5 -185.5t228.5 -68.5q18 0 36 1.5t33.5 3.5t29.5 4.5t24.5 5t18.5 4.5l12 3l5 2q13 5 26 -2q12 -7 15 -21z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M1020 399v-367q0 -14 -9 -23t-23 -9h-956q-14 0 -23 9t-9 23v150q0 13 9.5 22.5t22.5 9.5h97v383h-95q-14 0 -23 9.5t-9 22.5v131q0 14 9 23t23 9h95v223q0 171 123.5 282t314.5 111q185 0 335 -125q9 -8 10 -20.5t-7 -22.5l-103 -127q-9 -11 -22 -12q-13 -2 -23 7 q-5 5 -26 19t-69 32t-93 18q-85 0 -137 -47t-52 -123v-215h305q13 0 22.5 -9t9.5 -23v-131q0 -13 -9.5 -22.5t-22.5 -9.5h-305v-379h414v181q0 13 9 22.5t23 9.5h162q14 0 23 -9.5t9 -22.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M978 351q0 -153 -99.5 -263.5t-258.5 -136.5v-175q0 -14 -9 -23t-23 -9h-135q-13 0 -22.5 9.5t-9.5 22.5v175q-66 9 -127.5 31t-101.5 44.5t-74 48t-46.5 37.5t-17.5 18q-17 21 -2 41l103 135q7 10 23 12q15 2 24 -9l2 -2q113 -99 243 -125q37 -8 74 -8q81 0 142.5 43 t61.5 122q0 28 -15 53t-33.5 42t-58.5 37.5t-66 32t-80 32.5q-39 16 -61.5 25t-61.5 26.5t-62.5 31t-56.5 35.5t-53.5 42.5t-43.5 49t-35.5 58t-21 66.5t-8.5 78q0 138 98 242t255 134v180q0 13 9.5 22.5t22.5 9.5h135q14 0 23 -9t9 -23v-176q57 -6 110.5 -23t87 -33.5 t63.5 -37.5t39 -29t15 -14q17 -18 5 -38l-81 -146q-8 -15 -23 -16q-14 -3 -27 7q-3 3 -14.5 12t-39 26.5t-58.5 32t-74.5 26t-85.5 11.5q-95 0 -155 -43t-60 -111q0 -26 8.5 -48t29.5 -41.5t39.5 -33t56 -31t60.5 -27t70 -27.5q53 -20 81 -31.5t76 -35t75.5 -42.5t62 -50 t53 -63.5t31.5 -76.5t13 -94z" />
|
||||
<glyph unicode="" horiz-adv-x="898" d="M898 1066v-102q0 -14 -9 -23t-23 -9h-168q-23 -144 -129 -234t-276 -110q167 -178 459 -536q14 -16 4 -34q-8 -18 -29 -18h-195q-16 0 -25 12q-306 367 -498 571q-9 9 -9 22v127q0 13 9.5 22.5t22.5 9.5h112q132 0 212.5 43t102.5 125h-427q-14 0 -23 9t-9 23v102 q0 14 9 23t23 9h413q-57 113 -268 113h-145q-13 0 -22.5 9.5t-9.5 22.5v133q0 14 9 23t23 9h832q14 0 23 -9t9 -23v-102q0 -14 -9 -23t-23 -9h-233q47 -61 64 -144h171q14 0 23 -9t9 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1027" d="M603 0h-172q-13 0 -22.5 9t-9.5 23v330h-288q-13 0 -22.5 9t-9.5 23v103q0 13 9.5 22.5t22.5 9.5h288v85h-288q-13 0 -22.5 9t-9.5 23v104q0 13 9.5 22.5t22.5 9.5h214l-321 578q-8 16 0 32q10 16 28 16h194q19 0 29 -18l215 -425q19 -38 56 -125q10 24 30.5 68t27.5 61 l191 420q8 19 29 19h191q17 0 27 -16q9 -14 1 -31l-313 -579h215q13 0 22.5 -9.5t9.5 -22.5v-104q0 -14 -9.5 -23t-22.5 -9h-290v-85h290q13 0 22.5 -9.5t9.5 -22.5v-103q0 -14 -9.5 -23t-22.5 -9h-290v-330q0 -13 -9.5 -22.5t-22.5 -9.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1280" d="M1043 971q0 100 -65 162t-171 62h-320v-448h320q106 0 171 62t65 162zM1280 971q0 -193 -126.5 -315t-326.5 -122h-340v-118h505q14 0 23 -9t9 -23v-128q0 -14 -9 -23t-23 -9h-505v-192q0 -14 -9.5 -23t-22.5 -9h-167q-14 0 -23 9t-9 23v192h-224q-14 0 -23 9t-9 23v128 q0 14 9 23t23 9h224v118h-224q-14 0 -23 9t-9 23v149q0 13 9 22.5t23 9.5h224v629q0 14 9 23t23 9h539q200 0 326.5 -122t126.5 -315z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M514 341l81 299h-159l75 -300q1 -1 1 -3t1 -3q0 1 0.5 3.5t0.5 3.5zM630 768l35 128h-292l32 -128h225zM822 768h139l-35 128h-70zM1271 340l78 300h-162l81 -299q0 -1 0.5 -3.5t1.5 -3.5q0 1 0.5 3t0.5 3zM1382 768l33 128h-297l34 -128h230zM1792 736v-64q0 -14 -9 -23 t-23 -9h-213l-164 -616q-7 -24 -31 -24h-159q-24 0 -31 24l-166 616h-209l-167 -616q-7 -24 -31 -24h-159q-11 0 -19.5 7t-10.5 17l-160 616h-208q-14 0 -23 9t-9 23v64q0 14 9 23t23 9h175l-33 128h-142q-14 0 -23 9t-9 23v64q0 14 9 23t23 9h109l-89 344q-5 15 5 28 q10 12 26 12h137q26 0 31 -24l90 -360h359l97 360q7 24 31 24h126q24 0 31 -24l98 -360h365l93 360q5 24 31 24h137q16 0 26 -12q10 -13 5 -28l-91 -344h111q14 0 23 -9t9 -23v-64q0 -14 -9 -23t-23 -9h-145l-34 -128h179q14 0 23 -9t9 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1280" d="M1167 896q18 -182 -131 -258q117 -28 175 -103t45 -214q-7 -71 -32.5 -125t-64.5 -89t-97 -58.5t-121.5 -34.5t-145.5 -15v-255h-154v251q-80 0 -122 1v-252h-154v255q-18 0 -54 0.5t-55 0.5h-200l31 183h111q50 0 58 51v402h16q-6 1 -16 1v287q-13 68 -89 68h-111v164 l212 -1q64 0 97 1v252h154v-247q82 2 122 2v245h154v-252q79 -7 140 -22.5t113 -45t82.5 -78t36.5 -114.5zM952 351q0 36 -15 64t-37 46t-57.5 30.5t-65.5 18.5t-74 9t-69 3t-64.5 -1t-47.5 -1v-338q8 0 37 -0.5t48 -0.5t53 1.5t58.5 4t57 8.5t55.5 14t47.5 21t39.5 30 t24.5 40t9.5 51zM881 827q0 33 -12.5 58.5t-30.5 42t-48 28t-55 16.5t-61.5 8t-58 2.5t-54 -1t-39.5 -0.5v-307q5 0 34.5 -0.5t46.5 0t50 2t55 5.5t51.5 11t48.5 18.5t37 27t27 38.5t9 51z" />
|
||||
<glyph unicode="" horiz-adv-x="1280" d="M1280 768v-800q0 -40 -28 -68t-68 -28h-1088q-40 0 -68 28t-28 68v1344q0 40 28 68t68 28h544v-544q0 -40 28 -68t68 -28h544zM1277 896h-509v509q82 -15 132 -65l312 -312q50 -50 65 -132z" />
|
||||
<glyph unicode="" horiz-adv-x="1280" d="M1024 160v64q0 14 -9 23t-23 9h-704q-14 0 -23 -9t-9 -23v-64q0 -14 9 -23t23 -9h704q14 0 23 9t9 23zM1024 416v64q0 14 -9 23t-23 9h-704q-14 0 -23 -9t-9 -23v-64q0 -14 9 -23t23 -9h704q14 0 23 9t9 23zM1280 768v-800q0 -40 -28 -68t-68 -28h-1088q-40 0 -68 28 t-28 68v1344q0 40 28 68t68 28h544v-544q0 -40 28 -68t68 -28h544zM1277 896h-509v509q82 -15 132 -65l312 -312q50 -50 65 -132z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1191 1128h177l-72 218l-12 47q-2 16 -2 20h-4l-3 -20q0 -1 -3.5 -18t-7.5 -29zM736 96q0 -12 -10 -24l-319 -319q-10 -9 -23 -9q-12 0 -23 9l-320 320q-15 16 -7 35q8 20 30 20h192v1376q0 14 9 23t23 9h192q14 0 23 -9t9 -23v-1376h192q14 0 23 -9t9 -23zM1572 -23 v-233h-584v90l369 529q12 18 21 27l11 9v3q-2 0 -6.5 -0.5t-7.5 -0.5q-12 -3 -30 -3h-232v-115h-120v229h567v-89l-369 -530q-6 -8 -21 -26l-11 -11v-2l14 2q9 2 30 2h248v119h121zM1661 874v-106h-288v106h75l-47 144h-243l-47 -144h75v-106h-287v106h70l230 662h162 l230 -662h70z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1191 104h177l-72 218l-12 47q-2 16 -2 20h-4l-3 -20q0 -1 -3.5 -18t-7.5 -29zM736 96q0 -12 -10 -24l-319 -319q-10 -9 -23 -9q-12 0 -23 9l-320 320q-15 16 -7 35q8 20 30 20h192v1376q0 14 9 23t23 9h192q14 0 23 -9t9 -23v-1376h192q14 0 23 -9t9 -23zM1661 -150 v-106h-288v106h75l-47 144h-243l-47 -144h75v-106h-287v106h70l230 662h162l230 -662h70zM1572 1001v-233h-584v90l369 529q12 18 21 27l11 9v3q-2 0 -6.5 -0.5t-7.5 -0.5q-12 -3 -30 -3h-232v-115h-120v229h567v-89l-369 -530q-6 -8 -21 -26l-11 -10v-3l14 3q9 1 30 1h248 v119h121z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M736 96q0 -12 -10 -24l-319 -319q-10 -9 -23 -9q-12 0 -23 9l-320 320q-15 16 -7 35q8 20 30 20h192v1376q0 14 9 23t23 9h192q14 0 23 -9t9 -23v-1376h192q14 0 23 -9t9 -23zM1792 -32v-192q0 -14 -9 -23t-23 -9h-832q-14 0 -23 9t-9 23v192q0 14 9 23t23 9h832 q14 0 23 -9t9 -23zM1600 480v-192q0 -14 -9 -23t-23 -9h-640q-14 0 -23 9t-9 23v192q0 14 9 23t23 9h640q14 0 23 -9t9 -23zM1408 992v-192q0 -14 -9 -23t-23 -9h-448q-14 0 -23 9t-9 23v192q0 14 9 23t23 9h448q14 0 23 -9t9 -23zM1216 1504v-192q0 -14 -9 -23t-23 -9h-256 q-14 0 -23 9t-9 23v192q0 14 9 23t23 9h256q14 0 23 -9t9 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1216 -32v-192q0 -14 -9 -23t-23 -9h-256q-14 0 -23 9t-9 23v192q0 14 9 23t23 9h256q14 0 23 -9t9 -23zM736 96q0 -12 -10 -24l-319 -319q-10 -9 -23 -9q-12 0 -23 9l-320 320q-15 16 -7 35q8 20 30 20h192v1376q0 14 9 23t23 9h192q14 0 23 -9t9 -23v-1376h192 q14 0 23 -9t9 -23zM1408 480v-192q0 -14 -9 -23t-23 -9h-448q-14 0 -23 9t-9 23v192q0 14 9 23t23 9h448q14 0 23 -9t9 -23zM1600 992v-192q0 -14 -9 -23t-23 -9h-640q-14 0 -23 9t-9 23v192q0 14 9 23t23 9h640q14 0 23 -9t9 -23zM1792 1504v-192q0 -14 -9 -23t-23 -9h-832 q-14 0 -23 9t-9 23v192q0 14 9 23t23 9h832q14 0 23 -9t9 -23z" />
|
||||
<glyph unicode="" d="M1346 223q0 63 -44 116t-103 53q-52 0 -83 -37t-31 -94t36.5 -95t104.5 -38q50 0 85 27t35 68zM736 96q0 -12 -10 -24l-319 -319q-10 -9 -23 -9q-12 0 -23 9l-320 320q-15 16 -7 35q8 20 30 20h192v1376q0 14 9 23t23 9h192q14 0 23 -9t9 -23v-1376h192q14 0 23 -9t9 -23 zM1486 165q0 -62 -13 -121.5t-41 -114t-68 -95.5t-98.5 -65.5t-127.5 -24.5q-62 0 -108 16q-24 8 -42 15l39 113q15 -7 31 -11q37 -13 75 -13q84 0 134.5 58.5t66.5 145.5h-2q-21 -23 -61.5 -37t-84.5 -14q-106 0 -173 71.5t-67 172.5q0 105 72 178t181 73q123 0 205 -94.5 t82 -252.5zM1456 882v-114h-469v114h167v432q0 7 0.5 19t0.5 17v16h-2l-7 -12q-8 -13 -26 -31l-62 -58l-82 86l192 185h123v-654h165z" />
|
||||
<glyph unicode="" d="M1346 1247q0 63 -44 116t-103 53q-52 0 -83 -37t-31 -94t36.5 -95t104.5 -38q50 0 85 27t35 68zM736 96q0 -12 -10 -24l-319 -319q-10 -9 -23 -9q-12 0 -23 9l-320 320q-15 16 -7 35q8 20 30 20h192v1376q0 14 9 23t23 9h192q14 0 23 -9t9 -23v-1376h192q14 0 23 -9 t9 -23zM1456 -142v-114h-469v114h167v432q0 7 0.5 19t0.5 17v16h-2l-7 -12q-8 -13 -26 -31l-62 -58l-82 86l192 185h123v-654h165zM1486 1189q0 -62 -13 -121.5t-41 -114t-68 -95.5t-98.5 -65.5t-127.5 -24.5q-62 0 -108 16q-24 8 -42 15l39 113q15 -7 31 -11q37 -13 75 -13 q84 0 134.5 58.5t66.5 145.5h-2q-21 -23 -61.5 -37t-84.5 -14q-106 0 -173 71.5t-67 172.5q0 105 72 178t181 73q123 0 205 -94.5t82 -252.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M256 192q0 26 -19 45t-45 19q-27 0 -45.5 -19t-18.5 -45q0 -27 18.5 -45.5t45.5 -18.5q26 0 45 18.5t19 45.5zM416 704v-640q0 -26 -19 -45t-45 -19h-288q-26 0 -45 19t-19 45v640q0 26 19 45t45 19h288q26 0 45 -19t19 -45zM1600 704q0 -86 -55 -149q15 -44 15 -76 q3 -76 -43 -137q17 -56 0 -117q-15 -57 -54 -94q9 -112 -49 -181q-64 -76 -197 -78h-36h-76h-17q-66 0 -144 15.5t-121.5 29t-120.5 39.5q-123 43 -158 44q-26 1 -45 19.5t-19 44.5v641q0 25 18 43.5t43 20.5q24 2 76 59t101 121q68 87 101 120q18 18 31 48t17.5 48.5 t13.5 60.5q7 39 12.5 61t19.5 52t34 50q19 19 45 19q46 0 82.5 -10.5t60 -26t40 -40.5t24 -45t12 -50t5 -45t0.5 -39q0 -38 -9.5 -76t-19 -60t-27.5 -56q-3 -6 -10 -18t-11 -22t-8 -24h277q78 0 135 -57t57 -135z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M256 960q0 -26 -19 -45t-45 -19q-27 0 -45.5 19t-18.5 45q0 27 18.5 45.5t45.5 18.5q26 0 45 -18.5t19 -45.5zM416 448v640q0 26 -19 45t-45 19h-288q-26 0 -45 -19t-19 -45v-640q0 -26 19 -45t45 -19h288q26 0 45 19t19 45zM1545 597q55 -61 55 -149q-1 -78 -57.5 -135 t-134.5 -57h-277q4 -14 8 -24t11 -22t10 -18q18 -37 27 -57t19 -58.5t10 -76.5q0 -24 -0.5 -39t-5 -45t-12 -50t-24 -45t-40 -40.5t-60 -26t-82.5 -10.5q-26 0 -45 19q-20 20 -34 50t-19.5 52t-12.5 61q-9 42 -13.5 60.5t-17.5 48.5t-31 48q-33 33 -101 120q-49 64 -101 121 t-76 59q-25 2 -43 20.5t-18 43.5v641q0 26 19 44.5t45 19.5q35 1 158 44q77 26 120.5 39.5t121.5 29t144 15.5h17h76h36q133 -2 197 -78q58 -69 49 -181q39 -37 54 -94q17 -61 0 -117q46 -61 43 -137q0 -32 -15 -76z" />
|
||||
<glyph unicode="" d="M919 233v157q0 50 -29 50q-17 0 -33 -16v-224q16 -16 33 -16q29 0 29 49zM1103 355h66v34q0 51 -33 51t-33 -51v-34zM532 621v-70h-80v-423h-74v423h-78v70h232zM733 495v-367h-67v40q-39 -45 -76 -45q-33 0 -42 28q-6 16 -6 54v290h66v-270q0 -24 1 -26q1 -15 15 -15 q20 0 42 31v280h67zM985 384v-146q0 -52 -7 -73q-12 -42 -53 -42q-35 0 -68 41v-36h-67v493h67v-161q32 40 68 40q41 0 53 -42q7 -21 7 -74zM1236 255v-9q0 -29 -2 -43q-3 -22 -15 -40q-27 -40 -80 -40q-52 0 -81 38q-21 27 -21 86v129q0 59 20 86q29 38 80 38t78 -38 q21 -28 21 -86v-76h-133v-65q0 -51 34 -51q24 0 30 26q0 1 0.5 7t0.5 16.5v21.5h68zM785 1079v-156q0 -51 -32 -51t-32 51v156q0 52 32 52t32 -52zM1318 366q0 177 -19 260q-10 44 -43 73.5t-76 34.5q-136 15 -412 15q-275 0 -411 -15q-44 -5 -76.5 -34.5t-42.5 -73.5 q-20 -87 -20 -260q0 -176 20 -260q10 -43 42.5 -73t75.5 -35q137 -15 412 -15t412 15q43 5 75.5 35t42.5 73q20 84 20 260zM563 1017l90 296h-75l-51 -195l-53 195h-78l24 -69t23 -69q35 -103 46 -158v-201h74v201zM852 936v130q0 58 -21 87q-29 38 -78 38q-51 0 -78 -38 q-21 -29 -21 -87v-130q0 -58 21 -87q27 -38 78 -38q49 0 78 38q21 27 21 87zM1033 816h67v370h-67v-283q-22 -31 -42 -31q-15 0 -16 16q-1 2 -1 26v272h-67v-293q0 -37 6 -55q11 -27 43 -27q36 0 77 45v-40zM1536 1120v-960q0 -119 -84.5 -203.5t-203.5 -84.5h-960 q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" d="M971 292v-211q0 -67 -39 -67q-23 0 -45 22v301q22 22 45 22q39 0 39 -67zM1309 291v-46h-90v46q0 68 45 68t45 -68zM343 509h107v94h-312v-94h105v-569h100v569zM631 -60h89v494h-89v-378q-30 -42 -57 -42q-18 0 -21 21q-1 3 -1 35v364h-89v-391q0 -49 8 -73 q12 -37 58 -37q48 0 102 61v-54zM1060 88v197q0 73 -9 99q-17 56 -71 56q-50 0 -93 -54v217h-89v-663h89v48q45 -55 93 -55q54 0 71 55q9 27 9 100zM1398 98v13h-91q0 -51 -2 -61q-7 -36 -40 -36q-46 0 -46 69v87h179v103q0 79 -27 116q-39 51 -106 51q-68 0 -107 -51 q-28 -37 -28 -116v-173q0 -79 29 -116q39 -51 108 -51q72 0 108 53q18 27 21 54q2 9 2 58zM790 1011v210q0 69 -43 69t-43 -69v-210q0 -70 43 -70t43 70zM1509 260q0 -234 -26 -350q-14 -59 -58 -99t-102 -46q-184 -21 -555 -21t-555 21q-58 6 -102.5 46t-57.5 99 q-26 112 -26 350q0 234 26 350q14 59 58 99t103 47q183 20 554 20t555 -20q58 -7 102.5 -47t57.5 -99q26 -112 26 -350zM511 1536h102l-121 -399v-271h-100v271q-14 74 -61 212q-37 103 -65 187h106l71 -263zM881 1203v-175q0 -81 -28 -118q-37 -51 -106 -51q-67 0 -105 51 q-28 38 -28 118v175q0 80 28 117q38 51 105 51q69 0 106 -51q28 -37 28 -117zM1216 1365v-499h-91v55q-53 -62 -103 -62q-46 0 -59 37q-8 24 -8 75v394h91v-367q0 -33 1 -35q3 -22 21 -22q27 0 57 43v381h91z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M597 869q-10 -18 -257 -456q-27 -46 -65 -46h-239q-21 0 -31 17t0 36l253 448q1 0 0 1l-161 279q-12 22 -1 37q9 15 32 15h239q40 0 66 -45zM1403 1511q11 -16 0 -37l-528 -934v-1l336 -615q11 -20 1 -37q-10 -15 -32 -15h-239q-42 0 -66 45l-339 622q18 32 531 942 q25 45 64 45h241q22 0 31 -15z" />
|
||||
<glyph unicode="" d="M685 771q0 1 -126 222q-21 34 -52 34h-184q-18 0 -26 -11q-7 -12 1 -29l125 -216v-1l-196 -346q-9 -14 0 -28q8 -13 24 -13h185q31 0 50 36zM1309 1268q-7 12 -24 12h-187q-30 0 -49 -35l-411 -729q1 -2 262 -481q20 -35 52 -35h184q18 0 25 12q8 13 -1 28l-260 476v1 l409 723q8 16 0 28zM1536 1120v-960q0 -119 -84.5 -203.5t-203.5 -84.5h-960q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1280 640q0 37 -30 54l-512 320q-31 20 -65 2q-33 -18 -33 -56v-640q0 -38 33 -56q16 -8 31 -8q20 0 34 10l512 320q30 17 30 54zM1792 640q0 -96 -1 -150t-8.5 -136.5t-22.5 -147.5q-16 -73 -69 -123t-124 -58q-222 -25 -671 -25t-671 25q-71 8 -124.5 58t-69.5 123 q-14 65 -21.5 147.5t-8.5 136.5t-1 150t1 150t8.5 136.5t22.5 147.5q16 73 69 123t124 58q222 25 671 25t671 -25q71 -8 124.5 -58t69.5 -123q14 -65 21.5 -147.5t8.5 -136.5t1 -150z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M402 829l494 -305l-342 -285l-490 319zM1388 274v-108l-490 -293v-1l-1 1l-1 -1v1l-489 293v108l147 -96l342 284v2l1 -1l1 1v-2l343 -284zM554 1418l342 -285l-494 -304l-338 270zM1390 829l338 -271l-489 -319l-343 285zM1239 1418l489 -319l-338 -270l-494 304z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M928 135v-151l-707 -1v151zM1169 481v-701l-1 -35v-1h-1132l-35 1h-1v736h121v-618h928v618h120zM241 393l704 -65l-13 -150l-705 65zM309 709l683 -183l-39 -146l-683 183zM472 1058l609 -360l-77 -130l-609 360zM832 1389l398 -585l-124 -85l-399 584zM1285 1536 l121 -697l-149 -26l-121 697z" />
|
||||
<glyph unicode="" d="M1362 110v648h-135q20 -63 20 -131q0 -126 -64 -232.5t-174 -168.5t-240 -62q-197 0 -337 135.5t-140 327.5q0 68 20 131h-141v-648q0 -26 17.5 -43.5t43.5 -17.5h1069q25 0 43 17.5t18 43.5zM1078 643q0 124 -90.5 211.5t-218.5 87.5q-127 0 -217.5 -87.5t-90.5 -211.5 t90.5 -211.5t217.5 -87.5q128 0 218.5 87.5t90.5 211.5zM1362 1003v165q0 28 -20 48.5t-49 20.5h-174q-29 0 -49 -20.5t-20 -48.5v-165q0 -29 20 -49t49 -20h174q29 0 49 20t20 49zM1536 1211v-1142q0 -81 -58 -139t-139 -58h-1142q-81 0 -139 58t-58 139v1142q0 81 58 139 t139 58h1142q81 0 139 -58t58 -139z" />
|
||||
<glyph unicode="" d="M1248 1408q119 0 203.5 -84.5t84.5 -203.5v-960q0 -119 -84.5 -203.5t-203.5 -84.5h-960q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960zM698 640q0 88 -62 150t-150 62t-150 -62t-62 -150t62 -150t150 -62t150 62t62 150zM1262 640q0 88 -62 150 t-150 62t-150 -62t-62 -150t62 -150t150 -62t150 62t62 150z" />
|
||||
<glyph unicode="" d="M768 914l201 -306h-402zM1133 384h94l-459 691l-459 -691h94l104 160h522zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M815 677q8 -63 -50.5 -101t-111.5 -6q-39 17 -53.5 58t-0.5 82t52 58q36 18 72.5 12t64 -35.5t27.5 -67.5zM926 698q-14 107 -113 164t-197 13q-63 -28 -100.5 -88.5t-34.5 -129.5q4 -91 77.5 -155t165.5 -56q91 8 152 84t50 168zM1165 1240q-20 27 -56 44.5t-58 22 t-71 12.5q-291 47 -566 -2q-43 -7 -66 -12t-55 -22t-50 -43q30 -28 76 -45.5t73.5 -22t87.5 -11.5q228 -29 448 -1q63 8 89.5 12t72.5 21.5t75 46.5zM1222 205q-8 -26 -15.5 -76.5t-14 -84t-28.5 -70t-58 -56.5q-86 -48 -189.5 -71.5t-202 -22t-201.5 18.5q-46 8 -81.5 18 t-76.5 27t-73 43.5t-52 61.5q-25 96 -57 292l6 16l18 9q223 -148 506.5 -148t507.5 148q21 -6 24 -23t-5 -45t-8 -37zM1403 1166q-26 -167 -111 -655q-5 -30 -27 -56t-43.5 -40t-54.5 -31q-252 -126 -610 -88q-248 27 -394 139q-15 12 -25.5 26.5t-17 35t-9 34t-6 39.5 t-5.5 35q-9 50 -26.5 150t-28 161.5t-23.5 147.5t-22 158q3 26 17.5 48.5t31.5 37.5t45 30t46 22.5t48 18.5q125 46 313 64q379 37 676 -50q155 -46 215 -122q16 -20 16.5 -51t-5.5 -54z" />
|
||||
<glyph unicode="" d="M848 666q0 43 -41 66t-77 1q-43 -20 -42.5 -72.5t43.5 -70.5q39 -23 81 4t36 72zM928 682q8 -66 -36 -121t-110 -61t-119 40t-56 113q-2 49 25.5 93t72.5 64q70 31 141.5 -10t81.5 -118zM1100 1073q-20 -21 -53.5 -34t-53 -16t-63.5 -8q-155 -20 -324 0q-44 6 -63 9.5 t-52.5 16t-54.5 32.5q13 19 36 31t40 15.5t47 8.5q198 35 408 1q33 -5 51 -8.5t43 -16t39 -31.5zM1142 327q0 7 5.5 26.5t3 32t-17.5 16.5q-161 -106 -365 -106t-366 106l-12 -6l-5 -12q26 -154 41 -210q47 -81 204 -108q249 -46 428 53q34 19 49 51.5t22.5 85.5t12.5 71z M1272 1020q9 53 -8 75q-43 55 -155 88q-216 63 -487 36q-132 -12 -226 -46q-38 -15 -59.5 -25t-47 -34t-29.5 -54q8 -68 19 -138t29 -171t24 -137q1 -5 5 -31t7 -36t12 -27t22 -28q105 -80 284 -100q259 -28 440 63q24 13 39.5 23t31 29t19.5 40q48 267 80 473zM1536 1120 v-960q0 -119 -84.5 -203.5t-203.5 -84.5h-960q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M390 1408h219v-388h364v-241h-364v-394q0 -136 14 -172q13 -37 52 -60q50 -31 117 -31q117 0 232 76v-242q-102 -48 -178 -65q-77 -19 -173 -19q-105 0 -186 27q-78 25 -138 75q-58 51 -79 105q-22 54 -22 161v539h-170v217q91 30 155 84q64 55 103 132q39 78 54 196z " />
|
||||
<glyph unicode="" d="M1123 127v181q-88 -56 -174 -56q-51 0 -88 23q-29 17 -39 45q-11 30 -11 129v295h274v181h-274v291h-164q-11 -90 -40 -147t-78 -99q-48 -40 -116 -63v-163h127v-404q0 -78 17 -121q17 -42 59 -78q43 -37 104 -57q62 -20 140 -20q67 0 129 14q57 13 134 49zM1536 1120 v-960q0 -119 -84.5 -203.5t-203.5 -84.5h-960q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" horiz-adv-x="768" d="M765 237q8 -19 -5 -35l-350 -384q-10 -10 -23 -10q-14 0 -24 10l-355 384q-13 16 -5 35q9 19 29 19h224v1248q0 14 9 23t23 9h192q14 0 23 -9t9 -23v-1248h224q21 0 29 -19z" />
|
||||
<glyph unicode="" horiz-adv-x="768" d="M765 1043q-9 -19 -29 -19h-224v-1248q0 -14 -9 -23t-23 -9h-192q-14 0 -23 9t-9 23v1248h-224q-21 0 -29 19t5 35l350 384q10 10 23 10q14 0 24 -10l355 -384q13 -16 5 -35z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1792 736v-192q0 -14 -9 -23t-23 -9h-1248v-224q0 -21 -19 -29t-35 5l-384 350q-10 10 -10 23q0 14 10 24l384 354q16 14 35 6q19 -9 19 -29v-224h1248q14 0 23 -9t9 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1728 643q0 -14 -10 -24l-384 -354q-16 -14 -35 -6q-19 9 -19 29v224h-1248q-14 0 -23 9t-9 23v192q0 14 9 23t23 9h1248v224q0 21 19 29t35 -5l384 -350q10 -10 10 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M1393 321q-39 -125 -123 -250q-129 -196 -257 -196q-49 0 -140 32q-86 32 -151 32q-61 0 -142 -33q-81 -34 -132 -34q-152 0 -301 259q-147 261 -147 503q0 228 113 374q112 144 284 144q72 0 177 -30q104 -30 138 -30q45 0 143 34q102 34 173 34q119 0 213 -65 q52 -36 104 -100q-79 -67 -114 -118q-65 -94 -65 -207q0 -124 69 -223t158 -126zM1017 1494q0 -61 -29 -136q-30 -75 -93 -138q-54 -54 -108 -72q-37 -11 -104 -17q3 149 78 257q74 107 250 148q1 -3 2.5 -11t2.5 -11q0 -4 0.5 -10t0.5 -10z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M682 530v-651l-682 94v557h682zM682 1273v-659h-682v565zM1664 530v-786l-907 125v661h907zM1664 1408v-794h-907v669z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M493 1053q16 0 27.5 11.5t11.5 27.5t-11.5 27.5t-27.5 11.5t-27 -11.5t-11 -27.5t11 -27.5t27 -11.5zM915 1053q16 0 27 11.5t11 27.5t-11 27.5t-27 11.5t-27.5 -11.5t-11.5 -27.5t11.5 -27.5t27.5 -11.5zM103 869q42 0 72 -30t30 -72v-430q0 -43 -29.5 -73t-72.5 -30 t-73 30t-30 73v430q0 42 30 72t73 30zM1163 850v-666q0 -46 -32 -78t-77 -32h-75v-227q0 -43 -30 -73t-73 -30t-73 30t-30 73v227h-138v-227q0 -43 -30 -73t-73 -30q-42 0 -72 30t-30 73l-1 227h-74q-46 0 -78 32t-32 78v666h918zM931 1255q107 -55 171 -153.5t64 -215.5 h-925q0 117 64 215.5t172 153.5l-71 131q-7 13 5 20q13 6 20 -6l72 -132q95 42 201 42t201 -42l72 132q7 12 20 6q12 -7 5 -20zM1408 767v-430q0 -43 -30 -73t-73 -30q-42 0 -72 30t-30 73v430q0 43 30 72.5t72 29.5q43 0 73 -29.5t30 -72.5z" />
|
||||
<glyph unicode="" d="M663 1125q-11 -1 -15.5 -10.5t-8.5 -9.5q-5 -1 -5 5q0 12 19 15h10zM750 1111q-4 -1 -11.5 6.5t-17.5 4.5q24 11 32 -2q3 -6 -3 -9zM399 684q-4 1 -6 -3t-4.5 -12.5t-5.5 -13.5t-10 -13q-7 -10 -1 -12q4 -1 12.5 7t12.5 18q1 3 2 7t2 6t1.5 4.5t0.5 4v3t-1 2.5t-3 2z M1254 325q0 18 -55 42q4 15 7.5 27.5t5 26t3 21.5t0.5 22.5t-1 19.5t-3.5 22t-4 20.5t-5 25t-5.5 26.5q-10 48 -47 103t-72 75q24 -20 57 -83q87 -162 54 -278q-11 -40 -50 -42q-31 -4 -38.5 18.5t-8 83.5t-11.5 107q-9 39 -19.5 69t-19.5 45.5t-15.5 24.5t-13 15t-7.5 7 q-14 62 -31 103t-29.5 56t-23.5 33t-15 40q-4 21 6 53.5t4.5 49.5t-44.5 25q-15 3 -44.5 18t-35.5 16q-8 1 -11 26t8 51t36 27q37 3 51 -30t4 -58q-11 -19 -2 -26.5t30 -0.5q13 4 13 36v37q-5 30 -13.5 50t-21 30.5t-23.5 15t-27 7.5q-107 -8 -89 -134q0 -15 -1 -15 q-9 9 -29.5 10.5t-33 -0.5t-15.5 5q1 57 -16 90t-45 34q-27 1 -41.5 -27.5t-16.5 -59.5q-1 -15 3.5 -37t13 -37.5t15.5 -13.5q10 3 16 14q4 9 -7 8q-7 0 -15.5 14.5t-9.5 33.5q-1 22 9 37t34 14q17 0 27 -21t9.5 -39t-1.5 -22q-22 -15 -31 -29q-8 -12 -27.5 -23.5 t-20.5 -12.5q-13 -14 -15.5 -27t7.5 -18q14 -8 25 -19.5t16 -19t18.5 -13t35.5 -6.5q47 -2 102 15q2 1 23 7t34.5 10.5t29.5 13t21 17.5q9 14 20 8q5 -3 6.5 -8.5t-3 -12t-16.5 -9.5q-20 -6 -56.5 -21.5t-45.5 -19.5q-44 -19 -70 -23q-25 -5 -79 2q-10 2 -9 -2t17 -19 q25 -23 67 -22q17 1 36 7t36 14t33.5 17.5t30 17t24.5 12t17.5 2.5t8.5 -11q0 -2 -1 -4.5t-4 -5t-6 -4.5t-8.5 -5t-9 -4.5t-10 -5t-9.5 -4.5q-28 -14 -67.5 -44t-66.5 -43t-49 -1q-21 11 -63 73q-22 31 -25 22q-1 -3 -1 -10q0 -25 -15 -56.5t-29.5 -55.5t-21 -58t11.5 -63 q-23 -6 -62.5 -90t-47.5 -141q-2 -18 -1.5 -69t-5.5 -59q-8 -24 -29 -3q-32 31 -36 94q-2 28 4 56q4 19 -1 18l-4 -5q-36 -65 10 -166q5 -12 25 -28t24 -20q20 -23 104 -90.5t93 -76.5q16 -15 17.5 -38t-14 -43t-45.5 -23q8 -15 29 -44.5t28 -54t7 -70.5q46 24 7 92 q-4 8 -10.5 16t-9.5 12t-2 6q3 5 13 9.5t20 -2.5q46 -52 166 -36q133 15 177 87q23 38 34 30q12 -6 10 -52q-1 -25 -23 -92q-9 -23 -6 -37.5t24 -15.5q3 19 14.5 77t13.5 90q2 21 -6.5 73.5t-7.5 97t23 70.5q15 18 51 18q1 37 34.5 53t72.5 10.5t60 -22.5zM626 1152 q3 17 -2.5 30t-11.5 15q-9 2 -9 -7q2 -5 5 -6q10 0 7 -15q-3 -20 8 -20q3 0 3 3zM1045 955q-2 8 -6.5 11.5t-13 5t-14.5 5.5q-5 3 -9.5 8t-7 8t-5.5 6.5t-4 4t-4 -1.5q-14 -16 7 -43.5t39 -31.5q9 -1 14.5 8t3.5 20zM867 1168q0 11 -5 19.5t-11 12.5t-9 3q-14 -1 -7 -7l4 -2 q14 -4 18 -31q0 -3 8 2zM921 1401q0 2 -2.5 5t-9 7t-9.5 6q-15 15 -24 15q-9 -1 -11.5 -7.5t-1 -13t-0.5 -12.5q-1 -4 -6 -10.5t-6 -9t3 -8.5q4 -3 8 0t11 9t15 9q1 1 9 1t15 2t9 7zM1486 60q20 -12 31 -24.5t12 -24t-2.5 -22.5t-15.5 -22t-23.5 -19.5t-30 -18.5 t-31.5 -16.5t-32 -15.5t-27 -13q-38 -19 -85.5 -56t-75.5 -64q-17 -16 -68 -19.5t-89 14.5q-18 9 -29.5 23.5t-16.5 25.5t-22 19.5t-47 9.5q-44 1 -130 1q-19 0 -57 -1.5t-58 -2.5q-44 -1 -79.5 -15t-53.5 -30t-43.5 -28.5t-53.5 -11.5q-29 1 -111 31t-146 43q-19 4 -51 9.5 t-50 9t-39.5 9.5t-33.5 14.5t-17 19.5q-10 23 7 66.5t18 54.5q1 16 -4 40t-10 42.5t-4.5 36.5t10.5 27q14 12 57 14t60 12q30 18 42 35t12 51q21 -73 -32 -106q-32 -20 -83 -15q-34 3 -43 -10q-13 -15 5 -57q2 -6 8 -18t8.5 -18t4.5 -17t1 -22q0 -15 -17 -49t-14 -48 q3 -17 37 -26q20 -6 84.5 -18.5t99.5 -20.5q24 -6 74 -22t82.5 -23t55.5 -4q43 6 64.5 28t23 48t-7.5 58.5t-19 52t-20 36.5q-121 190 -169 242q-68 74 -113 40q-11 -9 -15 15q-3 16 -2 38q1 29 10 52t24 47t22 42q8 21 26.5 72t29.5 78t30 61t39 54q110 143 124 195 q-12 112 -16 310q-2 90 24 151.5t106 104.5q39 21 104 21q53 1 106 -13.5t89 -41.5q57 -42 91.5 -121.5t29.5 -147.5q-5 -95 30 -214q34 -113 133 -218q55 -59 99.5 -163t59.5 -191q8 -49 5 -84.5t-12 -55.5t-20 -22q-10 -2 -23.5 -19t-27 -35.5t-40.5 -33.5t-61 -14 q-18 1 -31.5 5t-22.5 13.5t-13.5 15.5t-11.5 20.5t-9 19.5q-22 37 -41 30t-28 -49t7 -97q20 -70 1 -195q-10 -65 18 -100.5t73 -33t85 35.5q59 49 89.5 66.5t103.5 42.5q53 18 77 36.5t18.5 34.5t-25 28.5t-51.5 23.5q-33 11 -49.5 48t-15 72.5t15.5 47.5q1 -31 8 -56.5 t14.5 -40.5t20.5 -28.5t21 -19t21.5 -13t16.5 -9.5z" />
|
||||
<glyph unicode="" d="M1024 36q-42 241 -140 498h-2l-2 -1q-16 -6 -43 -16.5t-101 -49t-137 -82t-131 -114.5t-103 -148l-15 11q184 -150 418 -150q132 0 256 52zM839 643q-21 49 -53 111q-311 -93 -673 -93q-1 -7 -1 -21q0 -124 44 -236.5t124 -201.5q50 89 123.5 166.5t142.5 124.5t130.5 81 t99.5 48l37 13q4 1 13 3.5t13 4.5zM732 855q-120 213 -244 378q-138 -65 -234 -186t-128 -272q302 0 606 80zM1416 536q-210 60 -409 29q87 -239 128 -469q111 75 185 189.5t96 250.5zM611 1277q-1 0 -2 -1q1 1 2 1zM1201 1132q-185 164 -433 164q-76 0 -155 -19 q131 -170 246 -382q69 26 130 60.5t96.5 61.5t65.5 57t37.5 40.5zM1424 647q-3 232 -149 410l-1 -1q-9 -12 -19 -24.5t-43.5 -44.5t-71 -60.5t-100 -65t-131.5 -64.5q25 -53 44 -95q2 -6 6.5 -17.5t7.5 -16.5q36 5 74.5 7t73.5 2t69 -1.5t64 -4t56.5 -5.5t48 -6.5t36.5 -6 t25 -4.5zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M1173 473q0 50 -19.5 91.5t-48.5 68.5t-73 49t-82.5 34t-87.5 23l-104 24q-30 7 -44 10.5t-35 11.5t-30 16t-16.5 21t-7.5 30q0 77 144 77q43 0 77 -12t54 -28.5t38 -33.5t40 -29t48 -12q47 0 75.5 32t28.5 77q0 55 -56 99.5t-142 67.5t-182 23q-68 0 -132 -15.5 t-119.5 -47t-89 -87t-33.5 -128.5q0 -61 19 -106.5t56 -75.5t80 -48.5t103 -32.5l146 -36q90 -22 112 -36q32 -20 32 -60q0 -39 -40 -64.5t-105 -25.5q-51 0 -91.5 16t-65 38.5t-45.5 45t-46 38.5t-54 16q-50 0 -75.5 -30t-25.5 -75q0 -92 122 -157.5t291 -65.5 q73 0 140 18.5t122.5 53.5t88.5 93.5t33 131.5zM1536 256q0 -159 -112.5 -271.5t-271.5 -112.5q-130 0 -234 80q-77 -16 -150 -16q-143 0 -273.5 55.5t-225 150t-150 225t-55.5 273.5q0 73 16 150q-80 104 -80 234q0 159 112.5 271.5t271.5 112.5q130 0 234 -80 q77 16 150 16q143 0 273.5 -55.5t225 -150t150 -225t55.5 -273.5q0 -73 -16 -150q80 -104 80 -234z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1483 512l-587 -587q-52 -53 -127.5 -53t-128.5 53l-587 587q-53 53 -53 128t53 128l587 587q53 53 128 53t128 -53l265 -265l-398 -399l-188 188q-42 42 -99 42q-59 0 -100 -41l-120 -121q-42 -40 -42 -99q0 -58 42 -100l406 -408q30 -28 67 -37l6 -4h28q60 0 99 41 l619 619l2 -3q53 -53 53 -128t-53 -128zM1406 1138l120 -120q14 -15 14 -36t-14 -36l-730 -730q-17 -15 -37 -15v0q-4 0 -6 1q-18 2 -30 14l-407 408q-14 15 -14 36t14 35l121 120q13 15 35 15t36 -15l252 -252l574 575q15 15 36 15t36 -15z" />
|
||||
<glyph unicode="" d="M704 192v1024q0 14 -9 23t-23 9h-480q-14 0 -23 -9t-9 -23v-1024q0 -14 9 -23t23 -9h480q14 0 23 9t9 23zM1376 576v640q0 14 -9 23t-23 9h-480q-14 0 -23 -9t-9 -23v-640q0 -14 9 -23t23 -9h480q14 0 23 9t9 23zM1536 1344v-1408q0 -26 -19 -45t-45 -19h-1408 q-26 0 -45 19t-19 45v1408q0 26 19 45t45 19h1408q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1280" d="M1280 480q0 -40 -28 -68t-68 -28q-51 0 -80 43l-227 341h-45v-132l247 -411q9 -15 9 -33q0 -26 -19 -45t-45 -19h-192v-272q0 -46 -33 -79t-79 -33h-160q-46 0 -79 33t-33 79v272h-192q-26 0 -45 19t-19 45q0 18 9 33l247 411v132h-45l-227 -341q-29 -43 -80 -43 q-40 0 -68 28t-28 68q0 29 16 53l256 384q73 107 176 107h384q103 0 176 -107l256 -384q16 -24 16 -53zM864 1280q0 -93 -65.5 -158.5t-158.5 -65.5t-158.5 65.5t-65.5 158.5t65.5 158.5t158.5 65.5t158.5 -65.5t65.5 -158.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1024" d="M1024 832v-416q0 -40 -28 -68t-68 -28t-68 28t-28 68v352h-64v-912q0 -46 -33 -79t-79 -33t-79 33t-33 79v464h-64v-464q0 -46 -33 -79t-79 -33t-79 33t-33 79v912h-64v-352q0 -40 -28 -68t-68 -28t-68 28t-28 68v416q0 80 56 136t136 56h640q80 0 136 -56t56 -136z M736 1280q0 -93 -65.5 -158.5t-158.5 -65.5t-158.5 65.5t-65.5 158.5t65.5 158.5t158.5 65.5t158.5 -65.5t65.5 -158.5z" />
|
||||
<glyph unicode="" d="M773 234l350 473q16 22 24.5 59t-6 85t-61.5 79q-40 26 -83 25.5t-73.5 -17.5t-54.5 -45q-36 -40 -96 -40q-59 0 -95 40q-24 28 -54.5 45t-73.5 17.5t-84 -25.5q-46 -31 -60.5 -79t-6 -85t24.5 -59zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103 t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1472 640q0 117 -45.5 223.5t-123 184t-184 123t-223.5 45.5t-223.5 -45.5t-184 -123t-123 -184t-45.5 -223.5t45.5 -223.5t123 -184t184 -123t223.5 -45.5t223.5 45.5t184 123t123 184t45.5 223.5zM1748 363q-4 -15 -20 -20l-292 -96v-306q0 -16 -13 -26q-15 -10 -29 -4 l-292 94l-180 -248q-10 -13 -26 -13t-26 13l-180 248l-292 -94q-14 -6 -29 4q-13 10 -13 26v306l-292 96q-16 5 -20 20q-5 17 4 29l180 248l-180 248q-9 13 -4 29q4 15 20 20l292 96v306q0 16 13 26q15 10 29 4l292 -94l180 248q9 12 26 12t26 -12l180 -248l292 94 q14 6 29 -4q13 -10 13 -26v-306l292 -96q16 -5 20 -20q5 -16 -4 -29l-180 -248l180 -248q9 -12 4 -29z" />
|
||||
<glyph unicode="" d="M1262 233q-54 -9 -110 -9q-182 0 -337 90t-245 245t-90 337q0 192 104 357q-201 -60 -328.5 -229t-127.5 -384q0 -130 51 -248.5t136.5 -204t204 -136.5t248.5 -51q144 0 273.5 61.5t220.5 171.5zM1465 318q-94 -203 -283.5 -324.5t-413.5 -121.5q-156 0 -298 61 t-245 164t-164 245t-61 298q0 153 57.5 292.5t156 241.5t235.5 164.5t290 68.5q44 2 61 -39q18 -41 -15 -72q-86 -78 -131.5 -181.5t-45.5 -218.5q0 -148 73 -273t198 -198t273 -73q118 0 228 51q41 18 72 -13q14 -14 17.5 -34t-4.5 -38z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M1088 704q0 26 -19 45t-45 19h-256q-26 0 -45 -19t-19 -45t19 -45t45 -19h256q26 0 45 19t19 45zM1664 896v-960q0 -26 -19 -45t-45 -19h-1408q-26 0 -45 19t-19 45v960q0 26 19 45t45 19h1408q26 0 45 -19t19 -45zM1728 1344v-256q0 -26 -19 -45t-45 -19h-1536 q-26 0 -45 19t-19 45v256q0 26 19 45t45 19h1536q26 0 45 -19t19 -45z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1632 576q0 -26 -19 -45t-45 -19h-224q0 -171 -67 -290l208 -209q19 -19 19 -45t-19 -45q-18 -19 -45 -19t-45 19l-198 197q-5 -5 -15 -13t-42 -28.5t-65 -36.5t-82 -29t-97 -13v896h-128v-896q-51 0 -101.5 13.5t-87 33t-66 39t-43.5 32.5l-15 14l-183 -207 q-20 -21 -48 -21q-24 0 -43 16q-19 18 -20.5 44.5t15.5 46.5l202 227q-58 114 -58 274h-224q-26 0 -45 19t-19 45t19 45t45 19h224v294l-173 173q-19 19 -19 45t19 45t45 19t45 -19l173 -173h844l173 173q19 19 45 19t45 -19t19 -45t-19 -45l-173 -173v-294h224q26 0 45 -19 t19 -45zM1152 1152h-640q0 133 93.5 226.5t226.5 93.5t226.5 -93.5t93.5 -226.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1920" d="M1917 1016q23 -64 -150 -294q-24 -32 -65 -85q-78 -100 -90 -131q-17 -41 14 -81q17 -21 81 -82h1l1 -1l1 -1l2 -2q141 -131 191 -221q3 -5 6.5 -12.5t7 -26.5t-0.5 -34t-25 -27.5t-59 -12.5l-256 -4q-24 -5 -56 5t-52 22l-20 12q-30 21 -70 64t-68.5 77.5t-61 58 t-56.5 15.5q-3 -1 -8 -3.5t-17 -14.5t-21.5 -29.5t-17 -52t-6.5 -77.5q0 -15 -3.5 -27.5t-7.5 -18.5l-4 -5q-18 -19 -53 -22h-115q-71 -4 -146 16.5t-131.5 53t-103 66t-70.5 57.5l-25 24q-10 10 -27.5 30t-71.5 91t-106 151t-122.5 211t-130.5 272q-6 16 -6 27t3 16l4 6 q15 19 57 19l274 2q12 -2 23 -6.5t16 -8.5l5 -3q16 -11 24 -32q20 -50 46 -103.5t41 -81.5l16 -29q29 -60 56 -104t48.5 -68.5t41.5 -38.5t34 -14t27 5q2 1 5 5t12 22t13.5 47t9.5 81t0 125q-2 40 -9 73t-14 46l-6 12q-25 34 -85 43q-13 2 5 24q17 19 38 30q53 26 239 24 q82 -1 135 -13q20 -5 33.5 -13.5t20.5 -24t10.5 -32t3.5 -45.5t-1 -55t-2.5 -70.5t-1.5 -82.5q0 -11 -1 -42t-0.5 -48t3.5 -40.5t11.5 -39t22.5 -24.5q8 -2 17 -4t26 11t38 34.5t52 67t68 107.5q60 104 107 225q4 10 10 17.5t11 10.5l4 3l5 2.5t13 3t20 0.5l288 2 q39 5 64 -2.5t31 -16.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" d="M675 252q21 34 11 69t-45 50q-34 14 -73 1t-60 -46q-22 -34 -13 -68.5t43 -50.5t74.5 -2.5t62.5 47.5zM769 373q8 13 3.5 26.5t-17.5 18.5q-14 5 -28.5 -0.5t-21.5 -18.5q-17 -31 13 -45q14 -5 29 0.5t22 18.5zM943 266q-45 -102 -158 -150t-224 -12 q-107 34 -147.5 126.5t6.5 187.5q47 93 151.5 139t210.5 19q111 -29 158.5 -119.5t2.5 -190.5zM1255 426q-9 96 -89 170t-208.5 109t-274.5 21q-223 -23 -369.5 -141.5t-132.5 -264.5q9 -96 89 -170t208.5 -109t274.5 -21q223 23 369.5 141.5t132.5 264.5zM1563 422 q0 -68 -37 -139.5t-109 -137t-168.5 -117.5t-226 -83t-270.5 -31t-275 33.5t-240.5 93t-171.5 151t-65 199.5q0 115 69.5 245t197.5 258q169 169 341.5 236t246.5 -7q65 -64 20 -209q-4 -14 -1 -20t10 -7t14.5 0.5t13.5 3.5l6 2q139 59 246 59t153 -61q45 -63 0 -178 q-2 -13 -4.5 -20t4.5 -12.5t12 -7.5t17 -6q57 -18 103 -47t80 -81.5t34 -116.5zM1489 1046q42 -47 54.5 -108.5t-6.5 -117.5q-8 -23 -29.5 -34t-44.5 -4q-23 8 -34 29.5t-4 44.5q20 63 -24 111t-107 35q-24 -5 -45 8t-25 37q-5 24 8 44.5t37 25.5q60 13 119 -5.5t101 -65.5z M1670 1209q87 -96 112.5 -222.5t-13.5 -241.5q-9 -27 -34 -40t-52 -4t-40 34t-5 52q28 82 10 172t-80 158q-62 69 -148 95.5t-173 8.5q-28 -6 -52 9.5t-30 43.5t9.5 51.5t43.5 29.5q123 26 244 -11.5t208 -134.5z" />
|
||||
<glyph unicode="" d="M1133 -34q-171 -94 -368 -94q-196 0 -367 94q138 87 235.5 211t131.5 268q35 -144 132.5 -268t235.5 -211zM638 1394v-485q0 -252 -126.5 -459.5t-330.5 -306.5q-181 215 -181 495q0 187 83.5 349.5t229.5 269.5t325 137zM1536 638q0 -280 -181 -495 q-204 99 -330.5 306.5t-126.5 459.5v485q179 -30 325 -137t229.5 -269.5t83.5 -349.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M1402 433q-32 -80 -76 -138t-91 -88.5t-99 -46.5t-101.5 -14.5t-96.5 8.5t-86.5 22t-69.5 27.5t-46 22.5l-17 10q-113 -228 -289.5 -359.5t-384.5 -132.5q-19 0 -32 13t-13 32t13 31.5t32 12.5q173 1 322.5 107.5t251.5 294.5q-36 -14 -72 -23t-83 -13t-91 2.5t-93 28.5 t-92 59t-84.5 100t-74.5 146q114 47 214 57t167.5 -7.5t124.5 -56.5t88.5 -77t56.5 -82q53 131 79 291q-7 -1 -18 -2.5t-46.5 -2.5t-69.5 0.5t-81.5 10t-88.5 23t-84 42.5t-75 65t-54.5 94.5t-28.5 127.5q70 28 133.5 36.5t112.5 -1t92 -30t73.5 -50t56 -61t42 -63t27.5 -56 t16 -39.5l4 -16q12 122 12 195q-8 6 -21.5 16t-49 44.5t-63.5 71.5t-54 93t-33 112.5t12 127t70 138.5q73 -25 127.5 -61.5t84.5 -76.5t48 -85t20.5 -89t-0.5 -85.5t-13 -76.5t-19 -62t-17 -42l-7 -15q1 -5 1 -50.5t-1 -71.5q3 7 10 18.5t30.5 43t50.5 58t71 55.5t91.5 44.5 t112 14.5t132.5 -24q-2 -78 -21.5 -141.5t-50 -104.5t-69.5 -71.5t-81.5 -45.5t-84.5 -24t-80 -9.5t-67.5 1t-46.5 4.5l-17 3q-23 -147 -73 -283q6 7 18 18.5t49.5 41t77.5 52.5t99.5 42t117.5 20t129 -23.5t137 -77.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1280" d="M1259 283v-66q0 -85 -57.5 -144.5t-138.5 -59.5h-57l-260 -269v269h-529q-81 0 -138.5 59.5t-57.5 144.5v66h1238zM1259 609v-255h-1238v255h1238zM1259 937v-255h-1238v255h1238zM1259 1077v-67h-1238v67q0 84 57.5 143.5t138.5 59.5h846q81 0 138.5 -59.5t57.5 -143.5z " />
|
||||
<glyph unicode="" d="M1152 640q0 -14 -9 -23l-320 -320q-9 -9 -23 -9q-13 0 -22.5 9.5t-9.5 22.5v192h-352q-13 0 -22.5 9.5t-9.5 22.5v192q0 13 9.5 22.5t22.5 9.5h352v192q0 14 9 23t23 9q12 0 24 -10l319 -319q9 -9 9 -23zM1312 640q0 148 -73 273t-198 198t-273 73t-273 -73t-198 -198 t-73 -273t73 -273t198 -198t273 -73t273 73t198 198t73 273zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M1152 736v-192q0 -13 -9.5 -22.5t-22.5 -9.5h-352v-192q0 -14 -9 -23t-23 -9q-12 0 -24 10l-319 319q-9 9 -9 23t9 23l320 320q9 9 23 9q13 0 22.5 -9.5t9.5 -22.5v-192h352q13 0 22.5 -9.5t9.5 -22.5zM1312 640q0 148 -73 273t-198 198t-273 73t-273 -73t-198 -198 t-73 -273t73 -273t198 -198t273 -73t273 73t198 198t73 273zM1536 640q0 -209 -103 -385.5t-279.5 -279.5t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" d="M1024 960v-640q0 -26 -19 -45t-45 -19q-20 0 -37 12l-448 320q-27 19 -27 52t27 52l448 320q17 12 37 12q26 0 45 -19t19 -45zM1280 160v960q0 13 -9.5 22.5t-22.5 9.5h-960q-13 0 -22.5 -9.5t-9.5 -22.5v-960q0 -13 9.5 -22.5t22.5 -9.5h960q13 0 22.5 9.5t9.5 22.5z M1536 1120v-960q0 -119 -84.5 -203.5t-203.5 -84.5h-960q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" d="M1024 640q0 -106 -75 -181t-181 -75t-181 75t-75 181t75 181t181 75t181 -75t75 -181zM768 1184q-148 0 -273 -73t-198 -198t-73 -273t73 -273t198 -198t273 -73t273 73t198 198t73 273t-73 273t-198 198t-273 73zM1536 640q0 -209 -103 -385.5t-279.5 -279.5 t-385.5 -103t-385.5 103t-279.5 279.5t-103 385.5t103 385.5t279.5 279.5t385.5 103t385.5 -103t279.5 -279.5t103 -385.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1664" d="M1023 349l102 -204q-58 -179 -210 -290t-339 -111q-156 0 -288.5 77.5t-210 210t-77.5 288.5q0 181 104.5 330t274.5 211l17 -131q-122 -54 -195 -165.5t-73 -244.5q0 -185 131.5 -316.5t316.5 -131.5q126 0 232.5 65t165 175.5t49.5 236.5zM1571 249l58 -114l-256 -128 q-13 -7 -29 -7q-40 0 -57 35l-239 477h-472q-24 0 -42.5 16.5t-21.5 40.5l-96 779q-2 16 6 42q14 51 57 82.5t97 31.5q66 0 113 -47t47 -113q0 -69 -52 -117.5t-120 -41.5l37 -289h423v-128h-407l16 -128h455q40 0 57 -35l228 -455z" />
|
||||
<glyph unicode="" d="M1254 899q16 85 -21 132q-52 65 -187 45q-17 -3 -41 -12.5t-57.5 -30.5t-64.5 -48.5t-59.5 -70t-44.5 -91.5q80 7 113.5 -16t26.5 -99q-5 -52 -52 -143q-43 -78 -71 -99q-44 -32 -87 14q-23 24 -37.5 64.5t-19 73t-10 84t-8.5 71.5q-23 129 -34 164q-12 37 -35.5 69 t-50.5 40q-57 16 -127 -25q-54 -32 -136.5 -106t-122.5 -102v-7q16 -8 25.5 -26t21.5 -20q21 -3 54.5 8.5t58 10.5t41.5 -30q11 -18 18.5 -38.5t15 -48t12.5 -40.5q17 -46 53 -187q36 -146 57 -197q42 -99 103 -125q43 -12 85 -1.5t76 31.5q131 77 250 237 q104 139 172.5 292.5t82.5 226.5zM1536 1120v-960q0 -119 -84.5 -203.5t-203.5 -84.5h-960q-119 0 -203.5 84.5t-84.5 203.5v960q0 119 84.5 203.5t203.5 84.5h960q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1152" d="M1152 704q0 -191 -94.5 -353t-256.5 -256.5t-353 -94.5h-160q-14 0 -23 9t-9 23v611l-215 -66q-3 -1 -9 -1q-10 0 -19 6q-13 10 -13 26v128q0 23 23 31l233 71v93l-215 -66q-3 -1 -9 -1q-10 0 -19 6q-13 10 -13 26v128q0 23 23 31l233 71v250q0 14 9 23t23 9h160 q14 0 23 -9t9 -23v-181l375 116q15 5 28 -5t13 -26v-128q0 -23 -23 -31l-393 -121v-93l375 116q15 5 28 -5t13 -26v-128q0 -23 -23 -31l-393 -121v-487q188 13 318 151t130 328q0 14 9 23t23 9h160q14 0 23 -9t9 -23z" />
|
||||
<glyph unicode="" horiz-adv-x="1408" d="M1152 736v-64q0 -14 -9 -23t-23 -9h-352v-352q0 -14 -9 -23t-23 -9h-64q-14 0 -23 9t-9 23v352h-352q-14 0 -23 9t-9 23v64q0 14 9 23t23 9h352v352q0 14 9 23t23 9h64q14 0 23 -9t9 -23v-352h352q14 0 23 -9t9 -23zM1280 288v832q0 66 -47 113t-113 47h-832 q-66 0 -113 -47t-47 -113v-832q0 -66 47 -113t113 -47h832q66 0 113 47t47 113zM1408 1120v-832q0 -119 -84.5 -203.5t-203.5 -84.5h-832q-119 0 -203.5 84.5t-84.5 203.5v832q0 119 84.5 203.5t203.5 84.5h832q119 0 203.5 -84.5t84.5 -203.5z" />
|
||||
<glyph unicode="" horiz-adv-x="1792" />
|
||||
<glyph unicode="" horiz-adv-x="1792" />
|
||||
<glyph unicode="" horiz-adv-x="1792" />
|
||||
<glyph unicode="" horiz-adv-x="1792" />
|
||||
<glyph unicode="" horiz-adv-x="1792" />
|
||||
<glyph unicode="" horiz-adv-x="1792" />
|
||||
<glyph unicode="" horiz-adv-x="1792" />
|
||||
<glyph unicode="" horiz-adv-x="1792" />
|
||||
<glyph unicode="" horiz-adv-x="1792" />
|
||||
</font>
|
||||
</defs></svg>
|
||||
|
After Width: | Height: | Size: 197 KiB |
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,47 @@
|
|||
$( document ).ready(function() {
|
||||
// Shift nav in mobile when clicking the menu.
|
||||
$(document).on('click', "[data-toggle='wy-nav-top']", function() {
|
||||
$("[data-toggle='wy-nav-shift']").toggleClass("shift");
|
||||
$("[data-toggle='rst-versions']").toggleClass("shift");
|
||||
});
|
||||
// Close menu when you click a link.
|
||||
$(document).on('click', ".wy-menu-vertical .current ul li a", function() {
|
||||
$("[data-toggle='wy-nav-shift']").removeClass("shift");
|
||||
$("[data-toggle='rst-versions']").toggleClass("shift");
|
||||
});
|
||||
$(document).on('click', "[data-toggle='rst-current-version']", function() {
|
||||
$("[data-toggle='rst-versions']").toggleClass("shift-up");
|
||||
});
|
||||
// Make tables responsive
|
||||
$("table.docutils:not(.field-list)").wrap("<div class='wy-table-responsive'></div>");
|
||||
});
|
||||
|
||||
window.SphinxRtdTheme = (function (jquery) {
|
||||
var stickyNav = (function () {
|
||||
var navBar,
|
||||
win,
|
||||
stickyNavCssClass = 'stickynav',
|
||||
applyStickNav = function () {
|
||||
if (navBar.height() <= win.height()) {
|
||||
navBar.addClass(stickyNavCssClass);
|
||||
} else {
|
||||
navBar.removeClass(stickyNavCssClass);
|
||||
}
|
||||
},
|
||||
enable = function () {
|
||||
applyStickNav();
|
||||
win.on('resize', applyStickNav);
|
||||
},
|
||||
init = function () {
|
||||
navBar = jquery('nav.wy-nav-side:first');
|
||||
win = jquery(window);
|
||||
};
|
||||
jquery(init);
|
||||
return {
|
||||
enable : enable
|
||||
};
|
||||
}());
|
||||
return {
|
||||
StickyNav : stickyNav
|
||||
};
|
||||
}($));
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
[theme]
|
||||
inherit = basic
|
||||
stylesheet = css/theme.css
|
||||
|
||||
[options]
|
||||
typekit_id = hiw1hhg
|
||||
analytics_id =
|
||||
sticky_navigation = True
|
||||
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
{% if READTHEDOCS %}
|
||||
{# Add rst-badge after rst-versions for small badge style. #}
|
||||
<div class="rst-versions" data-toggle="rst-versions" role="note" aria-label="versions">
|
||||
<span class="rst-current-version" data-toggle="rst-current-version">
|
||||
<span class="fa fa-book"> Read the Docs</span>
|
||||
v: {{ current_version }}
|
||||
<span class="fa fa-caret-down"></span>
|
||||
</span>
|
||||
<div class="rst-other-versions">
|
||||
<dl>
|
||||
<dt>Versions</dt>
|
||||
{% for slug, url in versions %}
|
||||
<dd><a href="{{ url }}">{{ slug }}</a></dd>
|
||||
{% endfor %}
|
||||
</dl>
|
||||
<dl>
|
||||
<dt>Downloads</dt>
|
||||
{% for type, url in downloads %}
|
||||
<dd><a href="{{ url }}">{{ type }}</a></dd>
|
||||
{% endfor %}
|
||||
</dl>
|
||||
<dl>
|
||||
<dt>On Read the Docs</dt>
|
||||
<dd>
|
||||
<a href="//{{ PRODUCTION_DOMAIN }}/projects/{{ slug }}/?fromdocs={{ slug }}">Project Home</a>
|
||||
</dd>
|
||||
<dd>
|
||||
<a href="//{{ PRODUCTION_DOMAIN }}/builds/{{ slug }}/?fromdocs={{ slug }}">Builds</a>
|
||||
</dd>
|
||||
</dl>
|
||||
<hr/>
|
||||
Free document hosting provided by <a href="http://www.readthedocs.org">Read the Docs</a>.
|
||||
|
||||
</div>
|
||||
</div>
|
||||
{% endif %}
|
||||
|
||||
|
|
@ -0,0 +1,402 @@
|
|||
# -*- coding: utf-8 -*-
|
||||
#
|
||||
# LiteSATA documentation build configuration file, created by
|
||||
# sphinx-quickstart on Tue Jul 01 09:20:29 2014.
|
||||
#
|
||||
# This file is execfile()d with the current directory set to its
|
||||
# containing dir.
|
||||
#
|
||||
# Note that not all possible configuration values are present in this
|
||||
# autogenerated file.
|
||||
#
|
||||
# All configuration values have a default; values that are commented out
|
||||
# serve to show the default.
|
||||
|
||||
import sys
|
||||
import os
|
||||
|
||||
|
||||
# At the top. #HamishW https://pypi.python.org/pypi/sphinx-bootstrap-theme/ ...
|
||||
#import sphinx_bootstrap_theme
|
||||
|
||||
|
||||
# At the top. #HamishW http://sphinx-better-theme.readthedocs.org/en/latest/installation.html easy_install sphinx_better_theme
|
||||
#from better import better_theme_path
|
||||
#html_theme_path = [better_theme_path]
|
||||
|
||||
|
||||
# At the top. #HamishW https://github.com/snide/sphinx_rtd_theme easy_install sphinx_rtd_theme
|
||||
#import sphinx_rtd_theme
|
||||
#html_theme_path = [sphinx_rtd_theme.get_html_theme_path()]
|
||||
|
||||
html_theme_path = ['_themes',]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
# If extensions (or modules to document with autodoc) are in another directory,
|
||||
# add these directories to sys.path here. If the directory is relative to the
|
||||
# documentation root, use os.path.abspath to make it absolute, like shown here.
|
||||
#sys.path.insert(0, os.path.abspath('.'))
|
||||
|
||||
|
||||
# -- General configuration ------------------------------------------------
|
||||
|
||||
# If your documentation needs a minimal Sphinx version, state it here.
|
||||
#needs_sphinx = '1.0'
|
||||
|
||||
# Add any Sphinx extension module names here, as strings. They can be
|
||||
# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
|
||||
# ones.
|
||||
extensions = [
|
||||
'sphinx.ext.autodoc',
|
||||
'sphinx.ext.doctest',
|
||||
'sphinx.ext.intersphinx',
|
||||
'sphinx.ext.todo',
|
||||
'sphinx.ext.coverage',
|
||||
'sphinx.ext.ifconfig',
|
||||
'sphinx.ext.viewcode',
|
||||
# 'breathe', #added by HamishW
|
||||
]
|
||||
|
||||
|
||||
#Build "Todo" notes into the source
|
||||
#todo_include_todos = 'True'
|
||||
|
||||
# Add any paths that contain templates here, relative to this directory.
|
||||
templates_path = ['_templates']
|
||||
|
||||
# The suffix of source filenames.
|
||||
source_suffix = '.rst'
|
||||
|
||||
# The encoding of source files.
|
||||
#source_encoding = 'utf-8-sig'
|
||||
|
||||
# The master toctree document.
|
||||
master_doc = 'index'
|
||||
|
||||
# General information about the project.
|
||||
project = u'LiteSATA'
|
||||
copyright = u'2015, '
|
||||
# Note, theme was modified to allow this to display (fix breaks the translation code, which was breaking the above link and rendering it as text).
|
||||
# Also so I could link to specific copyright page.
|
||||
|
||||
|
||||
# The version info for the project you're documenting, acts as replacement for
|
||||
# |version| and |release|, also used in various other places throughout the
|
||||
# built documents.
|
||||
#
|
||||
|
||||
litesata_version = open(os.path.abspath(os.path.join(os.path.dirname(os.path.dirname(os.path.dirname(__file__))), 'litesata-version.txt'))).read().strip()
|
||||
|
||||
# The short X.Y version.
|
||||
version = litesata_version[:litesata_version.rindex('.')]
|
||||
# The full version, including alpha/beta/rc tags.
|
||||
release = litesata_version
|
||||
|
||||
# The language for content autogenerated by Sphinx. Refer to documentation
|
||||
# for a list of supported languages.
|
||||
#language = None
|
||||
|
||||
# There are two options for replacing |today|: either, you set today to some
|
||||
# non-false value, then it is used:
|
||||
#today = ''
|
||||
# Else, today_fmt is used as the format for a strftime call.
|
||||
#today_fmt = '%B %d, %Y'
|
||||
|
||||
# List of patterns, relative to source directory, that match files and
|
||||
# directories to ignore when looking for source files.
|
||||
exclude_patterns = []
|
||||
|
||||
# The reST default role (used for this markup: `text`) to use for all
|
||||
# documents.
|
||||
#default_role = None
|
||||
|
||||
# If true, '()' will be appended to :func: etc. cross-reference text.
|
||||
#add_function_parentheses = True
|
||||
|
||||
# If true, the current module name will be prepended to all description
|
||||
# unit titles (such as .. function::).
|
||||
#add_module_names = True
|
||||
|
||||
# If true, sectionauthor and moduleauthor directives will be shown in the
|
||||
# output. They are ignored by default.
|
||||
#show_authors = False
|
||||
|
||||
# The name of the Pygments (syntax highlighting) style to use.
|
||||
pygments_style = 'sphinx'
|
||||
|
||||
# A list of ignored prefixes for module index sorting.
|
||||
#modindex_common_prefix = []
|
||||
|
||||
# If true, keep warnings as "system message" paragraphs in the built documents.
|
||||
#keep_warnings = False
|
||||
|
||||
|
||||
# -- Options for HTML output ----------------------------------------------
|
||||
|
||||
# The theme to use for HTML and HTML Help pages. See the documentation for
|
||||
# a list of builtin themes.
|
||||
#html_theme = 'default'
|
||||
#html_theme = 'sphinxdoc'
|
||||
#html_theme = 'agogo' #like this
|
||||
#html_theme = 'scrolls'
|
||||
#html_theme = 'bootstrap'
|
||||
#html_theme_path = sphinx_bootstrap_theme.get_html_theme_path()
|
||||
#html_theme = 'better'
|
||||
#html_theme = 'pyramid'
|
||||
#html_theme = 'nature'
|
||||
#html_theme = 'haiku'
|
||||
#html_theme = "sphinx_rtd_theme"
|
||||
html_theme = "enjoydigital_sphinx_rtd_theme"
|
||||
|
||||
# Theme options are theme-specific and customize the look and feel of a theme
|
||||
# further. For a list of options available for each theme, see the
|
||||
# documentation.
|
||||
#html_theme_options = {
|
||||
# "rightsidebar": "true",
|
||||
# "relbarbgcolor": "black"
|
||||
#}
|
||||
|
||||
|
||||
# Add any paths that contain custom themes here, relative to this directory.
|
||||
#html_theme_path = []
|
||||
|
||||
# The name for this set of Sphinx documents. If None, it defaults to
|
||||
# "<project> v<release> documentation".
|
||||
#html_title = None
|
||||
|
||||
# A shorter title for the navigation bar. Default is the same as html_title.
|
||||
#html_short_title = None
|
||||
|
||||
# The name of an image file (relative to this directory) to place at the top
|
||||
# of the sidebar.
|
||||
html_logo = '_static/LiteSATA_logo_full.png'
|
||||
|
||||
|
||||
# The name of an image file (within the static path) to use as favicon of the
|
||||
# docs. This file should be a Windows icon file (.ico) being 16x16 or 32x32
|
||||
# pixels large.
|
||||
html_favicon = 'litesata.ico'
|
||||
|
||||
# Add any paths that contain custom static files (such as style sheets) here,
|
||||
# relative to this directory. They are copied after the builtin static files,
|
||||
# so a file named "default.css" will overwrite the builtin "default.css".
|
||||
html_static_path = ['_static']
|
||||
|
||||
# Add any extra paths that contain custom files (such as robots.txt or
|
||||
# .htaccess) here, relative to this directory. These files are copied
|
||||
# directly to the root of the documentation.
|
||||
#html_extra_path = []
|
||||
|
||||
# If not '', a 'Last updated on:' timestamp is inserted at every page bottom,
|
||||
# using the given strftime format.
|
||||
#html_last_updated_fmt = '%b %d, %Y'
|
||||
|
||||
# If true, SmartyPants will be used to convert quotes and dashes to
|
||||
# typographically correct entities.
|
||||
#html_use_smartypants = True
|
||||
|
||||
# Custom sidebar templates, maps document names to template names.
|
||||
#html_sidebars = {}
|
||||
|
||||
# Additional templates that should be rendered to pages, maps page names to
|
||||
# template names.
|
||||
#html_additional_pages = {}
|
||||
|
||||
# If false, no module index is generated.
|
||||
#html_domain_indices = True
|
||||
|
||||
# If false, no index is generated.
|
||||
#html_use_index = True
|
||||
|
||||
# If true, the index is split into individual pages for each letter.
|
||||
#html_split_index = False
|
||||
|
||||
# If true, links to the reST sources are added to the pages.
|
||||
#html_show_sourcelink = True
|
||||
|
||||
# If true, "Created using Sphinx" is shown in the HTML footer. Default is True.
|
||||
#html_show_sphinx = True
|
||||
|
||||
# If true, "(C) Copyright ..." is shown in the HTML footer. Default is True.
|
||||
#html_show_copyright = True
|
||||
|
||||
# If true, an OpenSearch description file will be output, and all pages will
|
||||
# contain a <link> tag referring to it. The value of this option must be the
|
||||
# base URL from which the finished HTML is served.
|
||||
#html_use_opensearch = ''
|
||||
|
||||
# This is the file name suffix for HTML files (e.g. ".xhtml").
|
||||
#html_file_suffix = None
|
||||
|
||||
# Output file base name for HTML help builder.
|
||||
htmlhelp_basename = 'LiteSATAdoc'
|
||||
|
||||
|
||||
# -- Options for LaTeX output ---------------------------------------------
|
||||
|
||||
latex_elements = {
|
||||
# The paper size ('letterpaper' or 'a4paper').
|
||||
#'papersize': 'letterpaper',
|
||||
|
||||
# The font size ('10pt', '11pt' or '12pt').
|
||||
#'pointsize': '10pt',
|
||||
|
||||
# Additional stuff for the LaTeX preamble.
|
||||
#'preamble': '',
|
||||
}
|
||||
|
||||
# Grouping the document tree into LaTeX files. List of tuples
|
||||
# (source start file, target name, title,
|
||||
# author, documentclass [howto, manual, or own class]).
|
||||
latex_documents = [
|
||||
('index', 'LiteSATA.tex', u'LiteSATA Documentation',
|
||||
u'Kermarrec Florent', 'manual'),
|
||||
]
|
||||
|
||||
# The name of an image file (relative to this directory) to place at the top of
|
||||
# the title page.
|
||||
#latex_logo = None
|
||||
|
||||
# For "manual" documents, if this is true, then toplevel headings are parts,
|
||||
# not chapters.
|
||||
#latex_use_parts = False
|
||||
|
||||
# If true, show page references after internal links.
|
||||
#latex_show_pagerefs = False
|
||||
|
||||
# If true, show URL addresses after external links.
|
||||
#latex_show_urls = False
|
||||
|
||||
# Documents to append as an appendix to all manuals.
|
||||
#latex_appendices = []
|
||||
|
||||
# If false, no module index is generated.
|
||||
#latex_domain_indices = True
|
||||
|
||||
|
||||
# -- Options for manual page output ---------------------------------------
|
||||
|
||||
# One entry per manual page. List of tuples
|
||||
# (source start file, name, description, authors, manual section).
|
||||
man_pages = [
|
||||
('index', 'litesata', u'LiteSATA Documentation',
|
||||
[u'Florent Kermarrec'], 1)
|
||||
]
|
||||
|
||||
# If true, show URL addresses after external links.
|
||||
#man_show_urls = False
|
||||
|
||||
|
||||
# -- Options for Texinfo output -------------------------------------------
|
||||
|
||||
# Grouping the document tree into Texinfo files. List of tuples
|
||||
# (source start file, target name, title, author,
|
||||
# dir menu entry, description, category)
|
||||
texinfo_documents = [
|
||||
('index', 'LiteSATA', u'LiteSATA Documentation',
|
||||
u'Florent Kermarrec', 'LiteSATA', 'One line description of project.',
|
||||
'Miscellaneous'),
|
||||
]
|
||||
|
||||
# Documents to append as an appendix to all manuals.
|
||||
#texinfo_appendices = []
|
||||
|
||||
# If false, no module index is generated.
|
||||
#texinfo_domain_indices = True
|
||||
|
||||
# How to display URL addresses: 'footnote', 'no', or 'inline'.
|
||||
#texinfo_show_urls = 'footnote'
|
||||
|
||||
# If true, do not generate a @detailmenu in the "Top" node's menu.
|
||||
#texinfo_no_detailmenu = False
|
||||
|
||||
|
||||
# -- Options for Epub output ----------------------------------------------
|
||||
|
||||
# Bibliographic Dublin Core info.
|
||||
epub_title = u'LiteSATA'
|
||||
epub_author = u'Florent Kermarrec'
|
||||
epub_publisher = u'Florent Kermarrec'
|
||||
epub_copyright = u'2015, LiteSATA Contributors'
|
||||
|
||||
# The basename for the epub file. It defaults to the project name.
|
||||
#epub_basename = u'LiteSATA'
|
||||
|
||||
# The HTML theme for the epub output. Since the default themes are not optimized
|
||||
# for small screen space, using the same theme for HTML and epub output is
|
||||
# usually not wise. This defaults to 'epub', a theme designed to save visual
|
||||
# space.
|
||||
#epub_theme = 'epub'
|
||||
|
||||
# The language of the text. It defaults to the language option
|
||||
# or en if the language is not set.
|
||||
#epub_language = ''
|
||||
|
||||
# The scheme of the identifier. Typical schemes are ISBN or URL.
|
||||
#epub_scheme = ''
|
||||
|
||||
# The unique identifier of the text. This can be a ISBN number
|
||||
# or the project homepage.
|
||||
#epub_identifier = ''
|
||||
|
||||
# A unique identification for the text.
|
||||
#epub_uid = ''
|
||||
|
||||
# A tuple containing the cover image and cover page html template filenames.
|
||||
#epub_cover = ()
|
||||
|
||||
# A sequence of (type, uri, title) tuples for the guide element of content.opf.
|
||||
#epub_guide = ()
|
||||
|
||||
# HTML files that should be inserted before the pages created by sphinx.
|
||||
# The format is a list of tuples containing the path and title.
|
||||
#epub_pre_files = []
|
||||
|
||||
# HTML files shat should be inserted after the pages created by sphinx.
|
||||
# The format is a list of tuples containing the path and title.
|
||||
#epub_post_files = []
|
||||
|
||||
# A list of files that should not be packed into the epub file.
|
||||
epub_exclude_files = ['search.html']
|
||||
|
||||
# The depth of the table of contents in toc.ncx.
|
||||
#epub_tocdepth = 3
|
||||
|
||||
# Allow duplicate toc entries.
|
||||
#epub_tocdup = True
|
||||
|
||||
# Choose between 'default' and 'includehidden'.
|
||||
#epub_tocscope = 'default'
|
||||
|
||||
# Fix unsupported image types using the PIL.
|
||||
#epub_fix_images = False
|
||||
|
||||
# Scale large images.
|
||||
#epub_max_image_width = 0
|
||||
|
||||
# How to display URL addresses: 'footnote', 'no', or 'inline'.
|
||||
#epub_show_urls = 'inline'
|
||||
|
||||
# If false, no index is generated.
|
||||
#epub_use_index = True
|
||||
|
||||
|
||||
# Example configuration for intersphinx: refer to the Python standard library.
|
||||
intersphinx_mapping = {'http://docs.python.org/': None}
|
||||
|
||||
# HamishW - set highlighting language.
|
||||
highlight_language = 'cpp'
|
||||
|
||||
# HamishW - set domain (cpp)
|
||||
primary_domain = 'cpp'
|
||||
|
||||
# HamishW - tell Breathe about projects. Breathe is tool to convert Doxygen to Python objects, for import into Sphinx.
|
||||
#breathe_projects = { "myproject": "/home/me/docproj/doxyxml/", "nutshell":"./headers/xml/", }
|
||||
# HamishW - Specify a default project:
|
||||
#breathe_default_project = "nutshell"
|
||||
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
.. _core-index:
|
||||
|
||||
========================
|
||||
Core
|
||||
========================
|
||||
.. note::
|
||||
Please contribute to this document, or support us financially to write it.
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
.. _frontend-index:
|
||||
|
||||
========================
|
||||
Frontend
|
||||
========================
|
||||
.. note::
|
||||
Please contribute to this document, or support us financially to write it.
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
.. _FAQ:
|
||||
|
||||
===
|
||||
FAQ
|
||||
===
|
||||
.. note::
|
||||
Please contribute to this document.
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
.. _bug-reports:
|
||||
|
||||
=============
|
||||
Bug Reporting
|
||||
=============
|
||||
- send us feedback and suggestions for improvements
|
||||
- send us bug reports when something goes wrong
|
||||
- send us the modifications and improvements you have done to LiteSATA.
|
||||
The use of "git format-patch" is recommended. If your submission is large and
|
||||
complex and/or you are not sure how to proceed, feel free to discuss with us
|
||||
about it.
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
.. _sdk-download-and-install:
|
||||
|
||||
====================
|
||||
Download and install
|
||||
====================
|
||||
1. Install Python3 and your vendor's software
|
||||
|
||||
2. Obtain Migen and install it:
|
||||
- git clone https://github.com/m-labs/migen
|
||||
- cd migen
|
||||
- python3 setup.py install
|
||||
- cd ..
|
||||
|
||||
.. note::
|
||||
In case you have issues with Migen, please retry with our fork at:
|
||||
https://github.com/enjoy-digital/migen
|
||||
until new features are merged.
|
||||
|
||||
3. Obtain LiteScope and install it:
|
||||
- git clone https://github.com/enjoy-digital/litescope
|
||||
- cd litescope
|
||||
- python3 setup.py install
|
||||
- cd ..
|
||||
|
||||
4. Obtain LiteSATA
|
||||
- git clone https://github.com/enjoy-digital/litesata
|
||||
|
||||
5. Build and load BIST design (only for KC705 for now):
|
||||
- python3 make.py all
|
||||
|
||||
6. Test design (only for KC705 for now):
|
||||
- go to ./test directory and run:
|
||||
- python3 bist.py
|
||||
|
||||
7. Visualize Link Layer transactions (if BISTSoCDevel):
|
||||
- go to ./test directory and run:
|
||||
- python3 test_la.py [your_cond]
|
||||
- your_cond can be wr_cmd, id_cmd, rd_resp, ...
|
||||
(open test_la.py to see all conditions or add yours)
|
||||
|
||||
8. If you only want to build the core and use it with your
|
||||
regular design flow:
|
||||
- python3 make.py -t core build-core
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
.. _getting-started-index:
|
||||
|
||||
===============
|
||||
Getting Started
|
||||
===============
|
||||
|
||||
Now you know why LiteSATA is :ref:`core for you <about>`, it's time to *get started*.
|
||||
|
||||
This section provides a walk-through of :ref:`downloading and installing the tools`.
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
|
||||
downloads
|
||||
FAQ
|
||||
bug_reports
|
||||
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
.. _documentation-home:
|
||||
|
||||
========================
|
||||
LiteSATA Documentation
|
||||
========================
|
||||
|
||||
This comprehensive documentation set contains everything you need to know to use LiteSATA and integrate it in your design.
|
||||
|
||||
**Getting started:**
|
||||
|
||||
- :ref:`intro-index` explains what LiteSATA does, why it is needed, its limitations and its licensing. It will help you understand whether LiteSATA is the right core for you.
|
||||
- :ref:`getting-started-index` walks you through downloading, installing and using the LiteSATA core.
|
||||
|
||||
**LiteSATA Internals:**
|
||||
|
||||
- :ref:`phy-index` describes PHY building blocks.
|
||||
- :ref:`core-index` describes core building blocks.
|
||||
- :ref:`frontend-index` describes core building blocks.
|
||||
|
||||
**LiteSATA Verifications:**
|
||||
|
||||
- :ref:`simulation-index` describes provided simulations.
|
||||
- :ref:`test-index` describes provided tests.
|
||||
|
||||
The full hierarchy of articles, opened to the second level, is shown below.
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
intro/index
|
||||
getting_started/index
|
||||
specification/index
|
||||
phy/index
|
||||
core/index
|
||||
frontend/index
|
||||
simulation/index
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
.. _about:
|
||||
|
||||
================
|
||||
About LiteSATA
|
||||
================
|
||||
|
||||
LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
|
||||
|
||||
LiteSATA is part of LiteX libraries whose aims is to lower entry level of complex
|
||||
FPGA cores by providing simple, elegant and efficient implementations of
|
||||
components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
|
||||
|
||||
The core uses simple and specific streaming buses and will provides in the future
|
||||
adapters to use standardized AXI or Avalon-ST streaming buses.
|
||||
|
||||
Since Python is used to describe the HDL, the core is highly and easily
|
||||
configurable.
|
||||
|
||||
The synthetizable BIST can be used as a starting point to integrate SATA in
|
||||
your own SoC.
|
||||
|
||||
LiteSATA uses technologies developed in partnership with M-Labs Ltd:
|
||||
- Migen enables generating HDL with Python in an efficient way.
|
||||
- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
|
||||
|
||||
LiteSATA can be used as a Migen/MiSoC library (by simply installing it
|
||||
with the provided setup.py) or can be integrated with your standard design flow
|
||||
by generating the verilog rtl that you will use as a standard core.
|
||||
|
||||
.. _about-toolchain:
|
||||
|
||||
Features
|
||||
========
|
||||
PHY:
|
||||
- OOB, COMWAKE, COMINIT
|
||||
- ALIGN inserter/remover and bytes alignment on K28.5
|
||||
- 8B/10B encoding/decoding in transceiver
|
||||
- Errors detection and reporting
|
||||
- 32 bits interface
|
||||
- 1.5/3.0/6.0GBps supported speeds (respectively 37.5/75/150MHz system clk)
|
||||
Core:
|
||||
Link:
|
||||
- CONT inserter/remover
|
||||
- Scrambling/Descrambling of data
|
||||
- CRC inserter/checker
|
||||
- HOLD insertion/detection
|
||||
- Errors detection and reporting
|
||||
Transport/Command:
|
||||
- Easy to use user interfaces (Can be used with or without CPU)
|
||||
- 48 bits sector addressing
|
||||
- 3 supported commands: READ_DMA(_EXT), WRITE_DMA(_EXT), IDENTIFY_DEVICE
|
||||
- Errors detection and reporting
|
||||
|
||||
Frontend:
|
||||
- Configurable crossbar (simply use core.crossbar.get_port() to add a new port!)
|
||||
- Ports arbitration transparent to the user
|
||||
- Synthetizable BIST
|
||||
|
||||
|
||||
Possibles improvements
|
||||
======================
|
||||
- add standardized interfaces (AXI, Avalon-ST)
|
||||
- add NCQ support
|
||||
- add AES hardware encryption
|
||||
- add on-the-flow compression/decompression
|
||||
- add support for Altera PHYs.
|
||||
- add support for Lattice PHYs.
|
||||
- add support for Xilinx 7-Series GTP/GTH (currently only 7-Series GTX are
|
||||
supported)
|
||||
- add Zynq Linux drivers.
|
||||
- ... See below Support and Consulting :)
|
||||
|
||||
Support and Consulting
|
||||
======================
|
||||
We love open-source hardware and like sharing our designs with others.
|
||||
|
||||
LiteSATA is developed and maintained by EnjoyDigital.
|
||||
|
||||
If you would like to know more about LiteSATA or if you are already a happy user
|
||||
and would like to extend it for your needs, EnjoyDigital can provide standard
|
||||
commercial support as well as consulting services.
|
||||
|
||||
So feel free to contact us, we'd love to work with you! (and eventually shorten
|
||||
the list of the possible improvements :)
|
||||
|
||||
Contact
|
||||
=======
|
||||
E-mail: florent [AT] enjoy-digital.fr
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
.. _community:
|
||||
|
||||
=========
|
||||
Community
|
||||
=========
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
.. _intro-index:
|
||||
|
||||
======================
|
||||
Introducing LiteSATA
|
||||
======================
|
||||
|
||||
This section explains what LiteSATA does, why it is needed, its limitations and its licensing. After reading, you will understand whether LiteSATA is the right core for you, and where to go if you have :ref:`further questions <community>`.
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
|
||||
about
|
||||
license
|
||||
release_notes
|
||||
talks_and_publications
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
.. _license:
|
||||
|
||||
===================
|
||||
Open Source License
|
||||
===================
|
||||
|
||||
LiteSATA is released under the very permissive two-clause BSD license. Under the
|
||||
terms of this license, you are authorized to use LiteSATA for closed-source
|
||||
proprietary designs.
|
||||
Even though we do not require you to do so, those things are awesome, so please
|
||||
do them if possible:
|
||||
- tell us that you are using LiteSATA
|
||||
- cite LiteSATA in publications related to research it has helped
|
||||
- send us feedback and suggestions for improvements
|
||||
- send us bug reports when something goes wrong
|
||||
- send us the modifications and improvements you have done to LiteSATA.
|
||||
|
||||
::
|
||||
|
||||
Unless otherwise noted, LiteSATA is copyright (C) 2015 HKU.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
|
||||
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
|
||||
Other authors retain ownership of their contributions. If a submission can
|
||||
reasonably be considered independently copyrightable, it's yours and we
|
||||
encourage you to claim it with appropriate copyright notices. This submission
|
||||
then falls under the "otherwise noted" category. All submissions are strongly
|
||||
encouraged to use the two-clause BSD license reproduced above.
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
.. _release-notes:
|
||||
|
||||
=============
|
||||
Release Notes
|
||||
=============
|
||||
|
||||
.. _ChangeLog:
|
||||
|
||||
ChangeLog
|
||||
=========
|
||||
0.9.0:
|
||||
- First release supporting Xilinx Kintex7.
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
.. _talks-and-publications:
|
||||
|
||||
======================
|
||||
Talks and Publications
|
||||
======================
|
||||
|
||||
- Migen / MiSoC documentation:
|
||||
- `User guide <http://m-labs.hk/migen.pdf>`_ (`m-labs <https://github.com/m-labs>`_)
|
||||
- `Tutorial: An introduction to Migen <http://m-labs.hk/migen-tutorial.pdf>`_ (`m-labs <https://github.com/m-labs>`_)
|
||||
|
||||
- Migen / MiSoC presentations:
|
||||
- `Lecture slides <http://m-labs.hk/migen-slides.pdf>`_ (`sbourdeauducq <https://github.com/sbourdeauducq>`_)
|
||||
- `EHSM 2012 presentation <https://www.youtube.com/watch?v=yxKMsAi_WEA>`_ (`sbourdeauducq <https://github.com/sbourdeauducq>`_)
|
||||
- `ORCONF2014 <https://www.youtube.com/watch?v=AfEPbw4nREo>`_ (`fallen <https://github.com/fallen>`_)
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
.. _phy-index:
|
||||
|
||||
========================
|
||||
PHY
|
||||
========================
|
||||
.. note::
|
||||
Please contribute to this document, or support us financially to write it.
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
.. _simulation-index:
|
||||
|
||||
========================
|
||||
Simulation
|
||||
========================
|
||||
|
||||
.. note::
|
||||
Please contribute to this document, or support us financially to write it.
|
||||
|
||||
Simulations are available in ./lib/sata/test:
|
||||
- crc_tb
|
||||
- scrambler_tb
|
||||
- phy_datapath_tb
|
||||
- link_tb
|
||||
- command_tb
|
||||
- bist_tb
|
||||
|
||||
hdd.py is a simplified HDD model implementing all SATA layers.
|
||||
To run a simulation, move to ./lib/sata/test and run:
|
||||
- make simulation_name
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 11 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 6.0 KiB |
|
|
@ -0,0 +1,211 @@
|
|||
.. _sata-index:
|
||||
|
||||
========================
|
||||
SATA Specification
|
||||
========================
|
||||
|
||||
.. note::
|
||||
This chapter is a lightly modified version of the excellent SATA summerization found in Chapter 2 of Erik Landström's Thesis_.
|
||||
|
||||
Serial Advanced Technology Attachment (SATA) is a serial link replacement of
|
||||
Parallel ATA (PATA), both standards for communication with mass storage devices.
|
||||
This high-speed serial link is a differential layer that utilizes Gigabit technology
|
||||
and 8b/10b encoding. The link supports full duplex but the protocol only permits frames
|
||||
in one direction at a time. The other non-data direction is used for flow control of the
|
||||
data stream
|
||||
|
||||
.. figure:: sata_layers.png
|
||||
:scale: 50 %
|
||||
:align: center
|
||||
|
||||
SATA layers.
|
||||
|
||||
SATA’s architecture consists of four layers, Application, Transport, Link, and Physical.
|
||||
The Application layer is responsible for overall ATA commands and of controlling SATA
|
||||
register accesses. The transport layer places control information and data to be transferred between
|
||||
the host and corresponding SATA device in a data packets. One such packet is called a frame
|
||||
information structure (FIS). The Link layer is responsible for taking data from a FIS and
|
||||
encode/decode it using 8b/10b. It also inserts control characters for flow control and calculates
|
||||
the cyclic redundancy check (CRC) for error detection. Finally the Phy layer’s task is to deliver
|
||||
and receive the encoded serial data stream on the wire.
|
||||
|
||||
Dword - Data Representation
|
||||
===========================
|
||||
In the SATA standard the smallest allowed data is a Dword, its 32 bits are divided
|
||||
into four bytes. Where each pair of bytes represent a word and a pair of words
|
||||
represent a Dword. In this way it’s easy to see that odd number of bytes is not
|
||||
allowed in SATA communication.
|
||||
|
||||
.. figure:: byte_word_dword.png
|
||||
:scale: 50 %
|
||||
:align: center
|
||||
|
||||
Byte, Word, Dword definitions.
|
||||
|
||||
The Dwords can be represented by either a data Dword or a so called primitive. A
|
||||
primitive is a predefined Dword like for example start of frame (SOF) and end
|
||||
of frame (EOF).
|
||||
|
||||
Primitives
|
||||
==========
|
||||
Primitives are Dwords with a purpose to enable and control the serial communication.
|
||||
They all begin with a control character followed by three other characters to
|
||||
fill up the Dword. The control character makes it easy to recognize a primitive from
|
||||
a ordinary Dword of a frame. There is 18 different primitives, all with a dedicated
|
||||
task like for example mark a frame with a SOF or to provide synchronization
|
||||
with the SYNC.
|
||||
|
||||
8b/10b - Encoding
|
||||
=================
|
||||
8b/10b encoding is rather common in high speed applications, it’s used to provide
|
||||
bounded disparity but still provide enough toggling to make clock recovery possible
|
||||
(synchronize internal clock with the data stream). The bounded disparity means
|
||||
that in a string of twenty bits the difference between zeros and ones shall be -2, 0,
|
||||
or 2 and with a maximum runlength of five. The drawback is the created overhead
|
||||
of two bits per byte making the actual transfer speed of for example 1.5 Gbps link
|
||||
to 1.2 Gbps, a loss of 20 %. Since the 8b/10b extends the possible alphabet from
|
||||
256 symbols to 1024 it can provide detection and encoding of special characters
|
||||
(also called k-characters) in an easy and effective way. This is used in the SATA
|
||||
standard by encoding every primitive as such special characters.
|
||||
|
||||
|
||||
Out of Band Signaling
|
||||
======================
|
||||
Since SATA devices and hosts always sends junk over its differential channels,
|
||||
when it is idle (otherwise the link is considered lost), there has to be a way of
|
||||
recognizing a signal before a link has been initialized. For this SATA uses so
|
||||
called out of band signaling (OOB) to initialize a connection between a host and a
|
||||
device. The OOB mechanism supports low speed transmission over a high speed
|
||||
connection, such as a SATA link. The OOB signals are non-differential but are sent
|
||||
over a differential channel. This is possible by letting the differential transmitters
|
||||
drive their output pins to the same voltage, resulting in a reduced difference and
|
||||
when a preset threshold limit is reached the receiver can recognize the signal as
|
||||
OOB.
|
||||
|
||||
.. figure:: oob_signals.png
|
||||
:scale: 50 %
|
||||
:align: center
|
||||
|
||||
OOB signals.
|
||||
|
||||
As can be seen in the figure there are three types of (actually two
|
||||
since COMINIT and COMRESET are equal) valid OOB signals where bursts of
|
||||
six ALIGN are sent with different timing. The importance in the signaling lies
|
||||
in the timing, it does not really matter if an ALIGN or something else are sent
|
||||
because the receiver only detects the drop of voltage difference between rx+ and
|
||||
rx-. In the next figure the complete startup sequence is visualized and
|
||||
the calibration steps in it are optional to implement. The host sends COMRESET
|
||||
until the device is powered on and can respond with a COMINIT. Upon reception
|
||||
of the COMINIT the host sends a COMWAKE to the device which shall send a
|
||||
COMWAKE back. If this procedure is finished within a correct time the OOB signaling
|
||||
ends and the differential communication can proceed with determining the link speed
|
||||
(right part of the figure).
|
||||
|
||||
.. figure:: oob_sequence.png
|
||||
:scale: 50 %
|
||||
:align: center
|
||||
|
||||
OOB init sequence.
|
||||
|
||||
Physical Layer
|
||||
==============
|
||||
This section describes the physical interface towards the actual SATA link.
|
||||
The features of the phy can be summarized to:
|
||||
- Transmit/Receive a 1.5 Gbps, 3.0 or 6.0 Gbps differential signal
|
||||
- Speed negotiation
|
||||
- OOB detection and transmission
|
||||
- Serialize a 10, 20, or other width parallel data from the link layer
|
||||
- Extract data from the serial data stream
|
||||
- Parallelize the data stream and send it to the link layer
|
||||
- Handle spread spectrum clocking (SSC), a clock modulation technique used
|
||||
to reduce unintentional interference to radio signals
|
||||
|
||||
At startup the physical layer is in its OOB state and after a link has been initiated
|
||||
it changes to Idle Bus condition and normal SATA communication is now
|
||||
supported. Since the SATA connection is noisy the physical layer detects a frame
|
||||
when it receives a SOF primitive and it will keep on listening to the incoming
|
||||
signal until an EOF primitive is received. Except from FIS the SATA traffic
|
||||
also consists of single primitives which all are easy for the PHY to recognize because
|
||||
of their starting control character.
|
||||
|
||||
Link Layer
|
||||
==========
|
||||
This section describes the SATA link layer.
|
||||
The link layer’s major tasks are:
|
||||
- Flow control
|
||||
- Encapsulate FISes received from transport layer
|
||||
- CRC generation and CRC check
|
||||
- FIS scrambling and de-scrambling
|
||||
- 8b/10b encoding/decoding
|
||||
|
||||
A FIS is framed between a SOF and a EOF creating the boundaries of a frame.
|
||||
The last Dword before a EOF is the CRC value for the FIS. The CRC is calculated
|
||||
by applying the 32-bits generator polynomial G(x) in Equation on every bit in
|
||||
every non-primitive Dword in a FIS and then summarize (modulo 2) all these terms
|
||||
together with the Initial Value. The CRC is fixed to value of 0x52325032.
|
||||
|
||||
.. figure:: crc.png
|
||||
:scale: 50 %
|
||||
:align: center
|
||||
|
||||
CRC polynom.
|
||||
|
||||
Scrambling a FIS reduces EMI by spreading the noise over a broader frequency
|
||||
spectrum. The scrambling algorithm can be expressed as a polynomial or as a linear
|
||||
feedback shift register. The scrambling creates a pseudorandom bit pattern of the
|
||||
data that reduces EMI. The algorithm resets to a of value of 0xFFFF every time a SOF
|
||||
is encountered at the scrambler. The de-scrambler uses the same algorithm on scrambled
|
||||
data so it retakes its original form.
|
||||
|
||||
.. figure:: scrambler.png
|
||||
:scale: 50 %
|
||||
:align: center
|
||||
|
||||
Scrambler LFSR polynom.
|
||||
|
||||
It is important that the CRC calculations are made at original data and that
|
||||
the scrambling/de-scrambling are made between the CRC and the 8b/10b encoding/decoding.
|
||||
The flow control between host and device is managed by sending
|
||||
primitives to one another telling its status (which originates from the transport
|
||||
layer). Some of these primitives can be inserted into FIS. Primitives are not
|
||||
supposed to be scrambled or added to the CRC sum. Internally the flow control
|
||||
are regulated by signaling between the layers.
|
||||
|
||||
Transport Layer
|
||||
===============
|
||||
The main task for the SATA transport layer is to handle FISes and a brief description
|
||||
of the layer’s features follows:
|
||||
- Flow control
|
||||
- Error control
|
||||
- Error reporting
|
||||
- FIS construction
|
||||
- FIS decomposition
|
||||
- FIS buffering for retransmission
|
||||
|
||||
There are eight types of FISes each with its specific 8-bit ID and unique header.
|
||||
FISes vary in size from 1 Dword up to 2049 Dwords. The number of bytes in a
|
||||
FIS are always a multiple of four so the transport layer has to fill up with zeros if
|
||||
there are bytes or bits missing for an entire Dword.
|
||||
The flow control in this case is only to report to the link layer that the data buffers
|
||||
are close to over- or underflow. Errors detected are supposed to be reported to
|
||||
the application layer and the detectable errors are:
|
||||
- Errors from lower layers like 8b/10b disparity error or CRC errors.
|
||||
- SATA state or protocol errors caused by standard violation.
|
||||
- Frame errors like malformed header.
|
||||
- Internal transport layer errors like buffer overflow.
|
||||
|
||||
Errors are handled in different ways, for example are resending of complete FISes
|
||||
supported for all kind of FISes besides the data FISes (and the BIST FIS which
|
||||
is used typically during testing), because that would need buffers in size of 8192
|
||||
bytes (maximum supported FIS size). The max sized non-data FIS is 28 bytes so
|
||||
the costs of a large buffer can be spared.
|
||||
|
||||
Command Layer
|
||||
=================
|
||||
The command layer tells the transport layer what kind of FISes to send and receive
|
||||
for each specific command and in which order those FISes are expexted to be delivered.
|
||||
|
||||
.. note::
|
||||
This chapter is a lightly modified version of the excellent SATA summerization found in Chapter 2 of Erik Landström's Thesis_.
|
||||
|
||||
.. _Thesis: http://www.diva-portal.org/smash/get/diva2:207798/FULLTEXT01.pdf
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 94 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 29 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 13 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 4.0 KiB |
|
|
@ -0,0 +1,13 @@
|
|||
.. _test-index:
|
||||
|
||||
========================
|
||||
Test
|
||||
========================
|
||||
|
||||
.. note::
|
||||
Please contribute to this document, or support us financially to write it.
|
||||
|
||||
A synthetizable BIST is provided and can be controlled with ./test/bist.py.
|
||||
By using LiteScope and the provided ./test/test_link.py example you are able to
|
||||
visualize the internal logic of the design and even inject the captured data in
|
||||
the HDD model!
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
<img alt="./_static/LiteSATA_logo_full.png" src="_static/LiteSATA_logo_full.png">
|
||||
|
||||
<h3>LiteSATA provides a <b>small footprint and configurable FPGA SATA gen1/2/3 core</b>.</h3>
|
||||
|
||||
<div class="container" style="width:100%;margin-bottom:10px;">
|
||||
|
||||
<div class="one-third-container" style="width:32%; display:inline-block;">
|
||||
<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px;margin-right:5px;">
|
||||
<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Small footprint</div>
|
||||
<div class="signpost-body" style=""><p>Thanks to simple and efficient Migen's building blocks and the KISS principe used to develop this core, LiteSATA footprint is really small!</p></div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="one-third-container" style="width:32%; display:inline-block; font-style:bold;">
|
||||
<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px;margin-right:5px;">
|
||||
<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Configurable</div>
|
||||
<div class="signpost-body" style=""><p>LiteSATA generates HDL using Migen as a Python meta-language. The core is then easily configurable to fit
|
||||
user's needs! (Number of crossbar ports, included BIST and so on...)</p></div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="one-third-container" style="width:32%; display:inline-block; font-style:bold;">
|
||||
<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px; margin-right:5px;">
|
||||
<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Portable</div>
|
||||
<div class="signpost-body" style=""><p>Porting the core to another vendor or family only require adapting or adding a new PHY. All others building blocks of the core are generic.</p></div>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
.. title:: Main
|
||||
|
||||
.. _home-page:
|
||||
|
||||
.. raw:: html
|
||||
:file: home_page_layout.html
|
||||
|
||||
|
||||
-----
|
||||
|
||||
News
|
||||
====
|
||||
|
||||
- First 0.9.0 release supporting Xilinx Kintex7.
|
||||
|
||||
.. toctree::
|
||||
:hidden:
|
||||
|
||||
docs/intro/index
|
||||
docs/getting_started/index
|
||||
docs/specification/index
|
||||
docs/phy/index
|
||||
docs/core/index
|
||||
docs/frontend/index
|
||||
docs/simulation/index
|
||||
docs/test/index
|
||||
docs/site/about
|
||||
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
From 7444442f068cff672071ba0d8a2008c7f53275e3 Mon Sep 17 00:00:00 2001
|
||||
From: Florent Kermarrec <florent@enjoy-digital.fr>
|
||||
Date: Fri, 23 Jan 2015 10:13:47 +0100
|
||||
Subject: [PATCH] workaround for icarus simulation (Copyright 2014 David
|
||||
Carne)
|
||||
|
||||
---
|
||||
migen/fhdl/verilog.py | 51 +++++++++++++++++++++++++++++++++++----------------
|
||||
1 file changed, 35 insertions(+), 16 deletions(-)
|
||||
|
||||
diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
|
||||
index b4bd534..c0ec678 100644
|
||||
--- a/migen/fhdl/verilog.py
|
||||
+++ b/migen/fhdl/verilog.py
|
||||
@@ -95,9 +95,13 @@ def _printexpr(ns, node):
|
||||
|
||||
(_AT_BLOCKING, _AT_NONBLOCKING, _AT_SIGNAL) = range(3)
|
||||
|
||||
-def _printnode(ns, at, level, node):
|
||||
+def _printnode(ns, at, level, node, target_filter=None):
|
||||
if node is None:
|
||||
return ""
|
||||
+
|
||||
+ elif target_filter is not None and target_filter not in list_targets(node):
|
||||
+ return ""
|
||||
+
|
||||
elif isinstance(node, _Assign):
|
||||
if at == _AT_BLOCKING:
|
||||
assignment = " = "
|
||||
@@ -109,13 +113,13 @@ def _printnode(ns, at, level, node):
|
||||
assignment = " <= "
|
||||
return "\t"*level + _printexpr(ns, node.l)[0] + assignment + _printexpr(ns, node.r)[0] + ";\n"
|
||||
elif isinstance(node, (list, tuple)):
|
||||
- return "".join(list(map(partial(_printnode, ns, at, level), node)))
|
||||
+ return "".join(_printnode(ns, at, level, n, target_filter) for n in node)
|
||||
elif isinstance(node, If):
|
||||
r = "\t"*level + "if (" + _printexpr(ns, node.cond)[0] + ") begin\n"
|
||||
- r += _printnode(ns, at, level + 1, node.t)
|
||||
+ r += _printnode(ns, at, level + 1, node.t, target_filter)
|
||||
if node.f:
|
||||
r += "\t"*level + "end else begin\n"
|
||||
- r += _printnode(ns, at, level + 1, node.f)
|
||||
+ r += _printnode(ns, at, level + 1, node.f, target_filter)
|
||||
r += "\t"*level + "end\n"
|
||||
return r
|
||||
elif isinstance(node, Case):
|
||||
@@ -124,11 +128,12 @@ def _printnode(ns, at, level, node):
|
||||
css = sorted([(k, v) for (k, v) in node.cases.items() if k != "default"], key=itemgetter(0))
|
||||
for choice, statements in css:
|
||||
r += "\t"*(level + 1) + _printexpr(ns, choice)[0] + ": begin\n"
|
||||
- r += _printnode(ns, at, level + 2, statements)
|
||||
+ r += _printnode(ns, at, level + 2, statements, target_filter)
|
||||
r += "\t"*(level + 1) + "end\n"
|
||||
if "default" in node.cases:
|
||||
r += "\t"*(level + 1) + "default: begin\n"
|
||||
- r += _printnode(ns, at, level + 2, node.cases["default"])
|
||||
+ r += _printnode(ns, at, level + 2, node.cases["default"],
|
||||
+ target_filter)
|
||||
r += "\t"*(level + 1) + "end\n"
|
||||
r += "\t"*level + "endcase\n"
|
||||
return r
|
||||
@@ -187,26 +192,40 @@ def _printcomb(f, ns, display_run):
|
||||
r += "reg " + _printsig(ns, dummy_s) + ";\n"
|
||||
r += "initial " + ns.get_name(dummy_s) + " <= 1'd0;\n"
|
||||
r += syn_on
|
||||
+
|
||||
+ from collections import defaultdict
|
||||
+
|
||||
+ target_stmt_map = defaultdict(list)
|
||||
+
|
||||
+ for statement in flat_iteration(f.comb):
|
||||
+ targets = list_targets(statement)
|
||||
+ for t in targets:
|
||||
+ target_stmt_map[t].append(statement)
|
||||
+
|
||||
+ #from pprint import pprint
|
||||
+ #pprint(target_stmt_map)
|
||||
|
||||
groups = group_by_targets(f.comb)
|
||||
+
|
||||
+ for n, (t, stmts) in enumerate(target_stmt_map.items()):
|
||||
+ assert isinstance(t, Signal)
|
||||
|
||||
- for n, g in enumerate(groups):
|
||||
- if len(g[1]) == 1 and isinstance(g[1][0], _Assign):
|
||||
- r += "assign " + _printnode(ns, _AT_BLOCKING, 0, g[1][0])
|
||||
+ if len(stmts) == 1 and isinstance(stmts[0], _Assign):
|
||||
+ r += "assign " + _printnode(ns, _AT_BLOCKING, 0, stmts[0])
|
||||
else:
|
||||
dummy_d = Signal(name_override="dummy_d")
|
||||
r += "\n" + syn_off
|
||||
r += "reg " + _printsig(ns, dummy_d) + ";\n"
|
||||
r += syn_on
|
||||
-
|
||||
+
|
||||
r += "always @(*) begin\n"
|
||||
if display_run:
|
||||
r += "\t$display(\"Running comb block #" + str(n) + "\");\n"
|
||||
- for t in g[0]:
|
||||
- r += "\t" + ns.get_name(t) + " <= " + _printexpr(ns, t.reset)[0] + ";\n"
|
||||
- r += _printnode(ns, _AT_NONBLOCKING, 1, g[1])
|
||||
+
|
||||
+ r += "\t" + ns.get_name(t) + " = " + _printexpr(ns, t.reset)[0] + ";\n"
|
||||
+ r += _printnode(ns, _AT_BLOCKING, 1, stmts, t)
|
||||
r += syn_off
|
||||
- r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n"
|
||||
+ r += "\t" + ns.get_name(dummy_d) + " = " + ns.get_name(dummy_s) + ";\n"
|
||||
r += syn_on
|
||||
r += "end\n"
|
||||
r += "\n"
|
||||
@@ -275,7 +294,7 @@ def _printinit(f, ios, ns):
|
||||
signals = (list_signals(f) | list_special_ios(f, True, False, False)) \
|
||||
- ios \
|
||||
- list_targets(f) \
|
||||
- - list_special_ios(f, False, True, True)
|
||||
+ - list_special_ios(f, False, True, False)
|
||||
if signals:
|
||||
r += "initial begin\n"
|
||||
for s in sorted(signals, key=lambda x: x.huid):
|
||||
@@ -303,7 +322,7 @@ def convert(f, ios=None, name="top",
|
||||
ios |= {cd.clk, cd.rst}
|
||||
else:
|
||||
raise KeyError("Unresolved clock domain: '"+cd_name+"'")
|
||||
-
|
||||
+
|
||||
f = lower_complex_slices(f)
|
||||
insert_resets(f)
|
||||
f = lower_basics(f)
|
||||
--
|
||||
1.8.0.msysgit.0
|
||||
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
0.9.0
|
||||
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
from litesata.common import *
|
||||
from litesata.phy import *
|
||||
from litesata.core import *
|
||||
from litesata.frontend import *
|
||||
|
||||
from migen.bank.description import *
|
||||
|
||||
class LiteSATA(Module, AutoCSR):
|
||||
def __init__(self, phy, buffer_depth=2*fis_max_dwords,
|
||||
with_bist=False, with_bist_csr=False):
|
||||
# phy
|
||||
self.phy = phy
|
||||
|
||||
# core
|
||||
self.submodules.core = LiteSATACore(self.phy, buffer_depth)
|
||||
|
||||
# frontend
|
||||
self.submodules.crossbar = LiteSATACrossbar(self.core)
|
||||
if with_bist:
|
||||
self.submodules.bist = LiteSATABIST(self.crossbar, with_bist_csr)
|
||||
|
||||
|
|
@ -0,0 +1,381 @@
|
|||
import math
|
||||
|
||||
from migen.fhdl.std import *
|
||||
from migen.fhdl.decorators import ModuleDecorator
|
||||
from migen.genlib.resetsync import *
|
||||
from migen.genlib.fsm import *
|
||||
from migen.genlib.record import *
|
||||
from migen.genlib.misc import chooser, optree
|
||||
from migen.genlib.cdc import *
|
||||
from migen.flow.actor import *
|
||||
from migen.flow.plumbing import Multiplexer, Demultiplexer
|
||||
from migen.flow.plumbing import Buffer
|
||||
from migen.actorlib.fifo import *
|
||||
from migen.actorlib.structuring import Pipeline, Converter
|
||||
|
||||
bitrates = {
|
||||
"sata_gen3" : 6.0,
|
||||
"sata_gen2" : 3.0,
|
||||
"sata_gen1" : 1.5,
|
||||
}
|
||||
|
||||
frequencies = {
|
||||
"sata_gen3" : 150.0,
|
||||
"sata_gen2" : 75.0,
|
||||
"sata_gen1" : 37.5,
|
||||
}
|
||||
|
||||
# PHY / Link Layers
|
||||
primitives = {
|
||||
"ALIGN" : 0x7B4A4ABC,
|
||||
"CONT" : 0X9999AA7C,
|
||||
"SYNC" : 0xB5B5957C,
|
||||
"R_RDY" : 0x4A4A957C,
|
||||
"R_OK" : 0x3535B57C,
|
||||
"R_ERR" : 0x5656B57C,
|
||||
"R_IP" : 0X5555B57C,
|
||||
"X_RDY" : 0x5757B57C,
|
||||
"CONT" : 0x9999AA7C,
|
||||
"WTRM" : 0x5858B57C,
|
||||
"SOF" : 0x3737B57C,
|
||||
"EOF" : 0xD5D5B57C,
|
||||
"HOLD" : 0xD5D5AA7C,
|
||||
"HOLDA" : 0X9595AA7C
|
||||
}
|
||||
|
||||
def is_primitive(dword):
|
||||
for k, v in primitives.items():
|
||||
if dword == v:
|
||||
return True
|
||||
return False
|
||||
|
||||
def decode_primitive(dword):
|
||||
for k, v in primitives.items():
|
||||
if dword == v:
|
||||
return k
|
||||
return ""
|
||||
|
||||
def phy_description(dw):
|
||||
layout = [
|
||||
("data", dw),
|
||||
("charisk", dw//8),
|
||||
]
|
||||
return EndpointDescription(layout, packetized=False)
|
||||
|
||||
def link_description(dw):
|
||||
layout = [
|
||||
("d", dw),
|
||||
("error", 1)
|
||||
]
|
||||
return EndpointDescription(layout, packetized=True)
|
||||
|
||||
# Transport Layer
|
||||
fis_max_dwords = 2048
|
||||
|
||||
fis_types = {
|
||||
"REG_H2D": 0x27,
|
||||
"REG_D2H": 0x34,
|
||||
"DMA_ACTIVATE_D2H": 0x39,
|
||||
"PIO_SETUP_D2H": 0x5F,
|
||||
"DATA": 0x46
|
||||
}
|
||||
|
||||
class FISField():
|
||||
def __init__(self, dword, offset, width):
|
||||
self.dword = dword
|
||||
self.offset = offset
|
||||
self.width = width
|
||||
|
||||
fis_reg_h2d_cmd_len = 5
|
||||
fis_reg_h2d_layout = {
|
||||
"type": FISField(0, 0, 8),
|
||||
"pm_port": FISField(0, 8, 4),
|
||||
"c": FISField(0, 15, 1),
|
||||
"command": FISField(0, 16, 8),
|
||||
"features_lsb": FISField(0, 24, 8),
|
||||
|
||||
"lba_lsb": FISField(1, 0, 24),
|
||||
"device": FISField(1, 24, 8),
|
||||
|
||||
"lba_msb": FISField(2, 0, 24),
|
||||
"features_msb": FISField(2, 24, 8),
|
||||
|
||||
"count": FISField(3, 0, 16),
|
||||
"icc": FISField(3, 16, 8),
|
||||
"control": FISField(3, 24, 8)
|
||||
}
|
||||
|
||||
fis_reg_d2h_cmd_len = 5
|
||||
fis_reg_d2h_layout = {
|
||||
"type": FISField(0, 0, 8),
|
||||
"pm_port": FISField(0, 8, 4),
|
||||
"i": FISField(0, 14, 1),
|
||||
"status": FISField(0, 16, 8),
|
||||
"error": FISField(0, 24, 8),
|
||||
|
||||
"lba_lsb": FISField(1, 0, 24),
|
||||
"device": FISField(1, 24, 8),
|
||||
|
||||
"lba_msb": FISField(2, 0, 24),
|
||||
|
||||
"count": FISField(3, 0, 16)
|
||||
}
|
||||
|
||||
fis_dma_activate_d2h_cmd_len = 1
|
||||
fis_dma_activate_d2h_layout = {
|
||||
"type": FISField(0, 0, 8),
|
||||
"pm_port": FISField(0, 8, 4)
|
||||
}
|
||||
|
||||
fis_pio_setup_d2h_cmd_len = 5
|
||||
fis_pio_setup_d2h_layout = {
|
||||
"type": FISField(0, 0, 8),
|
||||
"pm_port": FISField(0, 8, 4),
|
||||
"d": FISField(0, 13, 1),
|
||||
"i": FISField(0, 14, 1),
|
||||
"status": FISField(0, 16, 8),
|
||||
"error": FISField(0, 24, 8),
|
||||
|
||||
"lba_lsb": FISField(1, 0, 24),
|
||||
|
||||
"lba_msb": FISField(2, 0, 24),
|
||||
|
||||
"count": FISField(3, 0, 16),
|
||||
|
||||
"transfer_count": FISField(4, 0, 16),
|
||||
}
|
||||
|
||||
fis_data_cmd_len = 1
|
||||
fis_data_layout = {
|
||||
"type": FISField(0, 0, 8)
|
||||
}
|
||||
|
||||
def transport_tx_description(dw):
|
||||
layout = [
|
||||
("type", 8),
|
||||
("pm_port", 4),
|
||||
("c", 1),
|
||||
("command", 8),
|
||||
("features", 16),
|
||||
("lba", 48),
|
||||
("device", 8),
|
||||
("count", 16),
|
||||
("icc", 8),
|
||||
("control", 8),
|
||||
("data", dw)
|
||||
]
|
||||
return EndpointDescription(layout, packetized=True)
|
||||
|
||||
def transport_rx_description(dw):
|
||||
layout = [
|
||||
("type", 8),
|
||||
("pm_port", 4),
|
||||
("r", 1),
|
||||
("d", 1),
|
||||
("i", 1),
|
||||
("status", 8),
|
||||
("errors", 8),
|
||||
("lba", 48),
|
||||
("device", 8),
|
||||
("count", 16),
|
||||
("transfer_count", 16),
|
||||
("data", dw),
|
||||
("error", 1)
|
||||
]
|
||||
return EndpointDescription(layout, packetized=True)
|
||||
|
||||
# Command Layer
|
||||
regs = {
|
||||
"WRITE_DMA_EXT" : 0x35,
|
||||
"READ_DMA_EXT" : 0x25,
|
||||
"IDENTIFY_DEVICE" : 0xEC
|
||||
}
|
||||
|
||||
reg_d2h_status = {
|
||||
"bsy" : 7,
|
||||
"drdy" : 6,
|
||||
"df" : 5,
|
||||
"se" : 5,
|
||||
"dwe" : 4,
|
||||
"drq" : 3,
|
||||
"ae" : 2,
|
||||
"sns" : 1,
|
||||
"cc" : 0,
|
||||
"err" : 0
|
||||
}
|
||||
|
||||
def command_tx_description(dw):
|
||||
layout = [
|
||||
("write", 1),
|
||||
("read", 1),
|
||||
("identify", 1),
|
||||
("sector", 48),
|
||||
("count", 16),
|
||||
("data", dw)
|
||||
]
|
||||
return EndpointDescription(layout, packetized=True)
|
||||
|
||||
def command_rx_description(dw):
|
||||
layout = [
|
||||
("write", 1),
|
||||
("read", 1),
|
||||
("identify", 1),
|
||||
("last", 1),
|
||||
("failed", 1),
|
||||
("data", dw)
|
||||
]
|
||||
return EndpointDescription(layout, packetized=True)
|
||||
|
||||
def command_rx_cmd_description(dw):
|
||||
layout = [
|
||||
("write", 1),
|
||||
("read", 1),
|
||||
("identify", 1),
|
||||
("last", 1),
|
||||
("failed", 1)
|
||||
]
|
||||
return EndpointDescription(layout, packetized=False)
|
||||
|
||||
def command_rx_data_description(dw):
|
||||
layout = [
|
||||
("data", dw)
|
||||
]
|
||||
return EndpointDescription(layout, packetized=True)
|
||||
|
||||
# HDD
|
||||
logical_sector_size = 512 # constant since all HDDs use this
|
||||
|
||||
def dwords2sectors(n):
|
||||
return math.ceil(n*4/logical_sector_size)
|
||||
|
||||
def sectors2dwords(n):
|
||||
return n*logical_sector_size//4
|
||||
|
||||
# Generic modules
|
||||
@DecorateModule(InsertReset)
|
||||
@DecorateModule(InsertCE)
|
||||
class Counter(Module):
|
||||
def __init__(self, signal=None, **kwargs):
|
||||
if signal is None:
|
||||
self.value = Signal(**kwargs)
|
||||
else:
|
||||
self.value = signal
|
||||
self.width = flen(self.value)
|
||||
self.sync += self.value.eq(self.value+1)
|
||||
|
||||
@DecorateModule(InsertReset)
|
||||
@DecorateModule(InsertCE)
|
||||
class Timeout(Module):
|
||||
def __init__(self, length):
|
||||
self.reached = Signal()
|
||||
###
|
||||
value = Signal(max=length)
|
||||
self.sync += If(~self.reached, value.eq(value+1))
|
||||
self.comb += self.reached.eq(value == (length-1))
|
||||
|
||||
class BufferizeEndpoints(ModuleDecorator):
|
||||
def __init__(self, submodule, *args):
|
||||
ModuleDecorator.__init__(self, submodule)
|
||||
|
||||
endpoints = get_endpoints(submodule)
|
||||
sinks = {}
|
||||
sources = {}
|
||||
for name, endpoint in endpoints.items():
|
||||
if name in args or len(args) == 0:
|
||||
if isinstance(endpoint, Sink):
|
||||
sinks.update({name : endpoint})
|
||||
elif isinstance(endpoint, Source):
|
||||
sources.update({name : endpoint})
|
||||
|
||||
# add buffer on sinks
|
||||
for name, sink in sinks.items():
|
||||
buf = Buffer(sink.description)
|
||||
self.submodules += buf
|
||||
setattr(self, name, buf.d)
|
||||
self.comb += Record.connect(buf.q, sink)
|
||||
|
||||
# add buffer on sources
|
||||
for name, source in sources.items():
|
||||
buf = Buffer(source.description)
|
||||
self.submodules += buf
|
||||
self.comb += Record.connect(source, buf.d)
|
||||
setattr(self, name, buf.q)
|
||||
|
||||
class EndpointPacketStatus(Module):
|
||||
def __init__(self, endpoint):
|
||||
self.start = Signal()
|
||||
self.done = Signal()
|
||||
self.ongoing = Signal()
|
||||
|
||||
ongoing = Signal()
|
||||
self.comb += [
|
||||
self.start.eq(endpoint.stb & endpoint.sop & endpoint.ack),
|
||||
self.done.eq(endpoint.stb & endpoint.eop & endpoint.ack)
|
||||
]
|
||||
self.sync += \
|
||||
If(self.start,
|
||||
ongoing.eq(1)
|
||||
).Elif(self.done,
|
||||
ongoing.eq(0)
|
||||
)
|
||||
self.comb += self.ongoing.eq((self.start | ongoing) & ~self.done)
|
||||
|
||||
class PacketBuffer(Module):
|
||||
def __init__(self, description, data_depth, cmd_depth=4, almost_full=None):
|
||||
self.sink = sink = Sink(description)
|
||||
self.source = source = Source(description)
|
||||
|
||||
###
|
||||
sink_status = EndpointPacketStatus(self.sink)
|
||||
source_status = EndpointPacketStatus(self.source)
|
||||
self.submodules += sink_status, source_status
|
||||
|
||||
# store incoming packets
|
||||
# cmds
|
||||
def cmd_description():
|
||||
layout = [("error", 1)]
|
||||
return EndpointDescription(layout)
|
||||
cmd_fifo = SyncFIFO(cmd_description(), cmd_depth)
|
||||
self.submodules += cmd_fifo
|
||||
self.comb += [
|
||||
cmd_fifo.sink.stb.eq(sink_status.done),
|
||||
cmd_fifo.sink.error.eq(sink.error)
|
||||
]
|
||||
|
||||
# data
|
||||
data_fifo = SyncFIFO(description, data_depth, buffered=True)
|
||||
self.submodules += data_fifo
|
||||
self.comb += [
|
||||
Record.connect(self.sink, data_fifo.sink),
|
||||
data_fifo.sink.stb.eq(self.sink.stb & cmd_fifo.sink.ack),
|
||||
self.sink.ack.eq(data_fifo.sink.ack & cmd_fifo.sink.ack),
|
||||
]
|
||||
|
||||
# output packets
|
||||
self.fsm = fsm = FSM(reset_state="IDLE")
|
||||
self.submodules += fsm
|
||||
fsm.act("IDLE",
|
||||
If(cmd_fifo.source.stb,
|
||||
NextState("SEEK_SOP")
|
||||
)
|
||||
)
|
||||
fsm.act("SEEK_SOP",
|
||||
If(~data_fifo.source.sop,
|
||||
data_fifo.source.ack.eq(1)
|
||||
).Else(
|
||||
NextState("OUTPUT")
|
||||
)
|
||||
)
|
||||
fsm.act("OUTPUT",
|
||||
Record.connect(data_fifo.source, self.source),
|
||||
self.source.error.eq(cmd_fifo.source.error),
|
||||
If(source_status.done,
|
||||
cmd_fifo.source.ack.eq(1),
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
|
||||
# compute almost full
|
||||
if almost_full is not None:
|
||||
self.almost_full = Signal()
|
||||
self.comb += self.almost_full.eq(data_fifo.fifo.level > almost_full)
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
from litesata.common import *
|
||||
from litesata.core.link import LiteSATALink
|
||||
from litesata.core.transport import LiteSATATransport
|
||||
from litesata.core.command import LiteSATACommand
|
||||
|
||||
class LiteSATACore(Module):
|
||||
def __init__(self, phy, buffer_depth):
|
||||
self.submodules.link = LiteSATALink(phy, buffer_depth)
|
||||
self.submodules.transport = LiteSATATransport(self.link)
|
||||
self.submodules.command = LiteSATACommand(self.transport)
|
||||
self.sink, self.source = self.command.sink, self.command.source
|
||||
|
|
@ -0,0 +1,279 @@
|
|||
from litesata.common import *
|
||||
|
||||
tx_to_rx = [
|
||||
("write", 1),
|
||||
("read", 1),
|
||||
("identify", 1),
|
||||
("count", 16)
|
||||
]
|
||||
|
||||
rx_to_tx = [
|
||||
("dma_activate", 1),
|
||||
("d2h_error", 1)
|
||||
]
|
||||
|
||||
class LiteSATACommandTX(Module):
|
||||
def __init__(self, transport):
|
||||
self.sink = sink = Sink(command_tx_description(32))
|
||||
self.to_rx = to_rx = Source(tx_to_rx)
|
||||
self.from_rx = from_rx = Sink(rx_to_tx)
|
||||
|
||||
###
|
||||
|
||||
self.comb += [
|
||||
transport.sink.pm_port.eq(0),
|
||||
transport.sink.features.eq(0),
|
||||
transport.sink.lba.eq(sink.sector),
|
||||
transport.sink.device.eq(0xe0),
|
||||
transport.sink.count.eq(sink.count),
|
||||
transport.sink.icc.eq(0),
|
||||
transport.sink.control.eq(0),
|
||||
transport.sink.data.eq(sink.data)
|
||||
]
|
||||
|
||||
dwords_counter = Counter(max=fis_max_dwords)
|
||||
self.submodules += dwords_counter
|
||||
|
||||
is_write = Signal()
|
||||
is_read = Signal()
|
||||
is_identify = Signal()
|
||||
|
||||
self.fsm = fsm = FSM(reset_state="IDLE")
|
||||
self.submodules += fsm
|
||||
fsm.act("IDLE",
|
||||
sink.ack.eq(0),
|
||||
If(sink.stb & sink.sop,
|
||||
NextState("SEND_CMD")
|
||||
).Else(
|
||||
sink.ack.eq(1)
|
||||
)
|
||||
)
|
||||
self.sync += \
|
||||
If(fsm.ongoing("IDLE"),
|
||||
is_write.eq(sink.write),
|
||||
is_read.eq(sink.read),
|
||||
is_identify.eq(sink.identify),
|
||||
)
|
||||
|
||||
fsm.act("SEND_CMD",
|
||||
transport.sink.stb.eq(sink.stb),
|
||||
transport.sink.sop.eq(1),
|
||||
transport.sink.eop.eq(1),
|
||||
transport.sink.c.eq(1),
|
||||
If(transport.sink.stb & transport.sink.ack,
|
||||
If(is_write,
|
||||
NextState("WAIT_DMA_ACTIVATE")
|
||||
).Else(
|
||||
sink.ack.eq(1),
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
)
|
||||
fsm.act("WAIT_DMA_ACTIVATE",
|
||||
dwords_counter.reset.eq(1),
|
||||
If(from_rx.dma_activate,
|
||||
NextState("SEND_DATA")
|
||||
).Elif(from_rx.d2h_error,
|
||||
sink.ack.eq(1),
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
fsm.act("SEND_DATA",
|
||||
dwords_counter.ce.eq(sink.stb & sink.ack),
|
||||
|
||||
transport.sink.stb.eq(sink.stb),
|
||||
transport.sink.sop.eq(dwords_counter.value == 0),
|
||||
transport.sink.eop.eq((dwords_counter.value == (fis_max_dwords-1)) | sink.eop),
|
||||
|
||||
sink.ack.eq(transport.sink.ack),
|
||||
If(sink.stb & sink.ack,
|
||||
If(sink.eop,
|
||||
NextState("IDLE")
|
||||
).Elif(dwords_counter.value == (fis_max_dwords-1),
|
||||
NextState("WAIT_DMA_ACTIVATE")
|
||||
)
|
||||
)
|
||||
)
|
||||
self.comb += \
|
||||
If(fsm.ongoing("SEND_DATA"),
|
||||
transport.sink.type.eq(fis_types["DATA"]),
|
||||
).Else(
|
||||
transport.sink.type.eq(fis_types["REG_H2D"]),
|
||||
If(is_write,
|
||||
transport.sink.command.eq(regs["WRITE_DMA_EXT"])
|
||||
).Elif(is_read,
|
||||
transport.sink.command.eq(regs["READ_DMA_EXT"]),
|
||||
).Else(
|
||||
transport.sink.command.eq(regs["IDENTIFY_DEVICE"]),
|
||||
)
|
||||
)
|
||||
self.comb += [
|
||||
If(sink.stb,
|
||||
to_rx.write.eq(sink.write),
|
||||
to_rx.read.eq(sink.read),
|
||||
to_rx.identify.eq(sink.identify),
|
||||
to_rx.count.eq(sink.count)
|
||||
)
|
||||
]
|
||||
|
||||
class LiteSATACommandRX(Module):
|
||||
def __init__(self, transport):
|
||||
self.source = source = Source(command_rx_description(32))
|
||||
self.to_tx = to_tx = Source(rx_to_tx)
|
||||
self.from_tx = from_tx = Sink(tx_to_rx)
|
||||
|
||||
###
|
||||
|
||||
def test_type(name):
|
||||
return transport.source.type == fis_types[name]
|
||||
|
||||
is_identify = Signal()
|
||||
is_dma_activate = Signal()
|
||||
read_ndwords = Signal(max=sectors2dwords(2**16))
|
||||
dwords_counter = Counter(max=sectors2dwords(2**16))
|
||||
self.submodules += dwords_counter
|
||||
read_done = Signal()
|
||||
|
||||
self.sync += \
|
||||
If(from_tx.read,
|
||||
read_ndwords.eq(from_tx.count*sectors2dwords(1)-1)
|
||||
)
|
||||
self.comb += read_done.eq(dwords_counter.value == read_ndwords)
|
||||
|
||||
d2h_error = Signal()
|
||||
clr_d2h_error = Signal()
|
||||
set_d2h_error = Signal()
|
||||
self.sync += \
|
||||
If(clr_d2h_error,
|
||||
d2h_error.eq(0)
|
||||
).Elif(set_d2h_error,
|
||||
d2h_error.eq(1)
|
||||
)
|
||||
|
||||
read_error = Signal()
|
||||
clr_read_error = Signal()
|
||||
set_read_error = Signal()
|
||||
self.sync += \
|
||||
If(clr_read_error,
|
||||
read_error.eq(0)
|
||||
).Elif(set_read_error,
|
||||
read_error.eq(1)
|
||||
)
|
||||
|
||||
self.fsm = fsm = FSM(reset_state="IDLE")
|
||||
self.submodules += fsm
|
||||
fsm.act("IDLE",
|
||||
dwords_counter.reset.eq(1),
|
||||
transport.source.ack.eq(1),
|
||||
clr_d2h_error.eq(1),
|
||||
clr_read_error.eq(1),
|
||||
If(from_tx.write,
|
||||
NextState("WAIT_WRITE_ACTIVATE_OR_REG_D2H")
|
||||
).Elif(from_tx.read,
|
||||
NextState("WAIT_READ_DATA_OR_REG_D2H"),
|
||||
).Elif(from_tx.identify,
|
||||
NextState("WAIT_PIO_SETUP_D2H"),
|
||||
)
|
||||
)
|
||||
self.sync += \
|
||||
If(fsm.ongoing("IDLE"),
|
||||
is_identify.eq(from_tx.identify)
|
||||
)
|
||||
fsm.act("WAIT_WRITE_ACTIVATE_OR_REG_D2H",
|
||||
transport.source.ack.eq(1),
|
||||
If(transport.source.stb,
|
||||
If(test_type("DMA_ACTIVATE_D2H"),
|
||||
is_dma_activate.eq(1),
|
||||
).Elif(test_type("REG_D2H"),
|
||||
set_d2h_error.eq(transport.source.status[reg_d2h_status["err"]]),
|
||||
NextState("PRESENT_WRITE_RESPONSE")
|
||||
)
|
||||
)
|
||||
)
|
||||
fsm.act("PRESENT_WRITE_RESPONSE",
|
||||
source.stb.eq(1),
|
||||
source.sop.eq(1),
|
||||
source.eop.eq(1),
|
||||
source.write.eq(1),
|
||||
source.last.eq(1),
|
||||
source.failed.eq(transport.source.error | d2h_error),
|
||||
If(source.stb & source.ack,
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
fsm.act("WAIT_READ_DATA_OR_REG_D2H",
|
||||
transport.source.ack.eq(1),
|
||||
If(transport.source.stb,
|
||||
transport.source.ack.eq(0),
|
||||
If(test_type("DATA"),
|
||||
NextState("PRESENT_READ_DATA")
|
||||
).Elif(test_type("REG_D2H"),
|
||||
NextState("PRESENT_READ_RESPONSE")
|
||||
)
|
||||
)
|
||||
)
|
||||
fsm.act("WAIT_PIO_SETUP_D2H",
|
||||
transport.source.ack.eq(1),
|
||||
If(transport.source.stb,
|
||||
transport.source.ack.eq(0),
|
||||
If(test_type("PIO_SETUP_D2H"),
|
||||
NextState("PRESENT_PIO_SETUP_D2H")
|
||||
)
|
||||
)
|
||||
)
|
||||
fsm.act("PRESENT_PIO_SETUP_D2H",
|
||||
transport.source.ack.eq(1),
|
||||
If(transport.source.stb & transport.source.eop,
|
||||
NextState("WAIT_READ_DATA_OR_REG_D2H")
|
||||
)
|
||||
)
|
||||
|
||||
fsm.act("PRESENT_READ_DATA",
|
||||
set_read_error.eq(transport.source.error),
|
||||
source.stb.eq(transport.source.stb),
|
||||
source.sop.eq(transport.source.sop),
|
||||
source.eop.eq(transport.source.eop),
|
||||
source.read.eq(~is_identify),
|
||||
source.identify.eq(is_identify),
|
||||
source.failed.eq(transport.source.error),
|
||||
source.last.eq(is_identify),
|
||||
source.data.eq(transport.source.data),
|
||||
transport.source.ack.eq(source.ack),
|
||||
If(source.stb & source.ack,
|
||||
dwords_counter.ce.eq(~read_done),
|
||||
If(source.eop,
|
||||
If(is_identify,
|
||||
NextState("IDLE")
|
||||
).Else(
|
||||
NextState("WAIT_READ_DATA_OR_REG_D2H")
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
fsm.act("PRESENT_READ_RESPONSE",
|
||||
source.stb.eq(1),
|
||||
source.sop.eq(1),
|
||||
source.eop.eq(1),
|
||||
source.read.eq(1),
|
||||
source.last.eq(1),
|
||||
source.failed.eq(~read_done | read_error | d2h_error),
|
||||
If(source.stb & source.ack,
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
|
||||
self.comb += [
|
||||
to_tx.dma_activate.eq(is_dma_activate),
|
||||
to_tx.d2h_error.eq(d2h_error)
|
||||
]
|
||||
|
||||
class LiteSATACommand(Module):
|
||||
def __init__(self, transport):
|
||||
self.submodules.tx = LiteSATACommandTX(transport)
|
||||
self.submodules.rx = LiteSATACommandRX(transport)
|
||||
self.comb += [
|
||||
self.rx.to_tx.connect(self.tx.from_rx),
|
||||
self.tx.to_rx.connect(self.rx.from_tx)
|
||||
]
|
||||
self.sink, self.source = self.tx.sink, self.rx.source
|
||||
|
|
@ -0,0 +1,254 @@
|
|||
from litesata.common import *
|
||||
from litesata.core.link.crc import LiteSATACRCInserter, LiteSATACRCChecker
|
||||
from litesata.core.link.scrambler import LiteSATAScrambler
|
||||
from litesata.core.link.cont import LiteSATACONTInserter, LiteSATACONTRemover
|
||||
|
||||
from_rx = [
|
||||
("idle", 1),
|
||||
("insert", 32),
|
||||
("det", 32)
|
||||
]
|
||||
|
||||
class LiteSATALinkTX(Module):
|
||||
def __init__(self, phy):
|
||||
self.sink = Sink(link_description(32))
|
||||
self.from_rx = Sink(from_rx)
|
||||
|
||||
###
|
||||
|
||||
self.fsm = fsm = FSM(reset_state="IDLE")
|
||||
self.submodules += fsm
|
||||
|
||||
# insert CRC
|
||||
crc = LiteSATACRCInserter(link_description(32))
|
||||
self.submodules += crc
|
||||
|
||||
# scramble
|
||||
scrambler = LiteSATAScrambler(link_description(32))
|
||||
self.submodules += scrambler
|
||||
|
||||
# connect CRC / scrambler
|
||||
self.comb += [
|
||||
Record.connect(self.sink, crc.sink),
|
||||
Record.connect(crc.source, scrambler.sink)
|
||||
]
|
||||
|
||||
# inserter CONT and scrambled data between
|
||||
# CONT and next primitive
|
||||
cont = BufferizeEndpoints(LiteSATACONTInserter(phy_description(32)), "source")
|
||||
self.submodules += cont
|
||||
|
||||
# datas / primitives mux
|
||||
insert = Signal(32)
|
||||
self.comb += [
|
||||
If(self.from_rx.insert,
|
||||
cont.sink.stb.eq(1),
|
||||
cont.sink.data.eq(self.from_rx.insert),
|
||||
cont.sink.charisk.eq(0x0001),
|
||||
).
|
||||
Elif(insert,
|
||||
cont.sink.stb.eq(1),
|
||||
cont.sink.data.eq(insert),
|
||||
cont.sink.charisk.eq(0x0001),
|
||||
).Elif(fsm.ongoing("COPY"),
|
||||
cont.sink.stb.eq(scrambler.source.stb),
|
||||
cont.sink.data.eq(scrambler.source.d),
|
||||
scrambler.source.ack.eq(cont.sink.ack),
|
||||
cont.sink.charisk.eq(0)
|
||||
)
|
||||
]
|
||||
self.comb += Record.connect(cont.source, phy.sink)
|
||||
|
||||
# FSM
|
||||
fsm.act("IDLE",
|
||||
scrambler.reset.eq(1),
|
||||
If(self.from_rx.idle,
|
||||
insert.eq(primitives["SYNC"]),
|
||||
If(scrambler.source.stb & scrambler.source.sop,
|
||||
If(self.from_rx.det == primitives["SYNC"],
|
||||
NextState("RDY")
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
fsm.act("RDY",
|
||||
insert.eq(primitives["X_RDY"]),
|
||||
If(~self.from_rx.idle,
|
||||
NextState("IDLE")
|
||||
).Elif(self.from_rx.det == primitives["R_RDY"],
|
||||
NextState("SOF")
|
||||
)
|
||||
)
|
||||
fsm.act("SOF",
|
||||
insert.eq(primitives["SOF"]),
|
||||
If(phy.sink.ack,
|
||||
NextState("COPY")
|
||||
)
|
||||
)
|
||||
fsm.act("COPY",
|
||||
If(self.from_rx.det == primitives["HOLD"],
|
||||
insert.eq(primitives["HOLDA"]),
|
||||
).Elif(~scrambler.source.stb,
|
||||
insert.eq(primitives["HOLD"]),
|
||||
).Elif(scrambler.source.stb & scrambler.source.eop & scrambler.source.ack,
|
||||
NextState("EOF")
|
||||
)
|
||||
)
|
||||
fsm.act("EOF",
|
||||
insert.eq(primitives["EOF"]),
|
||||
If(phy.sink.ack,
|
||||
NextState("WTRM")
|
||||
)
|
||||
)
|
||||
fsm.act("WTRM",
|
||||
insert.eq(primitives["WTRM"]),
|
||||
If(self.from_rx.det == primitives["R_OK"],
|
||||
NextState("IDLE")
|
||||
).Elif(self.from_rx.det == primitives["R_ERR"],
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
|
||||
class LiteSATALinkRX(Module):
|
||||
def __init__(self, phy):
|
||||
self.source = Source(link_description(32))
|
||||
self.hold = Signal()
|
||||
self.to_tx = Source(from_rx)
|
||||
|
||||
###
|
||||
|
||||
self.fsm = fsm = FSM(reset_state="IDLE")
|
||||
self.submodules += fsm
|
||||
|
||||
# CONT remover
|
||||
cont = BufferizeEndpoints(LiteSATACONTRemover(phy_description(32)), "source")
|
||||
self.submodules += cont
|
||||
self.comb += Record.connect(phy.source, cont.sink)
|
||||
|
||||
# datas / primitives detection
|
||||
insert = Signal(32)
|
||||
det = Signal(32)
|
||||
self.comb += \
|
||||
If(cont.source.stb & (cont.source.charisk == 0b0001),
|
||||
det.eq(cont.source.data)
|
||||
)
|
||||
|
||||
# descrambler
|
||||
scrambler = LiteSATAScrambler(link_description(32))
|
||||
self.submodules += scrambler
|
||||
|
||||
# check CRC
|
||||
crc = LiteSATACRCChecker(link_description(32))
|
||||
self.submodules += crc
|
||||
|
||||
sop = Signal()
|
||||
eop = Signal()
|
||||
self.sync += \
|
||||
If(fsm.ongoing("IDLE"),
|
||||
sop.eq(1),
|
||||
).Elif(fsm.ongoing("COPY"),
|
||||
If(scrambler.sink.stb & scrambler.sink.ack,
|
||||
sop.eq(0)
|
||||
)
|
||||
)
|
||||
self.comb += eop.eq(det == primitives["EOF"])
|
||||
|
||||
crc_error = Signal()
|
||||
self.sync += \
|
||||
If(crc.source.stb & crc.source.eop & crc.source.ack,
|
||||
crc_error.eq(crc.source.error)
|
||||
)
|
||||
|
||||
# graph
|
||||
self.comb += [
|
||||
cont.source.ack.eq(1),
|
||||
Record.connect(scrambler.source, crc.sink),
|
||||
Record.connect(crc.source, self.source),
|
||||
]
|
||||
cont_source_data_d = Signal(32)
|
||||
self.sync += \
|
||||
If(cont.source.stb & (det == 0),
|
||||
scrambler.sink.d.eq(cont.source.data)
|
||||
)
|
||||
|
||||
# FSM
|
||||
fsm.act("IDLE",
|
||||
scrambler.reset.eq(1),
|
||||
If(det == primitives["X_RDY"],
|
||||
NextState("RDY")
|
||||
)
|
||||
)
|
||||
fsm.act("RDY",
|
||||
insert.eq(primitives["R_RDY"]),
|
||||
If(det == primitives["SOF"],
|
||||
NextState("WAIT_FIRST")
|
||||
)
|
||||
)
|
||||
fsm.act("WAIT_FIRST",
|
||||
insert.eq(primitives["R_IP"]),
|
||||
If(cont.source.stb & (det == 0),
|
||||
NextState("COPY")
|
||||
)
|
||||
)
|
||||
self.comb += [
|
||||
scrambler.sink.sop.eq(sop),
|
||||
scrambler.sink.eop.eq(eop)
|
||||
]
|
||||
fsm.act("COPY",
|
||||
scrambler.sink.stb.eq(cont.source.stb & ((det == 0) | eop)),
|
||||
insert.eq(primitives["R_IP"]),
|
||||
If(det == primitives["HOLD"],
|
||||
insert.eq(primitives["HOLDA"])
|
||||
).Elif(det == primitives["EOF"],
|
||||
NextState("WTRM")
|
||||
).Elif(self.hold,
|
||||
insert.eq(primitives["HOLD"])
|
||||
)
|
||||
)
|
||||
fsm.act("EOF",
|
||||
insert.eq(primitives["R_IP"]),
|
||||
If(det == primitives["WTRM"],
|
||||
NextState("WTRM")
|
||||
)
|
||||
)
|
||||
fsm.act("WTRM",
|
||||
insert.eq(primitives["R_IP"]),
|
||||
If(~crc_error,
|
||||
NextState("R_OK")
|
||||
).Else(
|
||||
NextState("R_ERR")
|
||||
)
|
||||
)
|
||||
fsm.act("R_OK",
|
||||
insert.eq(primitives["R_OK"]),
|
||||
If(det == primitives["SYNC"],
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
fsm.act("R_ERR",
|
||||
insert.eq(primitives["R_ERR"]),
|
||||
If(det == primitives["SYNC"],
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
|
||||
# to TX
|
||||
self.comb += [
|
||||
self.to_tx.idle.eq(fsm.ongoing("IDLE")),
|
||||
self.to_tx.insert.eq(insert),
|
||||
self.to_tx.det.eq(det)
|
||||
]
|
||||
|
||||
class LiteSATALink(Module):
|
||||
def __init__(self, phy, buffer_depth):
|
||||
self.submodules.tx_buffer = PacketBuffer(link_description(32), buffer_depth)
|
||||
self.submodules.tx = LiteSATALinkTX(phy)
|
||||
self.submodules.rx = LiteSATALinkRX(phy)
|
||||
self.submodules.rx_buffer = PacketBuffer(link_description(32), buffer_depth, almost_full=3*buffer_depth//4)
|
||||
self.comb += [
|
||||
Record.connect(self.tx_buffer.source, self.tx.sink),
|
||||
Record.connect(self.rx.to_tx, self.tx.from_rx),
|
||||
Record.connect(self.rx.source, self.rx_buffer.sink),
|
||||
self.rx.hold.eq(self.rx_buffer.almost_full)
|
||||
]
|
||||
self.sink, self.source = self.tx_buffer.sink, self.rx_buffer.source
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
from litesata.common import *
|
||||
from litesata.core.link.scrambler import Scrambler
|
||||
|
||||
class LiteSATACONTInserter(Module):
|
||||
def __init__(self, description):
|
||||
self.sink = sink = Sink(description)
|
||||
self.source = source = Source(description)
|
||||
|
||||
###
|
||||
|
||||
counter = Counter(max=4)
|
||||
self.submodules += counter
|
||||
|
||||
is_data = Signal()
|
||||
was_data = Signal()
|
||||
was_hold = Signal()
|
||||
change = Signal()
|
||||
self.comb += is_data.eq(sink.charisk == 0)
|
||||
|
||||
last_data = Signal(32)
|
||||
last_primitive = Signal(32)
|
||||
last_charisk = Signal(4)
|
||||
self.sync += [
|
||||
If(sink.stb & source.ack,
|
||||
last_data.eq(sink.data),
|
||||
last_charisk.eq(sink.charisk),
|
||||
If(~is_data,
|
||||
last_primitive.eq(sink.data),
|
||||
),
|
||||
was_data.eq(is_data),
|
||||
was_hold.eq(last_primitive == primitives["HOLD"])
|
||||
)
|
||||
]
|
||||
self.comb += change.eq(
|
||||
(sink.data != last_data) |
|
||||
(sink.charisk != last_charisk) |
|
||||
is_data
|
||||
)
|
||||
|
||||
# scrambler
|
||||
scrambler = InsertReset(Scrambler())
|
||||
self.submodules += scrambler
|
||||
|
||||
# Datapath
|
||||
self.comb += [
|
||||
Record.connect(sink, source),
|
||||
If(sink.stb,
|
||||
If(~change,
|
||||
counter.ce.eq(sink.ack & (counter.value !=2)),
|
||||
# insert CONT
|
||||
If(counter.value == 1,
|
||||
source.charisk.eq(0b0001),
|
||||
source.data.eq(primitives["CONT"])
|
||||
# insert scrambled data for EMI
|
||||
).Elif(counter.value == 2,
|
||||
scrambler.ce.eq(sink.ack),
|
||||
source.charisk.eq(0b0000),
|
||||
source.data.eq(scrambler.value)
|
||||
)
|
||||
).Else(
|
||||
counter.reset.eq(source.ack),
|
||||
If(counter.value == 2,
|
||||
# Reinsert last primitive
|
||||
If(is_data | (~is_data & was_hold),
|
||||
source.stb.eq(1),
|
||||
sink.ack.eq(0),
|
||||
source.charisk.eq(0b0001),
|
||||
source.data.eq(last_primitive)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
]
|
||||
|
||||
class LiteSATACONTRemover(Module):
|
||||
def __init__(self, description):
|
||||
self.sink = sink = Sink(description)
|
||||
self.source = source = Source(description)
|
||||
|
||||
###
|
||||
|
||||
is_data = Signal()
|
||||
is_cont = Signal()
|
||||
in_cont = Signal()
|
||||
cont_ongoing = Signal()
|
||||
|
||||
self.comb += [
|
||||
is_data.eq(sink.charisk == 0),
|
||||
is_cont.eq(~is_data & (sink.data == primitives["CONT"]))
|
||||
]
|
||||
self.sync += \
|
||||
If(sink.stb & sink.ack,
|
||||
If(is_cont,
|
||||
in_cont.eq(1)
|
||||
).Elif(~is_data,
|
||||
in_cont.eq(0)
|
||||
)
|
||||
)
|
||||
self.comb += cont_ongoing.eq(is_cont | (in_cont & is_data))
|
||||
|
||||
# Datapath
|
||||
last_primitive = Signal(32)
|
||||
self.sync += [
|
||||
If(sink.stb & sink.ack,
|
||||
If(~is_data & ~is_cont,
|
||||
last_primitive.eq(sink.data)
|
||||
)
|
||||
)
|
||||
]
|
||||
self.comb += [
|
||||
Record.connect(sink, source),
|
||||
If(cont_ongoing,
|
||||
source.charisk.eq(0b0001),
|
||||
source.data.eq(last_primitive)
|
||||
)
|
||||
]
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
from collections import OrderedDict
|
||||
from litesata.common import *
|
||||
|
||||
from migen.actorlib.crc import CRCInserter, CRCChecker
|
||||
|
||||
class CRCEngine(Module):
|
||||
"""Cyclic Redundancy Check Engine
|
||||
|
||||
Compute next CRC value from last CRC value and data input using
|
||||
an optimized asynchronous LFSR.
|
||||
|
||||
Parameters
|
||||
----------
|
||||
width : int
|
||||
Width of the data bus and CRC.
|
||||
polynom : int
|
||||
Polynom of the CRC (ex: 0x04C11DB7 for IEEE 802.3 CRC)
|
||||
|
||||
Attributes
|
||||
----------
|
||||
d : in
|
||||
Data input.
|
||||
last : in
|
||||
last CRC value.
|
||||
next :
|
||||
next CRC value.
|
||||
"""
|
||||
def __init__(self, width, polynom):
|
||||
self.d = Signal(width)
|
||||
self.last = Signal(width)
|
||||
self.next = Signal(width)
|
||||
|
||||
###
|
||||
|
||||
def _optimize_eq(l):
|
||||
"""
|
||||
Replace even numbers of XORs in the equation
|
||||
with an equivalent XOR
|
||||
"""
|
||||
d = OrderedDict()
|
||||
for e in l:
|
||||
if e in d:
|
||||
d[e] += 1
|
||||
else:
|
||||
d[e] = 1
|
||||
r = []
|
||||
for key, value in d.items():
|
||||
if value%2 != 0:
|
||||
r.append(key)
|
||||
return r
|
||||
|
||||
new = Signal(32)
|
||||
self.comb += new.eq(self.last ^ self.d)
|
||||
|
||||
# compute and optimize CRC's LFSR
|
||||
curval = [[("new", i)] for i in range(width)]
|
||||
for i in range(width):
|
||||
feedback = curval.pop()
|
||||
for j in range(width-1):
|
||||
if (polynom & (1<<(j+1))):
|
||||
curval[j] += feedback
|
||||
curval[j] = _optimize_eq(curval[j])
|
||||
curval.insert(0, feedback)
|
||||
|
||||
# implement logic
|
||||
for i in range(width):
|
||||
xors = []
|
||||
for t, n in curval[i]:
|
||||
if t == "new":
|
||||
xors += [new[n]]
|
||||
self.comb += self.next[i].eq(optree("^", xors))
|
||||
|
||||
@DecorateModule(InsertReset)
|
||||
@DecorateModule(InsertCE)
|
||||
class LiteSATACRC(Module):
|
||||
"""SATA CRC
|
||||
|
||||
Implement a SATA CRC generator/checker
|
||||
|
||||
Attributes
|
||||
----------
|
||||
value : out
|
||||
CRC value (used for generator).
|
||||
error : out
|
||||
CRC error (used for checker).
|
||||
"""
|
||||
width = 32
|
||||
polynom = 0x04C11DB7
|
||||
init = 0x52325032
|
||||
check = 0x00000000
|
||||
def __init__(self, dw=32):
|
||||
self.d = Signal(self.width)
|
||||
self.value = Signal(self.width)
|
||||
self.error = Signal()
|
||||
|
||||
###
|
||||
|
||||
engine = CRCEngine(self.width, self.polynom)
|
||||
self.submodules += engine
|
||||
reg_i = Signal(self.width, reset=self.init)
|
||||
self.sync += reg_i.eq(engine.next)
|
||||
self.comb += [
|
||||
engine.d.eq(self.d),
|
||||
engine.last.eq(reg_i),
|
||||
|
||||
self.value.eq(reg_i),
|
||||
self.error.eq(engine.next != self.check)
|
||||
]
|
||||
|
||||
class LiteSATACRCInserter(CRCInserter):
|
||||
def __init__(self, description):
|
||||
CRCInserter.__init__(self, LiteSATACRC, description)
|
||||
|
||||
class LiteSATACRCChecker(CRCChecker):
|
||||
def __init__(self, description):
|
||||
CRCChecker.__init__(self, LiteSATACRC, description)
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
from litesata.common import *
|
||||
|
||||
@DecorateModule(InsertCE)
|
||||
class Scrambler(Module):
|
||||
"""SATA Scrambler
|
||||
|
||||
Implement a SATA Scrambler
|
||||
|
||||
Attributes
|
||||
----------
|
||||
value : out
|
||||
Scrambled value.
|
||||
"""
|
||||
def __init__(self):
|
||||
self.value = Signal(32)
|
||||
|
||||
###
|
||||
|
||||
context = Signal(16, reset=0xf0f6)
|
||||
next_value = Signal(32)
|
||||
self.sync += context.eq(next_value[16:32])
|
||||
|
||||
# XXX: from SATA specification, replace it with
|
||||
# a generic implementation using polynoms.
|
||||
lfsr_coefs = (
|
||||
(15, 13, 4, 0), #0
|
||||
(15, 14, 13, 5, 4, 1, 0),
|
||||
(14, 13, 6, 5, 4, 2,1, 0),
|
||||
(15, 14, 7, 6, 5, 3,2, 1),
|
||||
(13, 8, 7, 6, 3, 2, 0),
|
||||
(14, 9, 8, 7, 4, 3, 1),
|
||||
(15, 10, 9, 8, 5, 4, 2),
|
||||
(15, 13, 11, 10, 9, 6, 5, 4, 3, 0),
|
||||
(15, 14, 13, 12, 11, 10,7, 6, 5, 1, 0),
|
||||
(14, 12, 11, 8, 7, 6, 4, 2, 1, 0),
|
||||
(15, 13, 12, 9, 8, 7, 5, 3, 2, 1),
|
||||
(15, 14, 10, 9, 8, 6, 3, 2, 0),
|
||||
(13, 11, 10, 9, 7, 3, 1, 0),
|
||||
(14, 12, 11, 10, 8, 4, 2, 1),
|
||||
(15, 13, 12, 11, 9, 5, 3, 2),
|
||||
(15, 14, 12, 10, 6, 3, 0),
|
||||
|
||||
(11, 7, 1, 0), #16
|
||||
(12, 8, 2, 1),
|
||||
(13, 9, 3, 2),
|
||||
(14, 10, 4, 3),
|
||||
(15, 11, 5, 4),
|
||||
(15, 13, 12, 6, 5, 4, 0),
|
||||
(15, 14, 7, 6, 5, 4, 1, 0),
|
||||
(13, 8, 7, 6, 5, 4, 2, 1, 0),
|
||||
(14, 9, 8,7, 6, 5, 3, 2, 1),
|
||||
(15, 10, 9, 8, 7, 6, 4, 3, 2),
|
||||
(15, 13, 11, 10, 9, 8, 7, 5, 3, 0),
|
||||
(15, 14, 13, 12, 11, 10, 9, 8, 6, 1, 0),
|
||||
(14, 12, 11, 10, 9, 7, 4, 2, 1, 0),
|
||||
(15, 13, 12, 11, 10, 8, 5, 3, 2, 1),
|
||||
(15, 14, 12, 11, 9, 6, 3, 2, 0),
|
||||
(12, 10, 7, 3, 1, 0),
|
||||
)
|
||||
|
||||
for n, coefs in enumerate(lfsr_coefs):
|
||||
eq = [context[i] for i in coefs]
|
||||
self.comb += next_value[n].eq(optree("^", eq))
|
||||
|
||||
self.comb += self.value.eq(next_value)
|
||||
|
||||
@DecorateModule(InsertReset)
|
||||
class LiteSATAScrambler(Module):
|
||||
def __init__(self, description):
|
||||
self.sink = sink = Sink(description)
|
||||
self.source = source = Source(description)
|
||||
|
||||
###
|
||||
|
||||
scrambler = Scrambler()
|
||||
self.submodules += scrambler
|
||||
self.comb += [
|
||||
scrambler.ce.eq(sink.stb & sink.ack),
|
||||
Record.connect(sink, source),
|
||||
source.d.eq(sink.d ^ scrambler.value)
|
||||
]
|
||||
|
|
@ -0,0 +1,257 @@
|
|||
from litesata.common import *
|
||||
|
||||
def _get_item(obj, name, width):
|
||||
if "_lsb" in name:
|
||||
item = getattr(obj, name.replace("_lsb", ""))[:width]
|
||||
elif "_msb" in name:
|
||||
item = getattr(obj, name.replace("_msb", ""))[width:2*width]
|
||||
else:
|
||||
item = getattr(obj, name)
|
||||
return item
|
||||
|
||||
def _encode_cmd(obj, description, signal):
|
||||
r = []
|
||||
for k, v in sorted(description.items()):
|
||||
start = v.dword*32 + v.offset
|
||||
end = start + v.width
|
||||
item = _get_item(obj, k, v.width)
|
||||
r.append(signal[start:end].eq(item))
|
||||
return r
|
||||
|
||||
def test_type(name, signal):
|
||||
return signal == fis_types[name]
|
||||
|
||||
class LiteSATATransportTX(Module):
|
||||
def __init__(self, link):
|
||||
self.sink = sink = Sink(transport_tx_description(32))
|
||||
|
||||
###
|
||||
|
||||
cmd_ndwords = max(fis_reg_h2d_cmd_len, fis_data_cmd_len)
|
||||
encoded_cmd = Signal(cmd_ndwords*32)
|
||||
|
||||
counter = Counter(max=cmd_ndwords+1)
|
||||
self.submodules += counter
|
||||
|
||||
cmd_len = Signal(counter.width)
|
||||
cmd_with_data = Signal()
|
||||
|
||||
cmd_send = Signal()
|
||||
data_send = Signal()
|
||||
cmd_done = Signal()
|
||||
|
||||
fis_type = Signal(8)
|
||||
update_fis_type = Signal()
|
||||
|
||||
def test_type_tx(name):
|
||||
return test_type(name, sink.type)
|
||||
|
||||
self.fsm = fsm = FSM(reset_state="IDLE")
|
||||
self.submodules += fsm
|
||||
fsm.act("IDLE",
|
||||
sink.ack.eq(0),
|
||||
counter.reset.eq(1),
|
||||
update_fis_type.eq(1),
|
||||
If(sink.stb & sink.sop,
|
||||
If(test_type_tx("REG_H2D"),
|
||||
NextState("SEND_CTRL_CMD")
|
||||
).Elif(test_type_tx("DATA"),
|
||||
NextState("SEND_DATA_CMD")
|
||||
).Else(
|
||||
sink.ack.eq(1)
|
||||
)
|
||||
).Else(
|
||||
sink.ack.eq(1)
|
||||
)
|
||||
)
|
||||
self.sync += \
|
||||
If(update_fis_type, fis_type.eq(link.source.d[:8]))
|
||||
|
||||
fsm.act("SEND_CTRL_CMD",
|
||||
_encode_cmd(sink, fis_reg_h2d_layout, encoded_cmd),
|
||||
cmd_len.eq(fis_reg_h2d_cmd_len-1),
|
||||
cmd_send.eq(1),
|
||||
If(cmd_done,
|
||||
sink.ack.eq(1),
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
fsm.act("SEND_DATA_CMD",
|
||||
sink.ack.eq(0),
|
||||
_encode_cmd(sink, fis_data_layout, encoded_cmd),
|
||||
cmd_len.eq(fis_data_cmd_len-1),
|
||||
cmd_with_data.eq(1),
|
||||
cmd_send.eq(1),
|
||||
If(cmd_done,
|
||||
NextState("SEND_DATA")
|
||||
)
|
||||
)
|
||||
fsm.act("SEND_DATA",
|
||||
data_send.eq(1),
|
||||
sink.ack.eq(link.sink.ack),
|
||||
If(sink.stb & sink.eop & sink.ack,
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
|
||||
cmd_cases = {}
|
||||
for i in range(cmd_ndwords):
|
||||
cmd_cases[i] = [link.sink.d.eq(encoded_cmd[32*i:32*(i+1)])]
|
||||
|
||||
self.comb += [
|
||||
counter.ce.eq(sink.stb & link.sink.ack),
|
||||
cmd_done.eq((counter.value == cmd_len) & link.sink.stb & link.sink.ack),
|
||||
If(cmd_send,
|
||||
link.sink.stb.eq(sink.stb),
|
||||
link.sink.sop.eq(counter.value == 0),
|
||||
link.sink.eop.eq((counter.value == cmd_len) & ~cmd_with_data),
|
||||
Case(counter.value, cmd_cases)
|
||||
).Elif(data_send,
|
||||
link.sink.stb.eq(sink.stb),
|
||||
link.sink.sop.eq(0),
|
||||
link.sink.eop.eq(sink.eop),
|
||||
link.sink.d.eq(sink.data)
|
||||
)
|
||||
]
|
||||
|
||||
def _decode_cmd(signal, description, obj):
|
||||
r = []
|
||||
for k, v in sorted(description.items()):
|
||||
start = v.dword*32+v.offset
|
||||
end = start+v.width
|
||||
item = _get_item(obj, k, v.width)
|
||||
r.append(item.eq(signal[start:end]))
|
||||
return r
|
||||
|
||||
class LiteSATATransportRX(Module):
|
||||
def __init__(self, link):
|
||||
self.source = source = Source(transport_rx_description(32))
|
||||
|
||||
###
|
||||
|
||||
cmd_ndwords = max(fis_reg_d2h_cmd_len, fis_dma_activate_d2h_cmd_len,
|
||||
fis_pio_setup_d2h_cmd_len, fis_data_cmd_len)
|
||||
encoded_cmd = Signal(cmd_ndwords*32)
|
||||
|
||||
counter = Counter(max=cmd_ndwords+1)
|
||||
self.submodules += counter
|
||||
|
||||
cmd_len = Signal(counter.width)
|
||||
|
||||
cmd_receive = Signal()
|
||||
data_receive = Signal()
|
||||
cmd_done = Signal()
|
||||
data_done = Signal()
|
||||
|
||||
def test_type_rx(name):
|
||||
return test_type(name, link.source.d[:8])
|
||||
|
||||
self.fsm = fsm = FSM(reset_state="IDLE")
|
||||
self.submodules += fsm
|
||||
|
||||
data_sop = Signal()
|
||||
fis_type = Signal(8)
|
||||
update_fis_type = Signal()
|
||||
|
||||
fsm.act("IDLE",
|
||||
link.source.ack.eq(0),
|
||||
counter.reset.eq(1),
|
||||
update_fis_type.eq(1),
|
||||
If(link.source.stb & link.source.sop,
|
||||
If(test_type_rx("REG_D2H"),
|
||||
NextState("RECEIVE_CTRL_CMD")
|
||||
).Elif(test_type_rx("DMA_ACTIVATE_D2H"),
|
||||
NextState("RECEIVE_CTRL_CMD")
|
||||
).Elif(test_type_rx("PIO_SETUP_D2H"),
|
||||
NextState("RECEIVE_CTRL_CMD")
|
||||
).Elif(test_type_rx("DATA"),
|
||||
NextState("RECEIVE_DATA_CMD"),
|
||||
).Else(
|
||||
link.source.ack.eq(1)
|
||||
)
|
||||
).Else(
|
||||
link.source.ack.eq(1)
|
||||
)
|
||||
)
|
||||
self.sync += \
|
||||
If(update_fis_type, fis_type.eq(link.source.d[:8]))
|
||||
|
||||
fsm.act("RECEIVE_CTRL_CMD",
|
||||
If(test_type("REG_D2H", fis_type),
|
||||
cmd_len.eq(fis_reg_d2h_cmd_len-1)
|
||||
).Elif(test_type("DMA_ACTIVATE_D2H", fis_type),
|
||||
cmd_len.eq(fis_dma_activate_d2h_cmd_len-1)
|
||||
).Else(
|
||||
cmd_len.eq(fis_pio_setup_d2h_cmd_len-1)
|
||||
),
|
||||
cmd_receive.eq(1),
|
||||
link.source.ack.eq(1),
|
||||
If(cmd_done,
|
||||
NextState("PRESENT_CTRL_CMD")
|
||||
)
|
||||
)
|
||||
fsm.act("PRESENT_CTRL_CMD",
|
||||
source.stb.eq(1),
|
||||
source.sop.eq(1),
|
||||
source.eop.eq(1),
|
||||
If(test_type("REG_D2H", fis_type),
|
||||
_decode_cmd(encoded_cmd, fis_reg_d2h_layout, source),
|
||||
).Elif(test_type("DMA_ACTIVATE_D2H", fis_type),
|
||||
_decode_cmd(encoded_cmd, fis_dma_activate_d2h_layout, source),
|
||||
).Else(
|
||||
_decode_cmd(encoded_cmd, fis_pio_setup_d2h_layout, source),
|
||||
),
|
||||
If(source.stb & source.ack,
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
fsm.act("RECEIVE_DATA_CMD",
|
||||
cmd_len.eq(fis_data_cmd_len-1),
|
||||
cmd_receive.eq(1),
|
||||
link.source.ack.eq(1),
|
||||
If(cmd_done,
|
||||
NextState("PRESENT_DATA")
|
||||
)
|
||||
)
|
||||
fsm.act("PRESENT_DATA",
|
||||
data_receive.eq(1),
|
||||
source.stb.eq(link.source.stb),
|
||||
_decode_cmd(encoded_cmd, fis_data_layout, source),
|
||||
source.sop.eq(data_sop),
|
||||
source.eop.eq(link.source.eop),
|
||||
source.error.eq(link.source.error),
|
||||
source.data.eq(link.source.d),
|
||||
link.source.ack.eq(source.ack),
|
||||
If(source.stb & source.eop & source.ack,
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
|
||||
self.sync += \
|
||||
If(fsm.ongoing("RECEIVE_DATA_CMD"),
|
||||
data_sop.eq(1)
|
||||
).Elif(fsm.ongoing("PRESENT_DATA"),
|
||||
If(source.stb & source.ack,
|
||||
data_sop.eq(0)
|
||||
)
|
||||
)
|
||||
|
||||
cmd_cases = {}
|
||||
for i in range(cmd_ndwords):
|
||||
cmd_cases[i] = [encoded_cmd[32*i:32*(i+1)].eq(link.source.d)]
|
||||
|
||||
self.comb += \
|
||||
If(cmd_receive & link.source.stb,
|
||||
counter.ce.eq(1)
|
||||
)
|
||||
self.sync += \
|
||||
If(cmd_receive,
|
||||
Case(counter.value, cmd_cases),
|
||||
)
|
||||
self.comb += cmd_done.eq((counter.value == cmd_len) & link.source.ack)
|
||||
|
||||
class LiteSATATransport(Module):
|
||||
def __init__(self, link):
|
||||
self.submodules.tx = LiteSATATransportTX(link)
|
||||
self.submodules.rx = LiteSATATransportRX(link)
|
||||
self.sink, self.source = self.tx.sink, self.rx.source
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
from litesata.common import *
|
||||
from litesata.frontend.crossbar import LiteSATACrossbar
|
||||
from litesata.frontend.arbiter import LiteSATAArbiter
|
||||
from litesata.frontend.bist import LiteSATABIST
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
from litesata.common import *
|
||||
from litesata.frontend.common import *
|
||||
|
||||
from migen.genlib.roundrobin import *
|
||||
|
||||
class LiteSATAArbiter(Module):
|
||||
def __init__(self, users, master):
|
||||
self.rr = RoundRobin(len(users))
|
||||
self.submodules += self.rr
|
||||
self.grant = self.rr.grant
|
||||
cases = {}
|
||||
for i, slave in enumerate(users):
|
||||
sink, source = slave.sink, slave.source
|
||||
start = Signal()
|
||||
done = Signal()
|
||||
ongoing = Signal()
|
||||
self.comb += [
|
||||
start.eq(sink.stb & sink.sop),
|
||||
done.eq(source.stb & source.last & source.eop & source.ack)
|
||||
]
|
||||
self.sync += \
|
||||
If(start,
|
||||
ongoing.eq(1)
|
||||
).Elif(done,
|
||||
ongoing.eq(0)
|
||||
)
|
||||
self.comb += self.rr.request[i].eq((start | ongoing) & ~done)
|
||||
cases[i] = [users[i].connect(master)]
|
||||
self.comb += Case(self.grant, cases)
|
||||
|
|
@ -0,0 +1,294 @@
|
|||
from litesata.common import *
|
||||
from litesata.core.link.scrambler import Scrambler
|
||||
|
||||
from migen.fhdl.decorators import ModuleDecorator
|
||||
from migen.bank.description import *
|
||||
|
||||
class LiteSATABISTGenerator(Module):
|
||||
def __init__(self, user_port):
|
||||
self.start = Signal()
|
||||
self.sector = Signal(48)
|
||||
self.count = Signal(16)
|
||||
self.random = Signal()
|
||||
|
||||
self.done = Signal()
|
||||
self.aborted = Signal()
|
||||
self.errors = Signal(32) # Note: Not used for writes
|
||||
|
||||
###
|
||||
|
||||
source, sink = user_port.sink, user_port.source
|
||||
|
||||
counter = Counter(bits_sign=32)
|
||||
self.submodules += counter
|
||||
|
||||
scrambler = scrambler = InsertReset(Scrambler())
|
||||
self.submodules += scrambler
|
||||
self.comb += [
|
||||
scrambler.reset.eq(counter.reset),
|
||||
scrambler.ce.eq(counter.ce)
|
||||
]
|
||||
|
||||
self.fsm = fsm = FSM(reset_state="IDLE")
|
||||
self.submodules += fsm
|
||||
fsm.act("IDLE",
|
||||
self.done.eq(1),
|
||||
counter.reset.eq(1),
|
||||
If(self.start,
|
||||
NextState("SEND_CMD_AND_DATA")
|
||||
)
|
||||
)
|
||||
self.comb += [
|
||||
source.sop.eq(counter.value == 0),
|
||||
source.eop.eq(counter.value == (logical_sector_size//4*self.count)-1),
|
||||
source.write.eq(1),
|
||||
source.sector.eq(self.sector),
|
||||
source.count.eq(self.count),
|
||||
If(self.random,
|
||||
source.data.eq(scrambler.value)
|
||||
).Else(
|
||||
source.data.eq(counter.value)
|
||||
)
|
||||
]
|
||||
fsm.act("SEND_CMD_AND_DATA",
|
||||
source.stb.eq(1),
|
||||
If(source.stb & source.ack,
|
||||
counter.ce.eq(1),
|
||||
If(source.eop,
|
||||
NextState("WAIT_ACK")
|
||||
)
|
||||
)
|
||||
)
|
||||
fsm.act("WAIT_ACK",
|
||||
sink.ack.eq(1),
|
||||
If(sink.stb,
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
self.sync += If(sink.stb & sink.ack, self.aborted.eq(sink.failed))
|
||||
|
||||
class LiteSATABISTChecker(Module):
|
||||
def __init__(self, user_port):
|
||||
self.start = Signal()
|
||||
self.sector = Signal(48)
|
||||
self.count = Signal(16)
|
||||
self.random = Signal()
|
||||
|
||||
self.done = Signal()
|
||||
self.aborted = Signal()
|
||||
self.errors = Signal(32)
|
||||
|
||||
###
|
||||
|
||||
source, sink = user_port.sink, user_port.source
|
||||
|
||||
counter = Counter(bits_sign=32)
|
||||
error_counter = Counter(self.errors, bits_sign=32)
|
||||
self.submodules += counter, error_counter
|
||||
|
||||
scrambler = InsertReset(Scrambler())
|
||||
self.submodules += scrambler
|
||||
self.comb += [
|
||||
scrambler.reset.eq(counter.reset),
|
||||
scrambler.ce.eq(counter.ce)
|
||||
]
|
||||
|
||||
self.fsm = fsm = FSM(reset_state="IDLE")
|
||||
self.submodules += self.fsm
|
||||
fsm.act("IDLE",
|
||||
self.done.eq(1),
|
||||
counter.reset.eq(1),
|
||||
If(self.start,
|
||||
error_counter.reset.eq(1),
|
||||
NextState("SEND_CMD")
|
||||
)
|
||||
)
|
||||
self.comb += [
|
||||
source.sop.eq(1),
|
||||
source.eop.eq(1),
|
||||
source.read.eq(1),
|
||||
source.sector.eq(self.sector),
|
||||
source.count.eq(self.count),
|
||||
]
|
||||
fsm.act("SEND_CMD",
|
||||
source.stb.eq(1),
|
||||
If(source.ack,
|
||||
counter.reset.eq(1),
|
||||
NextState("WAIT_ACK")
|
||||
)
|
||||
)
|
||||
fsm.act("WAIT_ACK",
|
||||
If(sink.stb & sink.read,
|
||||
NextState("RECEIVE_DATA")
|
||||
)
|
||||
)
|
||||
expected_data = Signal(32)
|
||||
self.comb += \
|
||||
If(self.random,
|
||||
expected_data.eq(scrambler.value)
|
||||
).Else(
|
||||
expected_data.eq(counter.value)
|
||||
)
|
||||
fsm.act("RECEIVE_DATA",
|
||||
sink.ack.eq(1),
|
||||
If(sink.stb,
|
||||
counter.ce.eq(1),
|
||||
If(sink.data != expected_data,
|
||||
error_counter.ce.eq(~sink.last)
|
||||
),
|
||||
If(sink.eop,
|
||||
If(sink.last,
|
||||
NextState("IDLE")
|
||||
).Else(
|
||||
NextState("WAIT_ACK")
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
self.sync += If(sink.stb & sink.ack, self.aborted.eq(sink.failed))
|
||||
|
||||
class LiteSATABISTUnitCSR(Module, AutoCSR):
|
||||
def __init__(self, bist_unit):
|
||||
self._start = CSR()
|
||||
self._sector = CSRStorage(48)
|
||||
self._count = CSRStorage(16)
|
||||
self._loops = CSRStorage(8)
|
||||
self._random = CSRStorage()
|
||||
|
||||
self._done = CSRStatus()
|
||||
self._aborted = CSRStatus()
|
||||
self._errors = CSRStatus(32)
|
||||
self._cycles = CSRStatus(32)
|
||||
|
||||
###
|
||||
|
||||
self.submodules += bist_unit
|
||||
|
||||
start = self._start.r & self._start.re
|
||||
done = self._done.status
|
||||
loops = self._loops.storage
|
||||
|
||||
self.comb += [
|
||||
bist_unit.sector.eq(self._sector.storage),
|
||||
bist_unit.count.eq(self._count.storage),
|
||||
bist_unit.random.eq(self._random.storage),
|
||||
|
||||
self._aborted.status.eq(bist_unit.aborted),
|
||||
self._errors.status.eq(bist_unit.errors)
|
||||
]
|
||||
|
||||
self.fsm = fsm = FSM(reset_state="IDLE")
|
||||
loop_counter = Counter(bits_sign=8)
|
||||
self.submodules += fsm, loop_counter
|
||||
fsm.act("IDLE",
|
||||
self._done.status.eq(1),
|
||||
loop_counter.reset.eq(1),
|
||||
If(start,
|
||||
NextState("CHECK")
|
||||
)
|
||||
)
|
||||
fsm.act("CHECK",
|
||||
If(loop_counter.value < loops,
|
||||
NextState("START")
|
||||
).Else(
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
fsm.act("START",
|
||||
bist_unit.start.eq(1),
|
||||
NextState("WAIT_DONE")
|
||||
)
|
||||
fsm.act("WAIT_DONE",
|
||||
If(bist_unit.done,
|
||||
loop_counter.ce.eq(1),
|
||||
NextState("CHECK")
|
||||
)
|
||||
)
|
||||
|
||||
cycles_counter = Counter(self._cycles.status)
|
||||
self.submodules += cycles_counter
|
||||
self.sync += [
|
||||
cycles_counter.reset.eq(start),
|
||||
cycles_counter.ce.eq(~fsm.ongoing("IDLE"))
|
||||
]
|
||||
|
||||
class LiteSATABISTIdentify(Module):
|
||||
def __init__(self, user_port):
|
||||
self.start = Signal()
|
||||
self.done = Signal()
|
||||
|
||||
fifo = SyncFIFO([("data", 32)], 512, buffered=True)
|
||||
self.submodules += fifo
|
||||
self.source = fifo.source
|
||||
|
||||
###
|
||||
|
||||
source, sink = user_port.sink, user_port.source
|
||||
|
||||
self.fsm = fsm = FSM(reset_state="IDLE")
|
||||
self.submodules += fsm
|
||||
fsm.act("IDLE",
|
||||
self.done.eq(1),
|
||||
If(self.start,
|
||||
NextState("SEND_CMD")
|
||||
)
|
||||
)
|
||||
self.comb += [
|
||||
source.sop.eq(1),
|
||||
source.eop.eq(1),
|
||||
source.identify.eq(1),
|
||||
]
|
||||
fsm.act("SEND_CMD",
|
||||
source.stb.eq(1),
|
||||
If(source.stb & source.ack,
|
||||
NextState("WAIT_ACK")
|
||||
)
|
||||
)
|
||||
fsm.act("WAIT_ACK",
|
||||
If(sink.stb & sink.identify,
|
||||
NextState("RECEIVE_DATA")
|
||||
)
|
||||
)
|
||||
self.comb += fifo.sink.data.eq(sink.data)
|
||||
fsm.act("RECEIVE_DATA",
|
||||
sink.ack.eq(fifo.sink.ack),
|
||||
If(sink.stb,
|
||||
fifo.sink.stb.eq(1),
|
||||
If(sink.eop,
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
class LiteSATABISTIdentifyCSR(Module, AutoCSR):
|
||||
def __init__(self, bist_identify):
|
||||
self._start = CSR()
|
||||
self._done = CSRStatus()
|
||||
self._source_stb = CSRStatus()
|
||||
self._source_ack = CSR()
|
||||
self._source_data = CSRStatus(32)
|
||||
|
||||
###
|
||||
|
||||
self.submodules += bist_identify
|
||||
self.comb += [
|
||||
bist_identify.start.eq(self._start.r & self._start.re),
|
||||
self._done.status.eq(bist_identify.done),
|
||||
|
||||
self._source_stb.status.eq(bist_identify.source.stb),
|
||||
self._source_data.status.eq(bist_identify.source.data),
|
||||
bist_identify.source.ack.eq(self._source_ack.r & self._source_ack.re)
|
||||
]
|
||||
|
||||
class LiteSATABIST(Module, AutoCSR):
|
||||
def __init__(self, crossbar, with_csr=False):
|
||||
generator = LiteSATABISTGenerator(crossbar.get_port())
|
||||
checker = LiteSATABISTChecker(crossbar.get_port())
|
||||
identify = LiteSATABISTIdentify(crossbar.get_port())
|
||||
if with_csr:
|
||||
generator = LiteSATABISTUnitCSR(generator)
|
||||
checker = LiteSATABISTUnitCSR(checker)
|
||||
identify = LiteSATABISTIdentifyCSR(identify)
|
||||
self.submodules.generator = generator
|
||||
self.submodules.checker = checker
|
||||
self.submodules.identify = identify
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
from litesata.common import *
|
||||
|
||||
class LiteSATAMasterPort:
|
||||
def __init__(self, dw):
|
||||
self.source = Source(command_tx_description(dw))
|
||||
self.sink = Sink(command_rx_description(dw))
|
||||
|
||||
def connect(self, slave):
|
||||
return [
|
||||
Record.connect(self.source, slave.sink),
|
||||
Record.connect(slave.source, self.sink)
|
||||
]
|
||||
|
||||
class LiteSATASlavePort:
|
||||
def __init__(self, dw):
|
||||
self.sink = Sink(command_tx_description(dw))
|
||||
self.source = Source(command_rx_description(dw))
|
||||
|
||||
def connect(self, master):
|
||||
return [
|
||||
Record.connect(self.sink, master.source),
|
||||
Record.connect(master.sink, self.source)
|
||||
]
|
||||
|
||||
class LiteSATAUserPort(LiteSATASlavePort):
|
||||
def __init__(self, dw):
|
||||
LiteSATASlavePort.__init__(self, dw)
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
from litesata.common import *
|
||||
from litesata.frontend.common import *
|
||||
from litesata.frontend.arbiter import LiteSATAArbiter
|
||||
|
||||
class LiteSATACrossbar(Module):
|
||||
def __init__(self, core):
|
||||
self.users = []
|
||||
self.master = LiteSATAMasterPort(32)
|
||||
self.comb += [
|
||||
self.master.source.connect(core.sink),
|
||||
core.source.connect(self.master.sink)
|
||||
]
|
||||
|
||||
def get_port(self):
|
||||
port = LiteSATAUserPort(32)
|
||||
self.users += [port]
|
||||
return port
|
||||
|
||||
def get_ports(self, n):
|
||||
ports = []
|
||||
for i in range(n):
|
||||
ports.append(self.get_port())
|
||||
return ports
|
||||
|
||||
def do_finalize(self):
|
||||
arbiter = LiteSATAArbiter(self.users, self.master)
|
||||
self.submodules += arbiter
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
from litesata.common import *
|
||||
from litesata.phy.ctrl import *
|
||||
from litesata.phy.datapath import *
|
||||
|
||||
class LiteSATAPHY(Module):
|
||||
def __init__(self, device, pads, revision, clk_freq):
|
||||
self.pads = pads
|
||||
self.revision = revision
|
||||
# Transceiver / Clocks
|
||||
if device[:3] == "xc7": # Kintex 7
|
||||
from litesata.phy.k7.trx import K7LiteSATAPHYTRX
|
||||
from litesata.phy.k7.crg import K7LiteSATAPHYCRG
|
||||
self.submodules.trx = K7LiteSATAPHYTRX(pads, revision)
|
||||
self.submodules.crg = K7LiteSATAPHYCRG(pads, self.trx, revision, clk_freq)
|
||||
else:
|
||||
msg = "Device" + device + "not (yet) supported."
|
||||
raise NotImplementedError(msg)
|
||||
|
||||
# Control
|
||||
self.submodules.ctrl = LiteSATAPHYCtrl(self.trx, self.crg, clk_freq)
|
||||
|
||||
# Datapath
|
||||
self.submodules.datapath = LiteSATAPHYDatapath(self.trx, self.ctrl)
|
||||
self.sink, self.source = self.datapath.sink, self.datapath.source
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
from litesata.common import *
|
||||
|
||||
def us(t, clk_freq):
|
||||
clk_period_us = 1000000/clk_freq
|
||||
return math.ceil(t/clk_period_us)
|
||||
|
||||
class LiteSATAPHYCtrl(Module):
|
||||
def __init__(self, trx, crg, clk_freq):
|
||||
self.ready = Signal()
|
||||
self.need_reset = Signal()
|
||||
self.sink = sink = Sink(phy_description(32))
|
||||
self.source = source = Source(phy_description(32))
|
||||
|
||||
###
|
||||
self.comb += [
|
||||
source.stb.eq(1),
|
||||
sink.ack.eq(1)
|
||||
]
|
||||
|
||||
retry_timeout = Timeout(us(10000, clk_freq))
|
||||
align_timeout = Timeout(us(873, clk_freq))
|
||||
self.submodules += align_timeout, retry_timeout
|
||||
|
||||
align_detect = Signal()
|
||||
non_align_cnt = Signal(4)
|
||||
|
||||
self.fsm = fsm = FSM(reset_state="RESET")
|
||||
self.submodules += fsm
|
||||
fsm.act("RESET",
|
||||
trx.tx_idle.eq(1),
|
||||
retry_timeout.reset.eq(1),
|
||||
align_timeout.reset.eq(1),
|
||||
If(crg.ready,
|
||||
NextState("COMINIT")
|
||||
),
|
||||
)
|
||||
fsm.act("COMINIT",
|
||||
trx.tx_idle.eq(1),
|
||||
trx.tx_cominit_stb.eq(1),
|
||||
If(trx.tx_cominit_ack & ~trx.rx_cominit_stb,
|
||||
NextState("AWAIT_COMINIT")
|
||||
),
|
||||
)
|
||||
fsm.act("AWAIT_COMINIT",
|
||||
trx.tx_idle.eq(1),
|
||||
retry_timeout.ce.eq(1),
|
||||
If(trx.rx_cominit_stb,
|
||||
NextState("AWAIT_NO_COMINIT")
|
||||
).Else(
|
||||
If(retry_timeout.reached,
|
||||
NextState("RESET")
|
||||
)
|
||||
),
|
||||
)
|
||||
fsm.act("AWAIT_NO_COMINIT",
|
||||
trx.tx_idle.eq(1),
|
||||
retry_timeout.reset.eq(1),
|
||||
If(~trx.rx_cominit_stb,
|
||||
NextState("CALIBRATE")
|
||||
),
|
||||
)
|
||||
fsm.act("CALIBRATE",
|
||||
trx.tx_idle.eq(1),
|
||||
NextState("COMWAKE"),
|
||||
)
|
||||
fsm.act("COMWAKE",
|
||||
trx.tx_idle.eq(1),
|
||||
trx.tx_comwake_stb.eq(1),
|
||||
If(trx.tx_comwake_ack,
|
||||
NextState("AWAIT_COMWAKE")
|
||||
),
|
||||
)
|
||||
fsm.act("AWAIT_COMWAKE",
|
||||
trx.tx_idle.eq(1),
|
||||
retry_timeout.ce.eq(1),
|
||||
If(trx.rx_comwake_stb,
|
||||
NextState("AWAIT_NO_COMWAKE")
|
||||
).Else(
|
||||
If(retry_timeout.reached,
|
||||
NextState("RESET")
|
||||
)
|
||||
),
|
||||
)
|
||||
fsm.act("AWAIT_NO_COMWAKE",
|
||||
trx.tx_idle.eq(1),
|
||||
If(~trx.rx_comwake_stb,
|
||||
NextState("AWAIT_NO_RX_IDLE")
|
||||
),
|
||||
)
|
||||
fsm.act("AWAIT_NO_RX_IDLE",
|
||||
trx.tx_idle.eq(0),
|
||||
source.data.eq(0x4A4A4A4A), #D10.2
|
||||
source.charisk.eq(0b0000),
|
||||
If(~trx.rx_idle,
|
||||
NextState("AWAIT_ALIGN"),
|
||||
crg.reset.eq(1),
|
||||
trx.pmarxreset.eq(1)
|
||||
),
|
||||
)
|
||||
fsm.act("AWAIT_ALIGN",
|
||||
trx.tx_idle.eq(0),
|
||||
source.data.eq(0x4A4A4A4A), #D10.2
|
||||
source.charisk.eq(0b0000),
|
||||
trx.rx_align.eq(1),
|
||||
align_timeout.ce.eq(1),
|
||||
If(align_detect & ~trx.rx_idle,
|
||||
NextState("SEND_ALIGN")
|
||||
).Elif(align_timeout.reached,
|
||||
NextState("RESET")
|
||||
),
|
||||
)
|
||||
fsm.act("SEND_ALIGN",
|
||||
trx.tx_idle.eq(0),
|
||||
trx.rx_align.eq(1),
|
||||
source.data.eq(primitives["ALIGN"]),
|
||||
source.charisk.eq(0b0001),
|
||||
If(non_align_cnt == 3,
|
||||
NextState("READY")
|
||||
),
|
||||
)
|
||||
fsm.act("READY",
|
||||
trx.tx_idle.eq(0),
|
||||
trx.rx_align.eq(1),
|
||||
source.data.eq(primitives["SYNC"]),
|
||||
source.charisk.eq(0b0001),
|
||||
If(trx.rx_idle,
|
||||
NextState("RESET")
|
||||
),
|
||||
self.ready.eq(1),
|
||||
)
|
||||
|
||||
reset_timeout = Timeout(clk_freq//16)
|
||||
self.submodules += reset_timeout
|
||||
self.comb += [
|
||||
reset_timeout.ce.eq(~self.ready),
|
||||
self.need_reset.eq(reset_timeout.reached)
|
||||
]
|
||||
|
||||
self.comb += \
|
||||
align_detect.eq(self.sink.stb & (self.sink.data == primitives["ALIGN"]))
|
||||
self.sync += \
|
||||
If(fsm.ongoing("SEND_ALIGN"),
|
||||
If(sink.stb,
|
||||
If(sink.data[0:8] == 0x7C,
|
||||
non_align_cnt.eq(non_align_cnt + 1)
|
||||
).Else(
|
||||
non_align_cnt.eq(0)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
from litesata.common import *
|
||||
|
||||
class LiteSATAPHYDatapathRX(Module):
|
||||
def __init__(self):
|
||||
self.sink = sink = Sink(phy_description(16))
|
||||
self.source = source = Source(phy_description(32))
|
||||
|
||||
###
|
||||
|
||||
# width convertion (16 to 32) and byte alignment
|
||||
byte_alignment = Signal()
|
||||
last_charisk = Signal(2)
|
||||
last_data = Signal(16)
|
||||
self.sync.sata_rx += \
|
||||
If(sink.stb & sink.ack,
|
||||
If(sink.charisk != 0,
|
||||
byte_alignment.eq(sink.charisk[1])
|
||||
),
|
||||
last_charisk.eq(sink.charisk),
|
||||
last_data.eq(sink.data)
|
||||
)
|
||||
converter = Converter(phy_description(16), phy_description(32), reverse=False)
|
||||
converter = InsertReset(RenameClockDomains(converter, "sata_rx"))
|
||||
self.submodules += converter
|
||||
self.comb += [
|
||||
converter.sink.stb.eq(sink.stb),
|
||||
If(byte_alignment,
|
||||
converter.sink.charisk.eq(Cat(last_charisk[1], sink.charisk[0])),
|
||||
converter.sink.data.eq(Cat(last_data[8:], sink.data[:8]))
|
||||
).Else(
|
||||
converter.sink.charisk.eq(sink.charisk),
|
||||
converter.sink.data.eq(sink.data)
|
||||
),
|
||||
sink.ack.eq(converter.sink.ack),
|
||||
converter.reset.eq(converter.source.charisk[2:] != 0)
|
||||
]
|
||||
|
||||
# clock domain crossing
|
||||
# (sata_gen3) 300MHz sata_rx clk to sys_clk
|
||||
# (sata_gen2) 150MHz sata_rx clk to sys_clk
|
||||
# (sata_gen1) 75MHz sata_rx clk to sys_clk
|
||||
# requirements:
|
||||
# due to the convertion ratio of 2, sys_clk need to be > sata_rx/2
|
||||
# source destination is always able to accept data (ack always 1)
|
||||
fifo = AsyncFIFO(phy_description(32), 4)
|
||||
fifo = RenameClockDomains(fifo, {"write": "sata_rx", "read": "sys"})
|
||||
self.submodules += fifo
|
||||
self.comb += [
|
||||
Record.connect(converter.source, fifo.sink),
|
||||
Record.connect(fifo.source, source)
|
||||
]
|
||||
|
||||
class LiteSATAPHYDatapathTX(Module):
|
||||
def __init__(self):
|
||||
self.sink = sink = Sink(phy_description(32))
|
||||
self.source = source = Source(phy_description(16))
|
||||
|
||||
###
|
||||
|
||||
# clock domain crossing
|
||||
# (sata_gen3) sys_clk to 300MHz sata_tx clk
|
||||
# (sata_gen2) sys_clk to 150MHz sata_tx clk
|
||||
# (sata_gen1) sys_clk to 75MHz sata_tx clk
|
||||
# requirements:
|
||||
# source destination is always able to accept data (ack always 1)
|
||||
fifo = AsyncFIFO(phy_description(32), 4)
|
||||
fifo = RenameClockDomains(fifo, {"write": "sys", "read": "sata_tx"})
|
||||
self.submodules += fifo
|
||||
self.comb += Record.connect(sink, fifo.sink)
|
||||
|
||||
# width convertion (32 to 16)
|
||||
converter = Converter(phy_description(32), phy_description(16), reverse=False)
|
||||
converter = RenameClockDomains(converter, "sata_tx")
|
||||
self.submodules += converter
|
||||
self.comb += [
|
||||
Record.connect(fifo.source, converter.sink),
|
||||
Record.connect(converter.source, source)
|
||||
]
|
||||
|
||||
class LiteSATAPHYAlignInserter(Module):
|
||||
def __init__(self, ctrl):
|
||||
self.sink = sink = Sink(phy_description(32))
|
||||
self.source = source = Source(phy_description(32))
|
||||
|
||||
###
|
||||
|
||||
# send 2 ALIGN every 256 DWORDs
|
||||
# used for clock compensation between
|
||||
# HOST and device
|
||||
cnt = Signal(8)
|
||||
send = Signal()
|
||||
self.sync += \
|
||||
If(~ctrl.ready,
|
||||
cnt.eq(0)
|
||||
).Elif(source.stb & source.ack,
|
||||
cnt.eq(cnt+1)
|
||||
)
|
||||
self.comb += [
|
||||
send.eq(cnt < 2),
|
||||
If(send,
|
||||
source.stb.eq(1),
|
||||
source.charisk.eq(0b0001),
|
||||
source.data.eq(primitives["ALIGN"]),
|
||||
sink.ack.eq(0)
|
||||
).Else(
|
||||
source.stb.eq(sink.stb),
|
||||
source.data.eq(sink.data),
|
||||
source.charisk.eq(sink.charisk),
|
||||
sink.ack.eq(source.ack)
|
||||
)
|
||||
]
|
||||
|
||||
class LiteSATAPHYAlignRemover(Module):
|
||||
def __init__(self):
|
||||
self.sink = sink = Sink(phy_description(32))
|
||||
self.source = source = Source(phy_description(32))
|
||||
|
||||
###
|
||||
|
||||
charisk_match = sink.charisk == 0b0001
|
||||
data_match = sink.data == primitives["ALIGN"]
|
||||
|
||||
self.comb += \
|
||||
If(sink.stb & charisk_match & data_match,
|
||||
sink.ack.eq(1),
|
||||
).Else(
|
||||
Record.connect(sink, source)
|
||||
)
|
||||
|
||||
class LiteSATAPHYDatapath(Module):
|
||||
def __init__(self, trx, ctrl):
|
||||
self.sink = sink = Sink(phy_description(32))
|
||||
self.source = source = Source(phy_description(32))
|
||||
|
||||
###
|
||||
|
||||
# TX path
|
||||
align_inserter = LiteSATAPHYAlignInserter(ctrl)
|
||||
mux = Multiplexer(phy_description(32), 2)
|
||||
tx = LiteSATAPHYDatapathTX()
|
||||
self.submodules += align_inserter, mux, tx
|
||||
self.comb += [
|
||||
mux.sel.eq(ctrl.ready),
|
||||
Record.connect(sink, align_inserter.sink),
|
||||
Record.connect(ctrl.source, mux.sink0),
|
||||
Record.connect(align_inserter.source, mux.sink1),
|
||||
Record.connect(mux.source, tx.sink),
|
||||
Record.connect(tx.source, trx.sink)
|
||||
]
|
||||
|
||||
# RX path
|
||||
rx = LiteSATAPHYDatapathRX()
|
||||
demux = Demultiplexer(phy_description(32), 2)
|
||||
align_remover = LiteSATAPHYAlignRemover()
|
||||
self.submodules += rx, demux, align_remover
|
||||
self.comb += [
|
||||
demux.sel.eq(ctrl.ready),
|
||||
Record.connect(trx.source, rx.sink),
|
||||
Record.connect(rx.source, demux.sink),
|
||||
Record.connect(demux.source0, ctrl.sink),
|
||||
Record.connect(demux.source1, align_remover.sink),
|
||||
Record.connect(align_remover.source, source)
|
||||
]
|
||||
|
|
@ -0,0 +1,155 @@
|
|||
from litesata.common import *
|
||||
|
||||
class K7LiteSATAPHYCRG(Module):
|
||||
def __init__(self, pads, gtx, revision, clk_freq):
|
||||
self.reset = Signal()
|
||||
self.ready = Signal()
|
||||
|
||||
self.clock_domains.cd_sata_tx = ClockDomain()
|
||||
self.clock_domains.cd_sata_rx = ClockDomain()
|
||||
|
||||
# CPLL
|
||||
# (sata_gen3) 150MHz / VCO @ 3GHz / Line rate @ 6Gbps
|
||||
# (sata_gen2 & sata_gen1) VCO still @ 3 GHz, Line rate is decreased with output dividers.
|
||||
refclk = Signal()
|
||||
self.specials += Instance("IBUFDS_GTE2",
|
||||
i_CEB=0,
|
||||
i_I=pads.refclk_p,
|
||||
i_IB=pads.refclk_n,
|
||||
o_O=refclk
|
||||
)
|
||||
self.comb += gtx.gtrefclk0.eq(refclk)
|
||||
|
||||
# TX clocking
|
||||
# (sata_gen3) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 300MHz (16-bits)
|
||||
# (sata_gen2) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 150MHz (16-bits)
|
||||
# (sata_gen1) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 75MHz (16-bits)
|
||||
mmcm_reset = Signal()
|
||||
mmcm_locked = Signal()
|
||||
mmcm_fb = Signal()
|
||||
mmcm_clk_i = Signal()
|
||||
mmcm_clk0_o = Signal()
|
||||
mmcm_div_config = {
|
||||
"sata_gen1" : 16.0,
|
||||
"sata_gen2" : 8.0,
|
||||
"sata_gen3" : 4.0
|
||||
}
|
||||
mmcm_div = mmcm_div_config[revision]
|
||||
self.specials += [
|
||||
Instance("BUFG", i_I=gtx.txoutclk, o_O=mmcm_clk_i),
|
||||
Instance("MMCME2_ADV",
|
||||
p_BANDWIDTH="HIGH", p_COMPENSATION="ZHOLD", i_RST=mmcm_reset, o_LOCKED=mmcm_locked,
|
||||
|
||||
# DRP
|
||||
i_DCLK=0, i_DEN=0, i_DWE=0, #o_DRDY=,
|
||||
i_DADDR=0, i_DI=0, #o_DO=,
|
||||
|
||||
# VCO
|
||||
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=6.666,
|
||||
p_CLKFBOUT_MULT_F=8.000, p_CLKFBOUT_PHASE=0.000, p_DIVCLK_DIVIDE=1,
|
||||
i_CLKIN1=mmcm_clk_i, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
|
||||
|
||||
# CLK0
|
||||
p_CLKOUT0_DIVIDE_F=mmcm_div, p_CLKOUT0_PHASE=0.000, o_CLKOUT0=mmcm_clk0_o,
|
||||
),
|
||||
Instance("BUFG", i_I=mmcm_clk0_o, o_O=self.cd_sata_tx.clk),
|
||||
]
|
||||
self.comb += [
|
||||
gtx.txusrclk.eq(self.cd_sata_tx.clk),
|
||||
gtx.txusrclk2.eq(self.cd_sata_tx.clk)
|
||||
]
|
||||
|
||||
# RX clocking
|
||||
# (sata_gen3) sata_rx recovered clk @ 300MHz from GTX RXOUTCLK
|
||||
# (sata_gen2) sata_rx recovered clk @ 150MHz from GTX RXOUTCLK
|
||||
# (sata_gen1) sata_rx recovered clk @ 150MHz from GTX RXOUTCLK
|
||||
self.specials += [
|
||||
Instance("BUFG", i_I=gtx.rxoutclk, o_O=self.cd_sata_rx.clk),
|
||||
]
|
||||
self.comb += [
|
||||
gtx.rxusrclk.eq(self.cd_sata_rx.clk),
|
||||
gtx.rxusrclk2.eq(self.cd_sata_rx.clk)
|
||||
]
|
||||
|
||||
# Configuration Reset
|
||||
# After configuration, GTX's resets have to stay low for at least 500ns
|
||||
# See AR43482
|
||||
reset_en = Signal()
|
||||
clk_period_ns = 1000000000/clk_freq
|
||||
reset_en_cnt_max = math.ceil(500/clk_period_ns)
|
||||
reset_en_cnt = Signal(max=reset_en_cnt_max, reset=reset_en_cnt_max-1)
|
||||
self.sync += \
|
||||
If(self.reset,
|
||||
reset_en_cnt.eq(reset_en_cnt.reset)
|
||||
).Elif(~reset_en,
|
||||
reset_en_cnt.eq(reset_en_cnt-1)
|
||||
)
|
||||
self.comb += reset_en.eq(reset_en_cnt == 0)
|
||||
|
||||
# TX Reset FSM
|
||||
tx_reset_fsm = InsertReset(FSM(reset_state="IDLE"))
|
||||
self.submodules += tx_reset_fsm
|
||||
self.comb += tx_reset_fsm.reset.eq(self.reset)
|
||||
tx_reset_fsm.act("IDLE",
|
||||
If(reset_en,
|
||||
NextState("RESET_GTX"),
|
||||
)
|
||||
)
|
||||
tx_reset_fsm.act("RESET_GTX",
|
||||
gtx.gttxreset.eq(1),
|
||||
If(gtx.cplllock & mmcm_locked,
|
||||
NextState("RELEASE_GTX")
|
||||
)
|
||||
)
|
||||
tx_reset_fsm.act("RELEASE_GTX",
|
||||
gtx.txuserrdy.eq(1),
|
||||
If(gtx.txresetdone,
|
||||
NextState("READY")
|
||||
)
|
||||
)
|
||||
tx_reset_fsm.act("READY",
|
||||
gtx.txuserrdy.eq(1)
|
||||
)
|
||||
|
||||
# RX Reset FSM
|
||||
rx_reset_fsm = InsertReset(FSM(reset_state="IDLE"))
|
||||
self.submodules += rx_reset_fsm
|
||||
self.comb += rx_reset_fsm.reset.eq(self.reset)
|
||||
|
||||
rx_reset_fsm.act("IDLE",
|
||||
If(reset_en,
|
||||
NextState("RESET_GTX"),
|
||||
)
|
||||
)
|
||||
rx_reset_fsm.act("RESET_GTX",
|
||||
gtx.gtrxreset.eq(1),
|
||||
If(gtx.cplllock & mmcm_locked,
|
||||
NextState("RELEASE_GTX")
|
||||
)
|
||||
)
|
||||
rx_reset_fsm.act("RELEASE_GTX",
|
||||
gtx.rxuserrdy.eq(1),
|
||||
If(gtx.rxresetdone,
|
||||
NextState("READY")
|
||||
)
|
||||
)
|
||||
rx_reset_fsm.act("READY",
|
||||
gtx.rxuserrdy.eq(1)
|
||||
)
|
||||
|
||||
# Ready
|
||||
self.tx_ready = tx_reset_fsm.ongoing("READY")
|
||||
self.rx_ready = rx_reset_fsm.ongoing("READY")
|
||||
self.comb += self.ready.eq(self.tx_ready & self.rx_ready)
|
||||
|
||||
# Reset PLL
|
||||
self.comb += gtx.cpllreset.eq(ResetSignal() | self.reset | ~reset_en)
|
||||
|
||||
# Reset MMCM
|
||||
self.comb += mmcm_reset.eq(ResetSignal() | self.reset | ~gtx.cplllock)
|
||||
|
||||
# Reset for SATA TX/RX clock domains
|
||||
self.specials += [
|
||||
AsyncResetSynchronizer(self.cd_sata_tx, ~self.tx_ready),
|
||||
AsyncResetSynchronizer(self.cd_sata_rx, ~self.rx_ready),
|
||||
]
|
||||
|
|
@ -0,0 +1,852 @@
|
|||
from litesata.common import *
|
||||
|
||||
def ones(width):
|
||||
return 2**width-1
|
||||
|
||||
class _PulseSynchronizer(PulseSynchronizer):
|
||||
def __init__(self, i, idomain, o, odomain):
|
||||
PulseSynchronizer.__init__(self, idomain, odomain)
|
||||
self.comb += [
|
||||
self.i.eq(i),
|
||||
o.eq(self.o)
|
||||
]
|
||||
|
||||
class _RisingEdge(Module):
|
||||
def __init__(self, i, o):
|
||||
i_d = Signal()
|
||||
self.sync += i_d.eq(i)
|
||||
self.comb += o.eq(i & ~i_d)
|
||||
|
||||
class K7LiteSATAPHYTRX(Module):
|
||||
def __init__(self, pads, revision):
|
||||
# Common signals
|
||||
|
||||
# control
|
||||
self.tx_idle = Signal() #i
|
||||
|
||||
self.tx_cominit_stb = Signal() #i
|
||||
self.tx_cominit_ack = Signal() #o
|
||||
self.tx_comwake_stb = Signal() #i
|
||||
self.tx_comwake_ack = Signal() #o
|
||||
|
||||
self.rx_idle = Signal() #o
|
||||
self.rx_align = Signal() #i
|
||||
|
||||
self.rx_cominit_stb = Signal() #o
|
||||
self.rx_comwake_stb = Signal() #o
|
||||
|
||||
# datapath
|
||||
self.sink = Sink(phy_description(16))
|
||||
self.source = Source(phy_description(16))
|
||||
|
||||
# K7 specific signals
|
||||
# Channel - Ref Clock Ports
|
||||
self.gtrefclk0 = Signal()
|
||||
|
||||
# Channel PLL
|
||||
self.cplllock = Signal()
|
||||
self.cpllreset = Signal()
|
||||
|
||||
# Receive Ports
|
||||
self.rxuserrdy = Signal()
|
||||
self.rxalign = Signal()
|
||||
|
||||
# Receive Ports - 8b10b Decoder
|
||||
self.rxcharisk = Signal(2)
|
||||
self.rxdisperr = Signal(2)
|
||||
|
||||
# Receive Ports - RX Data Path interface
|
||||
self.gtrxreset = Signal()
|
||||
self.pmarxreset = Signal()
|
||||
self.rxdata = Signal(16)
|
||||
self.rxoutclk = Signal()
|
||||
self.rxusrclk = Signal()
|
||||
self.rxusrclk2 = Signal()
|
||||
|
||||
# Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR
|
||||
self.rxelecidle = Signal()
|
||||
|
||||
# Receive Ports - RX PLL Ports
|
||||
self.rxresetdone = Signal()
|
||||
|
||||
# Receive Ports - RX Ports for SATA
|
||||
self.rxcominitdet = Signal()
|
||||
self.rxcomwakedet = Signal()
|
||||
|
||||
# Transmit Ports
|
||||
self.txuserrdy = Signal()
|
||||
|
||||
# Transmit Ports - 8b10b Encoder Control Ports
|
||||
self.txcharisk = Signal(2)
|
||||
|
||||
# Transmit Ports - TX Data Path interface
|
||||
self.gttxreset = Signal()
|
||||
self.txdata = Signal(16)
|
||||
self.txoutclk = Signal()
|
||||
self.txusrclk = Signal()
|
||||
self.txusrclk2 = Signal()
|
||||
|
||||
# Transmit Ports - TX PLL Ports
|
||||
self.txresetdone = Signal()
|
||||
|
||||
# Transmit Ports - TX Ports for PCI Express
|
||||
self.txelecidle = Signal(reset=1)
|
||||
|
||||
# Transmit Ports - TX Ports for SATA
|
||||
self.txcomfinish = Signal()
|
||||
self.txcominit = Signal()
|
||||
self.txcomwake = Signal()
|
||||
self.txrate = Signal(3)
|
||||
self.rxcdrlock = Signal()
|
||||
|
||||
# Config at startup
|
||||
div_config = {
|
||||
"sata_gen1" : 4,
|
||||
"sata_gen2" : 2,
|
||||
"sata_gen3" : 1
|
||||
}
|
||||
rxout_div = div_config[revision]
|
||||
txout_div = div_config[revision]
|
||||
|
||||
cdr_config = {
|
||||
"sata_gen1" : 0x0380008BFF40100008,
|
||||
"sata_gen2" : 0x0388008BFF40200008,
|
||||
"sata_gen3" : 0X0380008BFF10200010
|
||||
}
|
||||
rxcdr_cfg = cdr_config[revision]
|
||||
|
||||
# Specific / Generic signals encoding/decoding
|
||||
self.comb += [
|
||||
self.txelecidle.eq(self.tx_idle),
|
||||
self.tx_cominit_ack.eq(self.tx_cominit_stb & self.txcomfinish),
|
||||
self.tx_comwake_ack.eq(self.tx_comwake_stb & self.txcomfinish),
|
||||
self.rx_idle.eq(self.rxelecidle),
|
||||
self.rxalign.eq(self.rx_align),
|
||||
self.rx_cominit_stb.eq(self.rxcominitdet),
|
||||
self.rx_comwake_stb.eq(self.rxcomwakedet),
|
||||
]
|
||||
self.submodules += [
|
||||
_RisingEdge(self.tx_cominit_stb, self.txcominit),
|
||||
_RisingEdge(self.tx_comwake_stb, self.txcomwake),
|
||||
]
|
||||
|
||||
self.comb += [
|
||||
self.txcharisk.eq(self.sink.charisk),
|
||||
self.txdata.eq(self.sink.data),
|
||||
self.sink.ack.eq(1),
|
||||
|
||||
self.source.stb.eq(1),
|
||||
self.source.charisk.eq(self.rxcharisk),
|
||||
self.source.data.eq(self.rxdata)
|
||||
]
|
||||
|
||||
# Internals and clock domain crossing
|
||||
# sys_clk --> sata_tx clk
|
||||
txuserrdy = Signal()
|
||||
txelecidle = Signal(reset=1)
|
||||
txcominit = Signal()
|
||||
txcomwake = Signal()
|
||||
txrate = Signal(3)
|
||||
|
||||
self.specials += [
|
||||
MultiReg(self.txuserrdy, txuserrdy, "sata_tx"),
|
||||
MultiReg(self.txelecidle, txelecidle, "sata_tx"),
|
||||
MultiReg(self.txrate, txrate, "sata_tx")
|
||||
]
|
||||
self.submodules += [
|
||||
_PulseSynchronizer(self.txcominit, "sys", txcominit, "sata_tx"),
|
||||
_PulseSynchronizer(self.txcomwake, "sys", txcomwake, "sata_tx"),
|
||||
]
|
||||
|
||||
# sata_tx clk --> sys clk
|
||||
txresetdone = Signal()
|
||||
txcomfinish = Signal()
|
||||
|
||||
self.specials += [
|
||||
MultiReg(txresetdone, self.txresetdone, "sys"),
|
||||
]
|
||||
|
||||
self.submodules += [
|
||||
_PulseSynchronizer(txcomfinish, "sata_tx", self.txcomfinish, "sys"),
|
||||
]
|
||||
|
||||
# sys clk --> sata_rx clk
|
||||
rxuserrdy = Signal()
|
||||
|
||||
self.specials += [
|
||||
MultiReg(self.rxuserrdy, rxuserrdy, "sata_rx"),
|
||||
]
|
||||
|
||||
# sata_rx clk --> sys clk
|
||||
rxelecidle = Signal()
|
||||
rxelecidle_i = Signal()
|
||||
rxelecidle_cnt_i = Signal(9)
|
||||
rxresetdone = Signal()
|
||||
rxcominitdet = Signal()
|
||||
rxcomwakedet = Signal()
|
||||
rxratedone = Signal()
|
||||
rxcdrlock = Signal()
|
||||
|
||||
self.specials += [
|
||||
MultiReg(rxelecidle, rxelecidle_i, "sys"),
|
||||
MultiReg(rxresetdone, self.rxresetdone, "sys"),
|
||||
MultiReg(rxcominitdet, self.rxcominitdet, "sys"),
|
||||
MultiReg(rxcomwakedet, self.rxcomwakedet, "sys"),
|
||||
MultiReg(rxcdrlock, self.rxcdrlock, "sys"),
|
||||
]
|
||||
|
||||
self.sync += [
|
||||
If(rxelecidle_i != self.rxelecidle,
|
||||
If(rxelecidle_cnt_i == 0,
|
||||
self.rxelecidle.eq(rxelecidle_i),
|
||||
rxelecidle_cnt_i.eq(255)
|
||||
).Else(
|
||||
rxelecidle_cnt_i.eq(rxelecidle_cnt_i-1)
|
||||
)
|
||||
).Else(
|
||||
rxelecidle_cnt_i.eq(255)
|
||||
)
|
||||
]
|
||||
|
||||
self.rxbyteisaligned = Signal()
|
||||
|
||||
# QPLL input clock
|
||||
self.qpllclk = Signal()
|
||||
self.qpllrefclk = Signal()
|
||||
|
||||
# Instance
|
||||
gtxe2_channel_parameters = {
|
||||
# Simulation-Only Attributes
|
||||
"p_SIM_RECEIVER_DETECT_PASS":"TRUE",
|
||||
"p_SIM_TX_EIDLE_DRIVE_LEVEL":"X",
|
||||
"p_SIM_RESET_SPEEDUP":"TRUE",
|
||||
"p_SIM_CPLLREFCLK_SEL":0b001,
|
||||
"p_SIM_VERSION":"4.0",
|
||||
|
||||
# RX Byte and Word Alignment Attributes
|
||||
"p_ALIGN_COMMA_DOUBLE":"FALSE",
|
||||
"p_ALIGN_COMMA_ENABLE":ones(10),
|
||||
"p_ALIGN_COMMA_WORD":2,
|
||||
"p_ALIGN_MCOMMA_DET":"TRUE",
|
||||
"p_ALIGN_MCOMMA_VALUE":0b1010000011,
|
||||
"p_ALIGN_PCOMMA_DET":"TRUE",
|
||||
"p_ALIGN_PCOMMA_VALUE":0b0101111100,
|
||||
"p_SHOW_REALIGN_COMMA":"FALSE",
|
||||
"p_RXSLIDE_AUTO_WAIT":7,
|
||||
"p_RXSLIDE_MODE":"PCS",
|
||||
"p_RX_SIG_VALID_DLY":10,
|
||||
|
||||
# RX 8B/10B Decoder Attributes
|
||||
"p_RX_DISPERR_SEQ_MATCH":"TRUE",
|
||||
"p_DEC_MCOMMA_DETECT":"TRUE",
|
||||
"p_DEC_PCOMMA_DETECT":"TRUE",
|
||||
"p_DEC_VALID_COMMA_ONLY":"FALSE",
|
||||
|
||||
# RX Clock Correction Attributes
|
||||
"p_CBCC_DATA_SOURCE_SEL":"DECODED",
|
||||
"p_CLK_COR_SEQ_2_USE":"FALSE",
|
||||
"p_CLK_COR_KEEP_IDLE":"FALSE",
|
||||
"p_CLK_COR_MAX_LAT":9,
|
||||
"p_CLK_COR_MIN_LAT":7,
|
||||
"p_CLK_COR_PRECEDENCE":"TRUE",
|
||||
"p_CLK_COR_REPEAT_WAIT":0,
|
||||
"p_CLK_COR_SEQ_LEN":1,
|
||||
"p_CLK_COR_SEQ_1_ENABLE":ones(4),
|
||||
"p_CLK_COR_SEQ_1_1":0b0100000000,
|
||||
"p_CLK_COR_SEQ_1_2":0b0000000000,
|
||||
"p_CLK_COR_SEQ_1_3":0b0000000000,
|
||||
"p_CLK_COR_SEQ_1_4":0b0000000000,
|
||||
"p_CLK_CORRECT_USE":"FALSE",
|
||||
"p_CLK_COR_SEQ_2_ENABLE":ones(4),
|
||||
"p_CLK_COR_SEQ_2_1":0b0100000000,
|
||||
"p_CLK_COR_SEQ_2_2":0,
|
||||
"p_CLK_COR_SEQ_2_3":0,
|
||||
"p_CLK_COR_SEQ_2_4":0,
|
||||
|
||||
# RX Channel Bonding Attributes
|
||||
"p_CHAN_BOND_KEEP_ALIGN":"FALSE",
|
||||
"p_CHAN_BOND_MAX_SKEW":1,
|
||||
"p_CHAN_BOND_SEQ_LEN":1,
|
||||
"p_CHAN_BOND_SEQ_1_1":0,
|
||||
"p_CHAN_BOND_SEQ_1_1":0,
|
||||
"p_CHAN_BOND_SEQ_1_2":0,
|
||||
"p_CHAN_BOND_SEQ_1_3":0,
|
||||
"p_CHAN_BOND_SEQ_1_4":0,
|
||||
"p_CHAN_BOND_SEQ_1_ENABLE":ones(4),
|
||||
"p_CHAN_BOND_SEQ_2_1":0,
|
||||
"p_CHAN_BOND_SEQ_2_2":0,
|
||||
"p_CHAN_BOND_SEQ_2_3":0,
|
||||
"p_CHAN_BOND_SEQ_2_4":0,
|
||||
"p_CHAN_BOND_SEQ_2_ENABLE":ones(4),
|
||||
"p_CHAN_BOND_SEQ_2_USE":"FALSE",
|
||||
"p_FTS_DESKEW_SEQ_ENABLE":ones(4),
|
||||
"p_FTS_LANE_DESKEW_CFG":ones(4),
|
||||
"p_FTS_LANE_DESKEW_EN":"FALSE",
|
||||
|
||||
# RX Margin Analysis Attributes
|
||||
"p_ES_CONTROL":0,
|
||||
"p_ES_ERRDET_EN":"FALSE",
|
||||
"p_ES_EYE_SCAN_EN":"TRUE",
|
||||
"p_ES_HORZ_OFFSET":0,
|
||||
"p_ES_PMA_CFG":0,
|
||||
"p_ES_PRESCALE":0,
|
||||
"p_ES_QUALIFIER":0,
|
||||
"p_ES_QUAL_MASK":0,
|
||||
"p_ES_SDATA_MASK":0,
|
||||
"p_ES_VERT_OFFSET":0,
|
||||
|
||||
# FPGA RX Interface Attributes
|
||||
"p_RX_DATA_WIDTH":20,
|
||||
|
||||
# PMA Attributes
|
||||
"p_OUTREFCLK_SEL_INV":0b11,
|
||||
"p_PMA_RSV":0x00018480,
|
||||
"p_PMA_RSV2":0x2050,
|
||||
"p_PMA_RSV3":0,
|
||||
"p_PMA_RSV4":0,
|
||||
"p_RX_BIAS_CFG":0b100,
|
||||
"p_DMONITOR_CFG":0xA00,
|
||||
"p_RX_CM_SEL":0b11,
|
||||
"p_RX_CM_TRIM":0b010,
|
||||
"p_RX_DEBUG_CFG":0,
|
||||
"p_RX_OS_CFG":0b10000000,
|
||||
"p_TERM_RCAL_CFG":0,
|
||||
"p_TERM_RCAL_OVRD":0,
|
||||
"p_TST_RSV":0,
|
||||
"p_RX_CLK25_DIV":6,
|
||||
"p_TX_CLK25_DIV":6,
|
||||
"p_UCODEER_CLR":0,
|
||||
|
||||
# PCI Express Attributes
|
||||
"p_PCS_PCIE_EN":"FALSE",
|
||||
|
||||
# PCS Attributes
|
||||
"p_PCS_RSVD_ATTR":0x100,
|
||||
|
||||
# RX Buffer Attributes
|
||||
"p_RXBUF_ADDR_MODE":"FAST",
|
||||
"p_RXBUF_EIDLE_HI_CNT":0b1000,
|
||||
"p_RXBUF_EIDLE_LO_CNT":0,
|
||||
"p_RXBUF_EN":"TRUE",
|
||||
"p_RX_BUFFER_CFG":0,
|
||||
"p_RXBUF_RESET_ON_CB_CHANGE":"TRUE",
|
||||
"p_RXBUF_RESET_ON_COMMAALIGN":"FALSE",
|
||||
"p_RXBUF_RESET_ON_EIDLE":"FALSE",
|
||||
"p_RXBUF_RESET_ON_RATE_CHANGE":"TRUE",
|
||||
"p_RXBUFRESET_TIME":1,
|
||||
"p_RXBUF_THRESH_OVFLW":61,
|
||||
"p_RXBUF_THRESH_OVRD":"FALSE",
|
||||
"p_RXBUF_THRESH_UNDFLW":4,
|
||||
"p_RXDLY_CFG":0x1f,
|
||||
"p_RXDLY_LCFG":0x30,
|
||||
"p_RXDLY_TAP_CFG":0,
|
||||
"p_RXPH_CFG":0,
|
||||
"p_RXPHDLY_CFG":0x084820,
|
||||
"p_RXPH_MONITOR_SEL":0,
|
||||
"p_RX_XCLK_SEL":"RXUSR",
|
||||
"p_RX_DDI_SEL":0,
|
||||
"p_RX_DEFER_RESET_BUF_EN":"TRUE",
|
||||
|
||||
#CDR Attributes
|
||||
"p_RXCDR_CFG":rxcdr_cfg,
|
||||
"p_RXCDR_FR_RESET_ON_EIDLE":0,
|
||||
"p_RXCDR_HOLD_DURING_EIDLE":0,
|
||||
"p_RXCDR_PH_RESET_ON_EIDLE":0,
|
||||
"p_RXCDR_LOCK_CFG":0b010101,
|
||||
|
||||
# RX Initialization and Reset Attributes
|
||||
"p_RXCDRFREQRESET_TIME":1,
|
||||
"p_RXCDRPHRESET_TIME":1,
|
||||
"p_RXISCANRESET_TIME":1,
|
||||
"p_RXPCSRESET_TIME":1,
|
||||
"p_RXPMARESET_TIME":3,
|
||||
|
||||
# RX OOB Signaling Attributes
|
||||
"p_RXOOB_CFG":0b0000110,
|
||||
|
||||
# RX Gearbox Attributes
|
||||
"p_RXGEARBOX_EN":"FALSE",
|
||||
"p_GEARBOX_MODE":0,
|
||||
|
||||
# PRBS Detection Attribute
|
||||
"p_RXPRBS_ERR_LOOPBACK":0,
|
||||
|
||||
# Power-Down Attributes
|
||||
"p_PD_TRANS_TIME_FROM_P2":0x03c,
|
||||
"p_PD_TRANS_TIME_NONE_P2":0x3c,
|
||||
"p_PD_TRANS_TIME_TO_P2":0x64,
|
||||
|
||||
# RX OOB Signaling Attributes
|
||||
"p_SAS_MAX_COM":64,
|
||||
"p_SAS_MIN_COM":36,
|
||||
"p_SATA_BURST_SEQ_LEN":0b0101,
|
||||
"p_SATA_BURST_VAL":0b100,
|
||||
"p_SATA_EIDLE_VAL":0b100,
|
||||
"p_SATA_MAX_BURST":8,
|
||||
"p_SATA_MAX_INIT":21,
|
||||
"p_SATA_MAX_WAKE":7,
|
||||
"p_SATA_MIN_BURST":4,
|
||||
"p_SATA_MIN_INIT":12,
|
||||
"p_SATA_MIN_WAKE":4,
|
||||
|
||||
# RX Fabric Clock Output Control Attributes
|
||||
"p_TRANS_TIME_RATE":0x0e,
|
||||
|
||||
# TX Buffer Attributes
|
||||
"p_TXBUF_EN":"TRUE",
|
||||
"p_TXBUF_RESET_ON_RATE_CHANGE":"TRUE",
|
||||
"p_TXDLY_CFG":0x1f,
|
||||
"p_TXDLY_LCFG":0x030,
|
||||
"p_TXDLY_TAP_CFG":0,
|
||||
"p_TXPH_CFG":0x0780,
|
||||
"p_TXPHDLY_CFG":0x084020,
|
||||
"p_TXPH_MONITOR_SEL":0,
|
||||
"p_TX_XCLK_SEL":"TXOUT",
|
||||
|
||||
# FPGA TX Interface Attributes
|
||||
"p_TX_DATA_WIDTH":20,
|
||||
|
||||
# TX Configurable Driver Attributes
|
||||
"p_TX_DEEMPH0":0,
|
||||
"p_TX_DEEMPH1":0,
|
||||
"p_TX_EIDLE_ASSERT_DELAY":0b110,
|
||||
"p_TX_EIDLE_DEASSERT_DELAY":0b100,
|
||||
"p_TX_LOOPBACK_DRIVE_HIZ":"FALSE",
|
||||
"p_TX_MAINCURSOR_SEL":0,
|
||||
"p_TX_DRIVE_MODE":"DIRECT",
|
||||
"p_TX_MARGIN_FULL_0":0b1001110,
|
||||
"p_TX_MARGIN_FULL_1":0b1001001,
|
||||
"p_TX_MARGIN_FULL_2":0b1000101,
|
||||
"p_TX_MARGIN_FULL_3":0b1000010,
|
||||
"p_TX_MARGIN_FULL_4":0b1000000,
|
||||
"p_TX_MARGIN_LOW_0":0b1000110,
|
||||
"p_TX_MARGIN_LOW_1":0b1000100,
|
||||
"p_TX_MARGIN_LOW_2":0b1000010,
|
||||
"p_TX_MARGIN_LOW_3":0b1000000,
|
||||
"p_TX_MARGIN_LOW_4":0b1000000,
|
||||
|
||||
# TX Gearbox Attributes
|
||||
"p_TXGEARBOX_EN":"FALSE",
|
||||
|
||||
# TX Initialization and Reset Attributes
|
||||
"p_TXPCSRESET_TIME":1,
|
||||
"p_TXPMARESET_TIME":1,
|
||||
|
||||
# TX Receiver Detection Attributes
|
||||
"p_TX_RXDETECT_CFG":0x1832,
|
||||
"p_TX_RXDETECT_REF":0b100,
|
||||
|
||||
# CPLL Attributes
|
||||
"p_CPLL_CFG":0xBC07DC,
|
||||
"p_CPLL_FBDIV":4,
|
||||
"p_CPLL_FBDIV_45":5,
|
||||
"p_CPLL_INIT_CFG":0x00001e,
|
||||
"p_CPLL_LOCK_CFG":0x01e8,
|
||||
"p_CPLL_REFCLK_DIV":1,
|
||||
"p_RXOUT_DIV":rxout_div,
|
||||
"p_TXOUT_DIV":txout_div,
|
||||
"p_SATA_CPLL_CFG":"VCO_3000MHZ",
|
||||
|
||||
# RX Initialization and Reset Attributes
|
||||
"p_RXDFELPMRESET_TIME":0b0001111,
|
||||
|
||||
# RX Equalizer Attributes
|
||||
"p_RXLPM_HF_CFG":0b00000011110000,
|
||||
"p_RXLPM_LF_CFG":0b00000011110000,
|
||||
"p_RX_DFE_GAIN_CFG":0x020fea,
|
||||
"p_RX_DFE_H2_CFG":0b000000000000,
|
||||
"p_RX_DFE_H3_CFG":0b000001000000,
|
||||
"p_RX_DFE_H4_CFG":0b00011110000,
|
||||
"p_RX_DFE_H5_CFG":0b00011100000,
|
||||
"p_RX_DFE_KL_CFG":0b0000011111110,
|
||||
"p_RX_DFE_LPM_CFG":0x0954,
|
||||
"p_RX_DFE_LPM_HOLD_DURING_EIDLE":0,
|
||||
"p_RX_DFE_UT_CFG":0b10001111000000000,
|
||||
"p_RX_DFE_VP_CFG":0b00011111100000011,
|
||||
|
||||
# Power-Down Attributes
|
||||
"p_RX_CLKMUX_PD":1,
|
||||
"p_TX_CLKMUX_PD":1,
|
||||
|
||||
# FPGA RX Interface Attribute
|
||||
"p_RX_INT_DATAWIDTH":0,
|
||||
|
||||
# FPGA TX Interface Attribute
|
||||
"p_TX_INT_DATAWIDTH":0,
|
||||
|
||||
# TX Configurable Driver Attributes
|
||||
"p_TX_QPI_STATUS_EN":0,
|
||||
|
||||
# RX Equalizer Attributes
|
||||
"p_RX_DFE_KL_CFG2":0b00110011000100000001100000001100,
|
||||
"p_RX_DFE_XYD_CFG":0b0000000000000,
|
||||
|
||||
# TX Configurable Driver Attributes
|
||||
"p_TX_PREDRIVER_MODE":0,
|
||||
}
|
||||
|
||||
self.specials += \
|
||||
Instance("GTXE2_CHANNEL",
|
||||
# CPLL Ports
|
||||
#o_CPLLFBCLKLOST=,
|
||||
o_CPLLLOCK=self.cplllock,
|
||||
i_CPLLLOCKDETCLK=0,
|
||||
i_CPLLLOCKEN=1,
|
||||
i_CPLLPD=0,
|
||||
#o_CPLLREFCLKLOST=0,
|
||||
i_CPLLREFCLKSEL=0b001,
|
||||
i_CPLLRESET=self.cpllreset,
|
||||
i_GTRSVD=0,
|
||||
i_PCSRSVDIN=0,
|
||||
i_PCSRSVDIN2=0,
|
||||
i_PMARSVDIN=0,
|
||||
i_PMARSVDIN2=0,
|
||||
i_TSTIN=ones(20),
|
||||
#o_TSTOUT=,
|
||||
|
||||
# Channel
|
||||
i_CLKRSVD=0,
|
||||
|
||||
# Channel - Clocking Ports
|
||||
i_GTGREFCLK=0,
|
||||
i_GTNORTHREFCLK0=0,
|
||||
i_GTNORTHREFCLK1=0,
|
||||
i_GTREFCLK0=self.gtrefclk0,
|
||||
i_GTREFCLK1=0,
|
||||
i_GTSOUTHREFCLK0=0,
|
||||
i_GTSOUTHREFCLK1=0,
|
||||
|
||||
# Channel - DRP Ports
|
||||
i_DRPADDR=0,
|
||||
i_DRPCLK=0,
|
||||
i_DRPDI=0,
|
||||
#o_DRPDO=,
|
||||
i_DRPEN=0,
|
||||
#o_DRPRDY=,
|
||||
i_DRPWE=0,
|
||||
|
||||
# Clocking Ports
|
||||
#o_GTREFCLKMONITOR=,
|
||||
i_QPLLCLK=self.qpllclk,
|
||||
i_QPLLREFCLK=self.qpllrefclk,
|
||||
i_RXSYSCLKSEL=0b00,
|
||||
i_TXSYSCLKSEL=0b00,
|
||||
|
||||
# Digital Monitor Ports
|
||||
#o_DMONITOROUT=,
|
||||
|
||||
# FPGA TX Interface Datapath Configuration
|
||||
i_TX8B10BEN=1,
|
||||
|
||||
# Loopback Ports
|
||||
i_LOOPBACK=0,
|
||||
|
||||
# PCI Express Ports
|
||||
#o_PHYSTATUS=,
|
||||
i_RXRATE=0,
|
||||
#o_RXVALID=,
|
||||
|
||||
# Power-Down Ports
|
||||
i_RXPD=0b00,
|
||||
i_TXPD=0b00,
|
||||
|
||||
# RX 8B/10B Decoder Ports
|
||||
i_SETERRSTATUS=0,
|
||||
|
||||
# RX Initialization and Reset Ports
|
||||
i_EYESCANRESET=0,
|
||||
i_RXUSERRDY=rxuserrdy,
|
||||
|
||||
# RX Margin Analysis Ports
|
||||
#o_EYESCANDATAERROR=,
|
||||
i_EYESCANMODE=0,
|
||||
i_EYESCANTRIGGER=0,
|
||||
|
||||
# Receive Ports - CDR Ports
|
||||
i_RXCDRFREQRESET=0,
|
||||
i_RXCDRHOLD=0,
|
||||
o_RXCDRLOCK=rxcdrlock,
|
||||
i_RXCDROVRDEN=0,
|
||||
i_RXCDRRESET=0,
|
||||
i_RXCDRRESETRSV=0,
|
||||
|
||||
# Receive Ports - Clock Correction Ports
|
||||
#o_RXCLKCORCNT=,
|
||||
|
||||
# Receive Ports - FPGA RX Interface Datapath Configuration
|
||||
i_RX8B10BEN=1,
|
||||
|
||||
# Receive Ports - FPGA RX Interface Ports
|
||||
i_RXUSRCLK=self.rxusrclk,
|
||||
i_RXUSRCLK2=self.rxusrclk2,
|
||||
|
||||
# Receive Ports - FPGA RX interface Ports
|
||||
o_RXDATA=self.rxdata,
|
||||
|
||||
# Receive Ports - Pattern Checker Ports
|
||||
#o_RXPRBSERR=,
|
||||
i_RXPRBSSEL=0,
|
||||
|
||||
# Receive Ports - Pattern Checker ports
|
||||
i_RXPRBSCNTRESET=0,
|
||||
|
||||
# Receive Ports - RX Equalizer Ports
|
||||
i_RXDFEXYDEN=0,
|
||||
i_RXDFEXYDHOLD=0,
|
||||
i_RXDFEXYDOVRDEN=0,
|
||||
|
||||
# Receive Ports - RX 8B/10B Decoder Ports
|
||||
#o_RXDISPERR=,
|
||||
#o_RXNOTINTABLE=,
|
||||
|
||||
# Receive Ports - RX AFE
|
||||
i_GTXRXP=pads.rxp,
|
||||
i_GTXRXN=pads.rxn,
|
||||
|
||||
# Receive Ports - RX Buffer Bypass Ports
|
||||
i_RXBUFRESET=0,
|
||||
#o_RXBUFSTATUS=,
|
||||
i_RXDDIEN=0,
|
||||
i_RXDLYBYPASS=1,
|
||||
i_RXDLYEN=0,
|
||||
i_RXDLYOVRDEN=0,
|
||||
i_RXDLYSRESET=0,
|
||||
#o_RXDLYSRESETDONE=0,
|
||||
i_RXPHALIGN=0,
|
||||
#o_RXPHALIGNDONE=,
|
||||
i_RXPHALIGNEN=0,
|
||||
i_RXPHDLYPD=0,
|
||||
i_RXPHDLYRESET=0,
|
||||
#o_RXPHMONITOR=,
|
||||
i_RXPHOVRDEN=0,
|
||||
#o_RXPHSLIPMONITOR=,
|
||||
#o_RXSTATUS=,
|
||||
|
||||
# Receive Ports - RX Byte and Word Alignment Ports
|
||||
o_RXBYTEISALIGNED=self.rxbyteisaligned,
|
||||
#o_RXBYTEREALIGN=,
|
||||
#o_RXCOMMADET=,
|
||||
i_RXCOMMADETEN=1,
|
||||
i_RXMCOMMAALIGNEN=1,
|
||||
i_RXPCOMMAALIGNEN=1,
|
||||
|
||||
# Receive Ports - RX Channel Bonding Ports
|
||||
#o_RXCHANBONDSEQ=,
|
||||
i_RXCHBONDEN=0,
|
||||
i_RXCHBONDLEVEL=0,
|
||||
i_RXCHBONDMASTER=0,
|
||||
#o_RXCHBONDO=,
|
||||
i_RXCHBONDSLAVE=0,
|
||||
|
||||
# Receive Ports - RX Channel Bonding Ports
|
||||
#o_RXCHANISALIGNED=,
|
||||
#o_RXCHANREALIGN=,
|
||||
|
||||
# Receive Ports - RX Equalizer Ports
|
||||
i_RXDFEAGCHOLD=0,
|
||||
i_RXDFEAGCOVRDEN=0,
|
||||
i_RXDFECM1EN=0,
|
||||
i_RXDFELFHOLD=0,
|
||||
i_RXDFELFOVRDEN=1,
|
||||
i_RXDFELPMRESET=0,
|
||||
i_RXDFETAP2HOLD=0,
|
||||
i_RXDFETAP2OVRDEN=0,
|
||||
i_RXDFETAP3HOLD=0,
|
||||
i_RXDFETAP3OVRDEN=0,
|
||||
i_RXDFETAP4HOLD=0,
|
||||
i_RXDFETAP4OVRDEN=0,
|
||||
i_RXDFETAP5HOLD=0,
|
||||
i_RXDFETAP5OVRDEN=0,
|
||||
i_RXDFEUTHOLD=0,
|
||||
i_RXDFEUTOVRDEN=0,
|
||||
i_RXDFEVPHOLD=0,
|
||||
i_RXDFEVPOVRDEN=0,
|
||||
i_RXDFEVSEN=0,
|
||||
i_RXLPMLFKLOVRDEN=0,
|
||||
#o_RXMONITOROUT=,
|
||||
i_RXMONITORSEL=0b00,
|
||||
i_RXOSHOLD=0,
|
||||
i_RXOSOVRDEN=0,
|
||||
|
||||
# Receive Ports - RX Equilizer Ports
|
||||
i_RXLPMHFHOLD=0,
|
||||
i_RXLPMHFOVRDEN=0,
|
||||
i_RXLPMLFHOLD=0,
|
||||
|
||||
# Receive Ports - RX Fabric ClocK Output Control Ports
|
||||
#o_RXRATEDONE=,
|
||||
|
||||
# Receive Ports - RX Fabric Output Control Ports
|
||||
o_RXOUTCLK=self.rxoutclk,
|
||||
#o_RXOUTCLKFABRIC=,
|
||||
#o_RXOUTCLKPCS=,
|
||||
i_RXOUTCLKSEL=0b010,
|
||||
|
||||
# Receive Ports - RX Gearbox Ports
|
||||
#o_RXDATAVALID=,
|
||||
#o_RXHEADER=,
|
||||
#o_RXHEADERVALID=,
|
||||
#o_RXSTARTOFSEQ=,
|
||||
|
||||
# Receive Ports - RX Gearbox Ports
|
||||
i_RXGEARBOXSLIP=0,
|
||||
|
||||
# Receive Ports - RX Initialization and Reset Ports
|
||||
i_GTRXRESET=self.gtrxreset,
|
||||
i_RXOOBRESET=0,
|
||||
i_RXPCSRESET=0,
|
||||
i_RXPMARESET=self.pmarxreset,
|
||||
|
||||
# Receive Ports - RX Margin Analysis ports
|
||||
i_RXLPMEN=0,
|
||||
|
||||
# Receive Ports - RX OOB Signaling ports
|
||||
#o_RXCOMSASDET=,
|
||||
o_RXCOMWAKEDET=rxcomwakedet,
|
||||
|
||||
# Receive Ports - RX OOB Signaling ports
|
||||
o_RXCOMINITDET=rxcominitdet,
|
||||
|
||||
# Receive Ports - RX OOB signalling Ports
|
||||
o_RXELECIDLE=rxelecidle,
|
||||
i_RXELECIDLEMODE=0b00,
|
||||
|
||||
# Receive Ports - RX Polarity Control Ports
|
||||
i_RXPOLARITY=0,
|
||||
|
||||
# Receive Ports - RX gearbox ports
|
||||
i_RXSLIDE=0,
|
||||
|
||||
# Receive Ports - RX8B/10B Decoder Ports
|
||||
#o_RXCHARISCOMMA=,
|
||||
o_RXCHARISK=self.rxcharisk,
|
||||
|
||||
# Receive Ports - Rx Channel Bonding Ports
|
||||
i_RXCHBONDI=0,
|
||||
|
||||
# Receive Ports -RX Initialization and Reset Ports
|
||||
o_RXRESETDONE=rxresetdone,
|
||||
|
||||
# Rx AFE Ports
|
||||
i_RXQPIEN=0,
|
||||
#o_RXQPISENN=,
|
||||
#o_RXQPISENP=,
|
||||
|
||||
# TX Buffer Bypass Ports
|
||||
i_TXPHDLYTSTCLK=0,
|
||||
|
||||
# TX Configurable Driver Ports
|
||||
i_TXPOSTCURSOR=0,
|
||||
i_TXPOSTCURSORINV=0,
|
||||
i_TXPRECURSOR=0,
|
||||
i_TXPRECURSORINV=0,
|
||||
i_TXQPIBIASEN=0,
|
||||
i_TXQPISTRONGPDOWN=0,
|
||||
i_TXQPIWEAKPUP=0,
|
||||
|
||||
# TX Initialization and Reset Ports
|
||||
i_CFGRESET=0,
|
||||
i_GTTXRESET=self.gttxreset,
|
||||
#o_PCSRSVDOUT=,
|
||||
i_TXUSERRDY=txuserrdy,
|
||||
|
||||
# Transceiver Reset Mode Operation
|
||||
i_GTRESETSEL=0,
|
||||
i_RESETOVRD=0,
|
||||
|
||||
# Transmit Ports - 8b10b Encoder Control Ports
|
||||
i_TXCHARDISPMODE=0,
|
||||
i_TXCHARDISPVAL=0,
|
||||
|
||||
# Transmit Ports - FPGA TX Interface Ports
|
||||
i_TXUSRCLK=self.txusrclk,
|
||||
i_TXUSRCLK2=self.txusrclk2,
|
||||
|
||||
# Transmit Ports - PCI Express Ports
|
||||
i_TXELECIDLE=txelecidle,
|
||||
i_TXMARGIN=0,
|
||||
i_TXRATE=txrate,
|
||||
i_TXSWING=0,
|
||||
|
||||
# Transmit Ports - Pattern Generator Ports
|
||||
i_TXPRBSFORCEERR=0,
|
||||
|
||||
# Transmit Ports - TX Buffer Bypass Ports
|
||||
i_TXDLYBYPASS=1,
|
||||
i_TXDLYEN=0,
|
||||
i_TXDLYHOLD=0,
|
||||
i_TXDLYOVRDEN=0,
|
||||
i_TXDLYSRESET=0,
|
||||
#o_TXDLYSRESETDONE=,
|
||||
i_TXDLYUPDOWN=0,
|
||||
i_TXPHALIGN=0,
|
||||
#o_TXPHALIGNDONE=txphaligndone,
|
||||
i_TXPHALIGNEN=0,
|
||||
i_TXPHDLYPD=0,
|
||||
i_TXPHDLYRESET=0,
|
||||
i_TXPHINIT=0,
|
||||
#o_TXPHINITDONE=,
|
||||
i_TXPHOVRDEN=0,
|
||||
|
||||
# Transmit Ports - TX Buffer Ports
|
||||
#o_TXBUFSTATUS=,
|
||||
|
||||
# Transmit Ports - TX Configurable Driver Ports
|
||||
i_TXBUFDIFFCTRL=0b100,
|
||||
i_TXDEEMPH=0,
|
||||
i_TXDIFFCTRL=0b1000,
|
||||
i_TXDIFFPD=0,
|
||||
i_TXINHIBIT=0,
|
||||
i_TXMAINCURSOR=0,
|
||||
i_TXPISOPD=0,
|
||||
|
||||
# Transmit Ports - TX Data Path interface
|
||||
i_TXDATA=self.txdata,
|
||||
|
||||
# Transmit Ports - TX Driver and OOB signaling
|
||||
o_GTXTXP=pads.txp,
|
||||
o_GTXTXN=pads.txn,
|
||||
|
||||
# Transmit Ports - TX Fabric Clock Output Control Ports
|
||||
o_TXOUTCLK=self.txoutclk,
|
||||
#o_TXOUTCLKFABRIC=,
|
||||
#o_TXOUTCLKPCS=,
|
||||
i_TXOUTCLKSEL=0b11, #??
|
||||
#o_TXRATEDONE=,
|
||||
# Transmit Ports - TX Gearbox Ports
|
||||
i_TXCHARISK=self.txcharisk,
|
||||
#o_TXGEARBOXREADY=,
|
||||
i_TXHEADER=0,
|
||||
i_TXSEQUENCE=0,
|
||||
i_TXSTARTSEQ=0,
|
||||
|
||||
# Transmit Ports - TX Initialization and Reset Ports
|
||||
i_TXPCSRESET=0,
|
||||
i_TXPMARESET=0,
|
||||
o_TXRESETDONE=txresetdone,
|
||||
|
||||
# Transmit Ports - TX OOB signalling Ports
|
||||
o_TXCOMFINISH=txcomfinish,
|
||||
i_TXCOMINIT=txcominit,
|
||||
i_TXCOMSAS=0,
|
||||
i_TXCOMWAKE=txcomwake,
|
||||
i_TXPDELECIDLEMODE=0,
|
||||
|
||||
# Transmit Ports - TX Polarity Control Ports
|
||||
i_TXPOLARITY=0,
|
||||
|
||||
# Transmit Ports - TX Receiver Detection Ports
|
||||
i_TXDETECTRX=0,
|
||||
|
||||
# Transmit Ports - TX8b/10b Encoder Ports
|
||||
i_TX8B10BBYPASS=0,
|
||||
|
||||
# Transmit Ports - pattern Generator Ports
|
||||
i_TXPRBSSEL=0,
|
||||
|
||||
# Tx Configurable Driver Ports
|
||||
#o_TXQPISENN=,
|
||||
#o_TXQPISENP=,
|
||||
|
||||
**gtxe2_channel_parameters
|
||||
)
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
MSCDIR = ../../
|
||||
PYTHON = python3
|
||||
|
||||
CMD = PYTHONPATH=$(MSCDIR) $(PYTHON)
|
||||
|
||||
CC=gcc
|
||||
CFLAGS =-Wall -O0
|
||||
|
||||
phy_datapath_tb:
|
||||
$(CMD) phy_datapath_tb.py
|
||||
|
||||
crc_tb:
|
||||
$(CC) $(CFLAGS) $(INC) -o crc crc.c
|
||||
$(CMD) crc_tb.py
|
||||
|
||||
scrambler_tb:
|
||||
$(CC) $(CFLAGS) $(INC) -o scrambler scrambler.c
|
||||
$(CMD) scrambler_tb.py
|
||||
|
||||
cont_tb:
|
||||
$(CMD) cont_tb.py
|
||||
|
||||
link_tb:
|
||||
$(CMD) link_tb.py
|
||||
|
||||
command_tb:
|
||||
$(CMD) command_tb.py
|
||||
|
||||
bist_tb:
|
||||
$(CMD) bist_tb.py
|
||||
|
||||
clean:
|
||||
rm crc scrambler *.vcd
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
from litesata.common import *
|
||||
from litesata import LiteSATA
|
||||
from litesata.frontend.bist import LiteSATABISTGenerator, LiteSATABISTChecker
|
||||
|
||||
from litesata.test.hdd import *
|
||||
from litesata.test.common import *
|
||||
|
||||
class TB(Module):
|
||||
def __init__(self):
|
||||
self.submodules.hdd = HDD(
|
||||
link_debug=False, link_random_level=0,
|
||||
transport_debug=False, transport_loopback=False,
|
||||
hdd_debug=True)
|
||||
self.submodules.controller = LiteSATA(self.hdd.phy)
|
||||
self.submodules.generator = LiteSATABISTGenerator(self.controller.crossbar.get_port())
|
||||
self.submodules.checker = LiteSATABISTChecker(self.controller.crossbar.get_port())
|
||||
|
||||
def gen_simulation(self, selfp):
|
||||
hdd = self.hdd
|
||||
hdd.malloc(0, 64)
|
||||
selfp.generator.sector = 0
|
||||
selfp.generator.count = 17
|
||||
selfp.checker.sector = 0
|
||||
selfp.checker.count = 17
|
||||
while True:
|
||||
selfp.generator.start = 1
|
||||
yield
|
||||
selfp.generator.start = 0
|
||||
yield
|
||||
while selfp.generator.done == 0:
|
||||
yield
|
||||
selfp.checker.start = 1
|
||||
yield
|
||||
selfp.checker.start = 0
|
||||
yield
|
||||
while selfp.checker.done == 0:
|
||||
yield
|
||||
print("errors {}".format(selfp.checker.errors))
|
||||
selfp.generator.sector += 1
|
||||
selfp.generator.count = max((selfp.generator.count + 1)%8, 1)
|
||||
selfp.checker.sector += 1
|
||||
selfp.checker.count = max((selfp.checker.count + 1)%8, 1)
|
||||
|
||||
if __name__ == "__main__":
|
||||
run_simulation(TB(), ncycles=8192*2, vcd_name="my.vcd", keep_files=True)
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
from litesata.common import *
|
||||
from litesata.core import LiteSATACore
|
||||
|
||||
from litesata.test.hdd import *
|
||||
from litesata.test.common import *
|
||||
|
||||
class CommandTXPacket(list):
|
||||
def __init__(self, write=0, read=0, sector=0, count=0, data=[]):
|
||||
self.ongoing = False
|
||||
self.done = False
|
||||
self.write = write
|
||||
self.read = read
|
||||
self.sector = sector
|
||||
self.count = count
|
||||
for d in data:
|
||||
self.append(d)
|
||||
|
||||
class CommandStreamer(PacketStreamer):
|
||||
def __init__(self):
|
||||
PacketStreamer.__init__(self, command_tx_description(32), CommandTXPacket)
|
||||
|
||||
def do_simulation(self, selfp):
|
||||
PacketStreamer.do_simulation(self, selfp)
|
||||
selfp.source.write = self.packet.write
|
||||
selfp.source.read = self.packet.read
|
||||
selfp.source.sector = self.packet.sector
|
||||
selfp.source.count = self.packet.count
|
||||
|
||||
class CommandRXPacket(list):
|
||||
def __init__(self):
|
||||
self.ongoing = False
|
||||
self.done = False
|
||||
self.write = 0
|
||||
self.read = 0
|
||||
self.failed = 0
|
||||
|
||||
class CommandLogger(PacketLogger):
|
||||
def __init__(self):
|
||||
PacketLogger.__init__(self, command_rx_description(32), CommandRXPacket)
|
||||
|
||||
def do_simulation(self, selfp):
|
||||
selfp.sink.ack = 1
|
||||
if selfp.sink.stb == 1 and selfp.sink.sop == 1:
|
||||
self.packet = CommandRXPacket()
|
||||
self.packet.write = selfp.sink.write
|
||||
self.packet.read = selfp.sink.read
|
||||
self.packet.failed = selfp.sink.failed
|
||||
self.packet.append(selfp.sink.data)
|
||||
elif selfp.sink.stb:
|
||||
self.packet.append(selfp.sink.data)
|
||||
if selfp.sink.stb == 1 and selfp.sink.eop == 1:
|
||||
self.packet.done = True
|
||||
|
||||
class TB(Module):
|
||||
def __init__(self):
|
||||
self.submodules.hdd = HDD(
|
||||
link_debug=False, link_random_level=50,
|
||||
transport_debug=False, transport_loopback=False,
|
||||
hdd_debug=True)
|
||||
self.submodules.core = LiteSATACore(self.hdd.phy, buffer_depth=512)
|
||||
|
||||
self.submodules.streamer = CommandStreamer()
|
||||
self.submodules.streamer_randomizer = Randomizer(command_tx_description(32), level=50)
|
||||
|
||||
self.submodules.logger = CommandLogger()
|
||||
self.submodules.logger_randomizer = Randomizer(command_rx_description(32), level=50)
|
||||
|
||||
self.submodules.pipeline = Pipeline(
|
||||
self.streamer,
|
||||
self.streamer_randomizer,
|
||||
self.core,
|
||||
self.logger_randomizer,
|
||||
self.logger
|
||||
)
|
||||
|
||||
def gen_simulation(self, selfp):
|
||||
hdd = self.hdd
|
||||
hdd.malloc(0, 64)
|
||||
write_data = [i for i in range(sectors2dwords(2))]
|
||||
write_len = dwords2sectors(len(write_data))
|
||||
write_packet = CommandTXPacket(write=1, sector=2, count=write_len, data=write_data)
|
||||
yield from self.streamer.send(write_packet)
|
||||
yield from self.logger.receive()
|
||||
read_packet = CommandTXPacket(read=1, sector=2, count=write_len)
|
||||
yield from self.streamer.send(read_packet)
|
||||
yield from self.logger.receive()
|
||||
read_data = self.logger.packet
|
||||
|
||||
# check results
|
||||
s, l, e = check(write_data, read_data)
|
||||
print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
|
||||
|
||||
if __name__ == "__main__":
|
||||
run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)
|
||||
|
|
@ -0,0 +1,135 @@
|
|||
import random, copy
|
||||
|
||||
from migen.sim.generic import run_simulation
|
||||
|
||||
from litesata.common import *
|
||||
|
||||
def seed_to_data(seed, random=True):
|
||||
if random:
|
||||
return (seed * 0x31415979 + 1) & 0xffffffff
|
||||
else:
|
||||
return seed
|
||||
|
||||
def check(p1, p2):
|
||||
p1 = copy.deepcopy(p1)
|
||||
p2 = copy.deepcopy(p2)
|
||||
if isinstance(p1, int):
|
||||
return 0, 1, int(p1 != p2)
|
||||
else:
|
||||
if len(p1) >= len(p2):
|
||||
ref, res = p1, p2
|
||||
else:
|
||||
ref, res = p2, p1
|
||||
shift = 0
|
||||
while((ref[0] != res[0]) and (len(res)>1)):
|
||||
res.pop(0)
|
||||
shift += 1
|
||||
length = min(len(ref), len(res))
|
||||
errors = 0
|
||||
for i in range(length):
|
||||
if ref.pop(0) != res.pop(0):
|
||||
errors += 1
|
||||
return shift, length, errors
|
||||
|
||||
def randn(max_n):
|
||||
return random.randint(0, max_n-1)
|
||||
|
||||
class PacketStreamer(Module):
|
||||
def __init__(self, description, packet_class):
|
||||
self.source = Source(description)
|
||||
###
|
||||
self.packets = []
|
||||
self.packet = packet_class()
|
||||
self.packet.done = 1
|
||||
|
||||
self.source_data = 0
|
||||
|
||||
def send(self, packet, blocking=True):
|
||||
packet = copy.deepcopy(packet)
|
||||
self.packets.append(packet)
|
||||
if blocking:
|
||||
while packet.done == 0:
|
||||
yield
|
||||
|
||||
def do_simulation(self, selfp):
|
||||
if len(self.packets) and self.packet.done:
|
||||
self.packet = self.packets.pop(0)
|
||||
if not self.packet.ongoing and not self.packet.done:
|
||||
selfp.source.stb = 1
|
||||
if self.source.description.packetized:
|
||||
selfp.source.sop = 1
|
||||
if len(self.packet) > 0:
|
||||
self.source_data = self.packet.pop(0)
|
||||
if hasattr(selfp.source, "data"):
|
||||
selfp.source.data = self.source_data
|
||||
else:
|
||||
selfp.source.d = self.source_data
|
||||
self.packet.ongoing = True
|
||||
elif selfp.source.stb == 1 and selfp.source.ack == 1:
|
||||
if self.source.description.packetized:
|
||||
selfp.source.sop = 0
|
||||
selfp.source.eop = (len(self.packet) == 1)
|
||||
if len(self.packet) > 0:
|
||||
selfp.source.stb = 1
|
||||
self.source_data = self.packet.pop(0)
|
||||
if hasattr(selfp.source, "data"):
|
||||
selfp.source.data = self.source_data
|
||||
else:
|
||||
selfp.source.d = self.source_data
|
||||
else:
|
||||
self.packet.done = 1
|
||||
selfp.source.stb = 0
|
||||
|
||||
class PacketLogger(Module):
|
||||
def __init__(self, description, packet_class):
|
||||
self.sink = Sink(description)
|
||||
###
|
||||
self.packet_class = packet_class
|
||||
self.packet = packet_class()
|
||||
|
||||
def receive(self, length=None):
|
||||
self.packet.done = 0
|
||||
if length is None:
|
||||
while self.packet.done == 0:
|
||||
yield
|
||||
else:
|
||||
while length > len(self.packet):
|
||||
yield
|
||||
|
||||
def do_simulation(self, selfp):
|
||||
selfp.sink.ack = 1
|
||||
if self.sink.description.packetized:
|
||||
if selfp.sink.stb == 1 and selfp.sink.sop == 1:
|
||||
self.packet = self.packet_class()
|
||||
if selfp.sink.stb:
|
||||
if hasattr(selfp.sink, "data"):
|
||||
self.packet.append(selfp.sink.data)
|
||||
else:
|
||||
self.packet.append(selfp.sink.d)
|
||||
if self.sink.description.packetized:
|
||||
if selfp.sink.stb == 1 and selfp.sink.eop == 1:
|
||||
self.packet.done = True
|
||||
|
||||
class Randomizer(Module):
|
||||
def __init__(self, description, level=0):
|
||||
self.level = level
|
||||
|
||||
self.sink = Sink(description)
|
||||
self.source = Source(description)
|
||||
|
||||
self.run = Signal()
|
||||
|
||||
self.comb += \
|
||||
If(self.run,
|
||||
Record.connect(self.sink, self.source)
|
||||
).Else(
|
||||
self.source.stb.eq(0),
|
||||
self.sink.ack.eq(0),
|
||||
)
|
||||
|
||||
def do_simulation(self, selfp):
|
||||
n = randn(100)
|
||||
if n < self.level:
|
||||
selfp.run = 0
|
||||
else:
|
||||
selfp.run = 1
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
from litesata.common import *
|
||||
from litesata.core.link.cont import LiteSATACONTInserter, LiteSATACONTRemover
|
||||
|
||||
from litesata.test.common import *
|
||||
|
||||
class ContPacket(list):
|
||||
def __init__(self, data=[]):
|
||||
self.ongoing = False
|
||||
self.done = False
|
||||
for d in data:
|
||||
self.append(d)
|
||||
|
||||
class ContStreamer(PacketStreamer):
|
||||
def __init__(self):
|
||||
PacketStreamer.__init__(self, phy_description(32), ContPacket)
|
||||
|
||||
def do_simulation(self, selfp):
|
||||
PacketStreamer.do_simulation(self, selfp)
|
||||
selfp.source.charisk = 0
|
||||
# Note: for simplicity we generate charisk by detecting
|
||||
# primitives in data
|
||||
for k, v in primitives.items():
|
||||
try:
|
||||
if self.source_data == v:
|
||||
selfp.source.charisk = 0b0001
|
||||
except:
|
||||
pass
|
||||
|
||||
class ContLogger(PacketLogger):
|
||||
def __init__(self):
|
||||
PacketLogger.__init__(self, phy_description(32), ContPacket)
|
||||
|
||||
class TB(Module):
|
||||
def __init__(self):
|
||||
self.submodules.streamer = ContStreamer()
|
||||
self.submodules.streamer_randomizer = Randomizer(phy_description(32), level=50)
|
||||
self.submodules.inserter = LiteSATACONTInserter(phy_description(32))
|
||||
self.submodules.remover = LiteSATACONTRemover(phy_description(32))
|
||||
self.submodules.logger_randomizer = Randomizer(phy_description(32), level=50)
|
||||
self.submodules.logger = ContLogger()
|
||||
|
||||
self.submodules.pipeline = Pipeline(
|
||||
self.streamer,
|
||||
self.streamer_randomizer,
|
||||
self.inserter,
|
||||
self.remover,
|
||||
self.logger_randomizer,
|
||||
self.logger
|
||||
)
|
||||
|
||||
def gen_simulation(self, selfp):
|
||||
test_packet = ContPacket([
|
||||
primitives["SYNC"],
|
||||
primitives["SYNC"],
|
||||
primitives["SYNC"],
|
||||
primitives["SYNC"],
|
||||
primitives["SYNC"],
|
||||
primitives["SYNC"],
|
||||
primitives["ALIGN"],
|
||||
primitives["ALIGN"],
|
||||
primitives["SYNC"],
|
||||
primitives["SYNC"],
|
||||
#primitives["SYNC"],
|
||||
0x00000000,
|
||||
0x00000001,
|
||||
0x00000002,
|
||||
0x00000003,
|
||||
0x00000004,
|
||||
0x00000005,
|
||||
0x00000006,
|
||||
0x00000007,
|
||||
primitives["SYNC"],
|
||||
primitives["SYNC"],
|
||||
primitives["SYNC"],
|
||||
primitives["SYNC"],
|
||||
primitives["ALIGN"],
|
||||
primitives["ALIGN"],
|
||||
primitives["SYNC"],
|
||||
primitives["SYNC"],
|
||||
primitives["SYNC"],
|
||||
primitives["SYNC"]]*4
|
||||
)
|
||||
streamer_packet = ContPacket(test_packet)
|
||||
yield from self.streamer.send(streamer_packet)
|
||||
yield from self.logger.receive(len(test_packet))
|
||||
#for d in self.logger.packet:
|
||||
# print("%08x" %d)
|
||||
|
||||
# check results
|
||||
s, l, e = check(streamer_packet, self.logger.packet)
|
||||
print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
run_simulation(TB(), ncycles=1024, vcd_name="my.vcd", keep_files=True)
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
// Adapted from SATA specification
|
||||
/****************************************************************************/
|
||||
/* */
|
||||
/* crc.c */
|
||||
/* */
|
||||
/* This sample code reads standard in for a sequence of 32 bit values */
|
||||
/* formatted in hexadecimal with a leading "0x" (e.g. 0xDEADBEEF). The */
|
||||
/* code calculates the Serial ATA CRC for the input data stream. The */
|
||||
/* generator polynomial used is: */
|
||||
/* 32 26 23 22 16 12 11 10 8 7 5 4 2 */
|
||||
/* G(x) = x + x + x + x + x + x + x + x + x + x + x + x + x + x + 1 */
|
||||
/* */
|
||||
/* This sample code uses a parallel implementation of the CRC calculation */
|
||||
/* circuit that is suitable for implementation in hardware. A block */
|
||||
/* diagram of the circuit being emulated is shown below. */
|
||||
/* */
|
||||
/* +---+ +---+ +---+ */
|
||||
/* Data_In --------->| | | | | R | */
|
||||
/* | + |--------->| * |--------->| e |----+ */
|
||||
/* +---->| | | | | g | | */
|
||||
/* | +---+ +---+ +---+ | */
|
||||
/* | | */
|
||||
/* | | */
|
||||
/* +--------------------------------------------+ */
|
||||
/* */
|
||||
/* The CRC value is initialized to 0x52325032 as defined in the Serial ATA */
|
||||
/* specification. */
|
||||
/* */
|
||||
/****************************************************************************/
|
||||
|
||||
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
int i;
|
||||
unsigned int data_count;
|
||||
unsigned int crc;
|
||||
unsigned int data_in;
|
||||
unsigned char crc_bit[32];
|
||||
unsigned char new_bit[32];
|
||||
|
||||
crc = 0x52325032;
|
||||
data_count = 0;
|
||||
|
||||
while((scanf(" 0x%8x", &data_in) == 1) && (!scanf("exit"))) {
|
||||
data_count++;
|
||||
/* Add the data_in value to the current value of the CRC held in the */
|
||||
/* "register". The addition is performed modulo two (XOR). */
|
||||
crc ^= data_in;
|
||||
/* Expand the value of the CRC held in the register to 32 individual */
|
||||
/* bits for easy manipulation. */
|
||||
for (i = 0; i < 32; ++i) {
|
||||
crc_bit[i] = (crc >> i) & 0x01;
|
||||
}
|
||||
/* The following 32 assignments perform the function of the box */
|
||||
/* labeled "*" in the block diagram above. The new_bit array is a */
|
||||
/* temporary holding place for the new CRC value being calculated. */
|
||||
/* Note that there are lots of shared terms in the assignments below. */
|
||||
new_bit[31] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[29] ^ crc_bit[28] ^ crc_bit[27] ^ crc_bit[25] ^ crc_bit[24] ^
|
||||
crc_bit[23] ^ crc_bit[15] ^ crc_bit[11] ^ crc_bit[9] ^ crc_bit[8] ^ crc_bit[5];
|
||||
new_bit[30] = crc_bit[30] ^ crc_bit[29] ^ crc_bit[28] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[24] ^ crc_bit[23] ^
|
||||
crc_bit[22] ^ crc_bit[14] ^ crc_bit[10] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[4];
|
||||
new_bit[29] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[28] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[23] ^
|
||||
crc_bit[22] ^ crc_bit[21] ^ crc_bit[13] ^ crc_bit[9] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[3];
|
||||
new_bit[28] = crc_bit[30] ^ crc_bit[28] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[22] ^
|
||||
crc_bit[21] ^ crc_bit[20] ^ crc_bit[12] ^ crc_bit[8] ^ crc_bit[6] ^ crc_bit[5] ^ crc_bit[2];
|
||||
new_bit[27] = crc_bit[29] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[23] ^ crc_bit[21] ^
|
||||
crc_bit[20] ^ crc_bit[19] ^ crc_bit[11] ^ crc_bit[7] ^ crc_bit[5] ^ crc_bit[4] ^ crc_bit[1];
|
||||
new_bit[26] = crc_bit[31] ^ crc_bit[28] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[23] ^ crc_bit[22] ^
|
||||
crc_bit[20] ^ crc_bit[19] ^ crc_bit[18] ^ crc_bit[10] ^ crc_bit[6] ^ crc_bit[4] ^ crc_bit[3] ^
|
||||
crc_bit[0];
|
||||
new_bit[25] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[28] ^ crc_bit[22] ^ crc_bit[21] ^ crc_bit[19] ^ crc_bit[18] ^
|
||||
crc_bit[17] ^ crc_bit[15] ^ crc_bit[11] ^ crc_bit[8] ^ crc_bit[3] ^ crc_bit[2];
|
||||
new_bit[24] = crc_bit[30] ^ crc_bit[28] ^ crc_bit[27] ^ crc_bit[21] ^ crc_bit[20] ^ crc_bit[18] ^ crc_bit[17] ^
|
||||
crc_bit[16] ^ crc_bit[14] ^ crc_bit[10] ^ crc_bit[7] ^ crc_bit[2] ^ crc_bit[1];
|
||||
new_bit[23] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[20] ^ crc_bit[19] ^ crc_bit[17] ^
|
||||
crc_bit[16] ^ crc_bit[15] ^ crc_bit[13] ^ crc_bit[9] ^ crc_bit[6] ^ crc_bit[1] ^ crc_bit[0];
|
||||
new_bit[22] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[24] ^ crc_bit[23] ^ crc_bit[19] ^
|
||||
crc_bit[18] ^ crc_bit[16] ^ crc_bit[14] ^ crc_bit[12] ^ crc_bit[11] ^ crc_bit[9] ^ crc_bit[0];
|
||||
new_bit[21] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[24] ^ crc_bit[22] ^ crc_bit[18] ^
|
||||
crc_bit[17] ^ crc_bit[13] ^ crc_bit[10] ^ crc_bit[9] ^ crc_bit[5];
|
||||
new_bit[20] = crc_bit[30] ^ crc_bit[28] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[23] ^ crc_bit[21] ^ crc_bit[17] ^
|
||||
crc_bit[16] ^ crc_bit[12] ^ crc_bit[9] ^ crc_bit[8] ^ crc_bit[4];
|
||||
new_bit[19] = crc_bit[29] ^ crc_bit[27] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[22] ^ crc_bit[20] ^ crc_bit[16] ^
|
||||
crc_bit[15] ^ crc_bit[11] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[3];
|
||||
new_bit[18] = crc_bit[31] ^ crc_bit[28] ^ crc_bit[26] ^ crc_bit[24] ^ crc_bit[23] ^ crc_bit[21] ^ crc_bit[19] ^
|
||||
crc_bit[15] ^ crc_bit[14] ^ crc_bit[10] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[2];
|
||||
new_bit[17] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[27] ^ crc_bit[25] ^ crc_bit[23] ^ crc_bit[22] ^ crc_bit[20] ^
|
||||
crc_bit[18] ^ crc_bit[14] ^ crc_bit[13] ^ crc_bit[9] ^ crc_bit[6] ^ crc_bit[5] ^ crc_bit[1];
|
||||
new_bit[16] = crc_bit[30] ^ crc_bit[29] ^ crc_bit[26] ^ crc_bit[24] ^ crc_bit[22] ^ crc_bit[21] ^ crc_bit[19] ^
|
||||
crc_bit[17] ^ crc_bit[13] ^ crc_bit[12] ^ crc_bit[8] ^ crc_bit[5] ^ crc_bit[4] ^ crc_bit[0];
|
||||
new_bit[15] = crc_bit[30] ^ crc_bit[27] ^ crc_bit[24] ^ crc_bit[21] ^ crc_bit[20] ^ crc_bit[18] ^ crc_bit[16] ^
|
||||
crc_bit[15] ^ crc_bit[12] ^ crc_bit[9] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[5] ^ crc_bit[4] ^
|
||||
crc_bit[3];
|
||||
new_bit[14] = crc_bit[29] ^ crc_bit[26] ^ crc_bit[23] ^ crc_bit[20] ^ crc_bit[19] ^ crc_bit[17] ^ crc_bit[15] ^
|
||||
crc_bit[14] ^ crc_bit[11] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[4] ^ crc_bit[3] ^
|
||||
crc_bit[2];
|
||||
new_bit[13] = crc_bit[31] ^ crc_bit[28] ^ crc_bit[25] ^ crc_bit[22] ^ crc_bit[19] ^ crc_bit[18] ^ crc_bit[16] ^
|
||||
crc_bit[14] ^ crc_bit[13] ^ crc_bit[10] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[5] ^ crc_bit[3] ^
|
||||
crc_bit[2] ^ crc_bit[1];
|
||||
new_bit[12] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[27] ^ crc_bit[24] ^ crc_bit[21] ^ crc_bit[18] ^ crc_bit[17] ^
|
||||
crc_bit[15] ^ crc_bit[13] ^ crc_bit[12] ^ crc_bit[9] ^ crc_bit[6] ^ crc_bit[5] ^ crc_bit[4] ^
|
||||
crc_bit[2] ^ crc_bit[1] ^ crc_bit[0];
|
||||
new_bit[11] = crc_bit[31] ^ crc_bit[28] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[20] ^
|
||||
crc_bit[17] ^ crc_bit[16] ^ crc_bit[15] ^ crc_bit[14] ^ crc_bit[12] ^ crc_bit[9] ^ crc_bit[4] ^
|
||||
crc_bit[3] ^ crc_bit[1] ^ crc_bit[0];
|
||||
new_bit[10] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[28] ^ crc_bit[26] ^ crc_bit[19] ^ crc_bit[16] ^ crc_bit[14] ^
|
||||
crc_bit[13] ^ crc_bit[9] ^ crc_bit[5] ^ crc_bit[3] ^ crc_bit[2] ^ crc_bit[0];
|
||||
new_bit[9] = crc_bit[29] ^ crc_bit[24] ^ crc_bit[23] ^ crc_bit[18] ^ crc_bit[13] ^ crc_bit[12] ^ crc_bit[11] ^
|
||||
crc_bit[9] ^ crc_bit[5] ^ crc_bit[4] ^ crc_bit[2] ^ crc_bit[1];
|
||||
new_bit[8] = crc_bit[31] ^ crc_bit[28] ^ crc_bit[23] ^ crc_bit[22] ^ crc_bit[17] ^ crc_bit[12] ^ crc_bit[11] ^
|
||||
crc_bit[10] ^ crc_bit[8] ^ crc_bit[4] ^ crc_bit[3] ^ crc_bit[1] ^ crc_bit[0];
|
||||
new_bit[7] = crc_bit[29] ^ crc_bit[28] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[23] ^ crc_bit[22] ^ crc_bit[21] ^
|
||||
crc_bit[16] ^ crc_bit[15] ^ crc_bit[10] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[5] ^ crc_bit[3] ^
|
||||
crc_bit[2] ^ crc_bit[0];
|
||||
new_bit[6] = crc_bit[30] ^ crc_bit[29] ^ crc_bit[25] ^ crc_bit[22] ^ crc_bit[21] ^ crc_bit[20] ^ crc_bit[14] ^
|
||||
crc_bit[11] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[5] ^ crc_bit[4] ^ crc_bit[2] ^
|
||||
crc_bit[1];
|
||||
new_bit[5] = crc_bit[29] ^ crc_bit[28] ^ crc_bit[24] ^ crc_bit[21] ^ crc_bit[20] ^ crc_bit[19] ^ crc_bit[13] ^
|
||||
crc_bit[10] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[5] ^ crc_bit[4] ^ crc_bit[3] ^ crc_bit[1] ^
|
||||
crc_bit[0];
|
||||
new_bit[4] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[29] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[20] ^ crc_bit[19] ^
|
||||
crc_bit[18] ^ crc_bit[15] ^ crc_bit[12] ^ crc_bit[11] ^ crc_bit[8] ^ crc_bit[6] ^ crc_bit[4] ^
|
||||
crc_bit[3] ^ crc_bit[2] ^ crc_bit[0];
|
||||
new_bit[3] = crc_bit[31] ^ crc_bit[27] ^ crc_bit[25] ^ crc_bit[19] ^ crc_bit[18] ^ crc_bit[17] ^ crc_bit[15] ^
|
||||
crc_bit[14] ^ crc_bit[10] ^ crc_bit[9] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[3] ^ crc_bit[2] ^
|
||||
crc_bit[1];
|
||||
new_bit[2] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[26] ^ crc_bit[24] ^ crc_bit[18] ^ crc_bit[17] ^ crc_bit[16] ^
|
||||
crc_bit[14] ^ crc_bit[13] ^ crc_bit[9] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[2] ^
|
||||
crc_bit[1] ^ crc_bit[0];
|
||||
new_bit[1] = crc_bit[28] ^ crc_bit[27] ^ crc_bit[24] ^ crc_bit[17] ^ crc_bit[16] ^ crc_bit[13] ^ crc_bit[12] ^
|
||||
crc_bit[11] ^ crc_bit[9] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[1] ^ crc_bit[0];
|
||||
new_bit[0] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[29] ^ crc_bit[28] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[24] ^
|
||||
crc_bit[16] ^ crc_bit[12] ^ crc_bit[10] ^ crc_bit[9] ^ crc_bit[6] ^ crc_bit[0];
|
||||
|
||||
/* The new CRC value has been calculated as individual bits in the */
|
||||
/* new_bit array. Re-assembled it into a 32 bit value and "clock" it */
|
||||
/* into the "register". */
|
||||
crc = 0;
|
||||
for (i = 31; i >= 0; --i) {
|
||||
crc = crc << 1;
|
||||
crc |= new_bit[i];
|
||||
}
|
||||
}
|
||||
printf("%08x\n", crc);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
import subprocess
|
||||
|
||||
from litesata.common import *
|
||||
from litesata.core.link.crc import *
|
||||
|
||||
from litesata.test.common import *
|
||||
|
||||
class TB(Module):
|
||||
def __init__(self, length, random):
|
||||
self.submodules.crc = LiteSATACRC()
|
||||
self.length = length
|
||||
self.random = random
|
||||
|
||||
def get_c_crc(self, datas):
|
||||
stdin = ""
|
||||
for data in datas:
|
||||
stdin += "0x%08x " %data
|
||||
stdin += "exit"
|
||||
with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
|
||||
process.stdin.write(stdin.encode("ASCII"))
|
||||
out, err = process.communicate()
|
||||
return int(out.decode("ASCII"), 16)
|
||||
|
||||
def gen_simulation(self, selfp):
|
||||
# init CRC
|
||||
selfp.crc.d = 0
|
||||
selfp.crc.ce = 1
|
||||
selfp.crc.reset = 1
|
||||
yield
|
||||
selfp.crc.reset = 0
|
||||
|
||||
# feed CRC with datas
|
||||
datas = []
|
||||
for i in range(self.length):
|
||||
data = seed_to_data(i, self.random)
|
||||
datas.append(data)
|
||||
selfp.crc.d = data
|
||||
yield
|
||||
|
||||
# log results
|
||||
yield
|
||||
sim_crc = selfp.crc.value
|
||||
|
||||
# stop
|
||||
selfp.crc.ce = 0
|
||||
for i in range(32):
|
||||
yield
|
||||
|
||||
# get C core reference
|
||||
c_crc = self.get_c_crc(datas)
|
||||
|
||||
# check results
|
||||
s, l, e = check(c_crc, sim_crc)
|
||||
print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
|
||||
|
||||
if __name__ == "__main__":
|
||||
from migen.sim.generic import run_simulation
|
||||
length = 8192
|
||||
run_simulation(TB(length, True), ncycles=length+100, vcd_name="my.vcd")
|
||||
|
|
@ -0,0 +1,511 @@
|
|||
import subprocess
|
||||
import math
|
||||
|
||||
from litesata.common import *
|
||||
from litesata.test.common import *
|
||||
|
||||
def print_with_prefix(s, prefix=""):
|
||||
if not isinstance(s, str):
|
||||
s = s.__repr__()
|
||||
s = s.split("\n")
|
||||
for l in s:
|
||||
print(prefix + l)
|
||||
|
||||
# PHY Layer model
|
||||
class PHYDword:
|
||||
def __init__(self, dat=0):
|
||||
self.dat = dat
|
||||
self.start = 1
|
||||
self.done = 0
|
||||
|
||||
class PHYSource(Module):
|
||||
def __init__(self):
|
||||
self.source = Source(phy_description(32))
|
||||
###
|
||||
self.dword = PHYDword()
|
||||
|
||||
def send(self, dword):
|
||||
self.dword = dword
|
||||
|
||||
def do_simulation(self, selfp):
|
||||
selfp.source.stb = 1
|
||||
selfp.source.charisk = 0b0000
|
||||
for k, v in primitives.items():
|
||||
if v == self.dword.dat:
|
||||
selfp.source.charisk = 0b0001
|
||||
selfp.source.data = self.dword.dat
|
||||
|
||||
class PHYSink(Module):
|
||||
def __init__(self):
|
||||
self.sink = Sink(phy_description(32))
|
||||
###
|
||||
self.dword = PHYDword()
|
||||
|
||||
def receive(self):
|
||||
self.dword.done = 0
|
||||
while self.dword.done == 0:
|
||||
yield
|
||||
|
||||
def do_simulation(self, selfp):
|
||||
self.dword.done = 0
|
||||
selfp.sink.ack = 1
|
||||
if selfp.sink.stb == 1:
|
||||
self.dword.done = 1
|
||||
self.dword.dat = selfp.sink.data
|
||||
|
||||
class PHYLayer(Module):
|
||||
def __init__(self):
|
||||
|
||||
self.submodules.rx = PHYSink()
|
||||
self.submodules.tx = PHYSource()
|
||||
|
||||
self.source = self.tx.source
|
||||
self.sink = self.rx.sink
|
||||
|
||||
def send(self, dword):
|
||||
packet = PHYDword(dword)
|
||||
self.tx.send(packet)
|
||||
|
||||
def receive(self):
|
||||
yield from self.rx.receive()
|
||||
|
||||
def __repr__(self):
|
||||
receiving = "%08x " %self.rx.dword.dat
|
||||
receiving += decode_primitive(self.rx.dword.dat)
|
||||
receiving += " "*(16-len(receiving))
|
||||
|
||||
sending = "%08x " %self.tx.dword.dat
|
||||
sending += decode_primitive(self.tx.dword.dat)
|
||||
sending += " "*(16-len(sending))
|
||||
|
||||
return receiving + sending
|
||||
|
||||
# Link Layer model
|
||||
def print_link(s):
|
||||
print_with_prefix(s, "[LNK]: ")
|
||||
|
||||
def import_scrambler_datas():
|
||||
with subprocess.Popen(["./scrambler"], stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
|
||||
process.stdin.write("0x10000".encode("ASCII"))
|
||||
out, err = process.communicate()
|
||||
return [int(e, 16) for e in out.decode("utf-8").split("\n")[:-1]]
|
||||
|
||||
class LinkPacket(list):
|
||||
def __init__(self, init=[]):
|
||||
self.ongoing = False
|
||||
self.done = False
|
||||
self.scrambled_datas = import_scrambler_datas()
|
||||
for dword in init:
|
||||
self.append(dword)
|
||||
|
||||
class LinkRXPacket(LinkPacket):
|
||||
def descramble(self):
|
||||
for i in range(len(self)):
|
||||
self[i] = self[i] ^ self.scrambled_datas[i]
|
||||
|
||||
def check_crc(self):
|
||||
stdin = ""
|
||||
for v in self[:-1]:
|
||||
stdin += "0x%08x " %v
|
||||
stdin += "exit"
|
||||
with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
|
||||
process.stdin.write(stdin.encode("ASCII"))
|
||||
out, err = process.communicate()
|
||||
crc = int(out.decode("ASCII"), 16)
|
||||
r = (self[-1] == crc)
|
||||
self.pop()
|
||||
return r
|
||||
|
||||
def decode(self):
|
||||
self.descramble()
|
||||
return self.check_crc()
|
||||
|
||||
class LinkTXPacket(LinkPacket):
|
||||
def insert_crc(self):
|
||||
stdin = ""
|
||||
for v in self:
|
||||
stdin += "0x%08x " %v
|
||||
stdin += "exit"
|
||||
with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
|
||||
process.stdin.write(stdin.encode("ASCII"))
|
||||
out, err = process.communicate()
|
||||
crc = int(out.decode("ASCII"), 16)
|
||||
self.append(crc)
|
||||
|
||||
def scramble(self):
|
||||
for i in range(len(self)):
|
||||
self[i] = self[i] ^ self.scrambled_datas[i]
|
||||
|
||||
def encode(self):
|
||||
self.insert_crc()
|
||||
self.scramble()
|
||||
|
||||
class LinkLayer(Module):
|
||||
def __init__(self, phy, debug=False, random_level=0):
|
||||
self.phy = phy
|
||||
self.debug = debug
|
||||
self.random_level = random_level
|
||||
self.tx_packets = []
|
||||
self.tx_packet = LinkTXPacket()
|
||||
self.rx_packet = LinkRXPacket()
|
||||
|
||||
self.rx_cont = False
|
||||
self.rx_last = 0
|
||||
self.tx_cont = False
|
||||
self.tx_cont_nb = -1
|
||||
self.tx_lasts = [0, 0, 0]
|
||||
|
||||
self.scrambled_datas = import_scrambler_datas()
|
||||
|
||||
self.transport_callback = None
|
||||
|
||||
self.send_state = ""
|
||||
self.send_states = ["RDY", "SOF", "DATA", "EOF", "WTRM"]
|
||||
|
||||
def set_transport_callback(self, callback):
|
||||
self.transport_callback = callback
|
||||
|
||||
def send(self, dword):
|
||||
if self.send_state == "RDY":
|
||||
self.phy.send(primitives["X_RDY"])
|
||||
if dword == primitives["R_RDY"]:
|
||||
self.send_state = "SOF"
|
||||
elif self.send_state == "SOF":
|
||||
self.phy.send(primitives["SOF"])
|
||||
self.send_state = "DATA"
|
||||
elif self.send_state == "DATA":
|
||||
if dword == primitives["HOLD"]:
|
||||
self.phy.send(primitives["HOLDA"])
|
||||
else:
|
||||
self.phy.send(self.tx_packet.pop(0))
|
||||
if len(self.tx_packet) == 0:
|
||||
self.send_state = "EOF"
|
||||
elif self.send_state == "EOF":
|
||||
self.phy.send(primitives["EOF"])
|
||||
self.send_state = "WTRM"
|
||||
elif self.send_state == "WTRM":
|
||||
self.phy.send(primitives["WTRM"])
|
||||
if dword == primitives["R_OK"]:
|
||||
self.tx_packet.done = True
|
||||
elif dword == primitives["R_ERR"]:
|
||||
self.tx_packet.done = True
|
||||
if self.tx_packet.done:
|
||||
self.phy.send(primitives["SYNC"])
|
||||
|
||||
def insert_cont(self):
|
||||
self.tx_lasts.pop(0)
|
||||
self.tx_lasts.append(self.phy.tx.dword.dat)
|
||||
self.tx_cont = True
|
||||
for i in range(3):
|
||||
if not is_primitive(self.tx_lasts[i]):
|
||||
self.tx_cont = False
|
||||
if self.tx_lasts[i] != self.tx_lasts[0]:
|
||||
self.tx_cont = False
|
||||
if self.tx_cont:
|
||||
if self.tx_cont_nb == 0:
|
||||
self.phy.send(primitives["CONT"])
|
||||
else:
|
||||
self.phy.send(self.scrambled_datas[self.tx_cont_nb])
|
||||
self.tx_cont_nb += 1
|
||||
else:
|
||||
self.tx_cont_nb = 0
|
||||
|
||||
def remove_cont(self, dword):
|
||||
if dword == primitives["HOLD"]:
|
||||
if self.rx_cont:
|
||||
self.tx_lasts = [0, 0, 0]
|
||||
if dword == primitives["CONT"]:
|
||||
self.rx_cont = True
|
||||
elif is_primitive(dword):
|
||||
self.rx_last = dword
|
||||
self.rx_cont = False
|
||||
if self.rx_cont:
|
||||
dword = self.rx_last
|
||||
return dword
|
||||
|
||||
def callback(self, dword):
|
||||
if dword == primitives["X_RDY"]:
|
||||
self.phy.send(primitives["R_RDY"])
|
||||
elif dword == primitives["WTRM"]:
|
||||
self.phy.send(primitives["R_OK"])
|
||||
if self.rx_packet.ongoing:
|
||||
self.rx_packet.decode()
|
||||
if self.transport_callback is not None:
|
||||
self.transport_callback(self.rx_packet)
|
||||
self.rx_packet.ongoing = False
|
||||
elif dword == primitives["HOLD"]:
|
||||
self.phy.send(primitives["HOLDA"])
|
||||
elif dword == primitives["EOF"]:
|
||||
pass
|
||||
elif self.rx_packet.ongoing:
|
||||
if dword != primitives["HOLD"]:
|
||||
n = randn(100)
|
||||
if n < self.random_level:
|
||||
self.phy.send(primitives["HOLD"])
|
||||
else:
|
||||
self.phy.send(primitives["R_IP"])
|
||||
if not is_primitive(dword):
|
||||
self.rx_packet.append(dword)
|
||||
elif dword == primitives["SOF"]:
|
||||
self.rx_packet = LinkRXPacket()
|
||||
self.rx_packet.ongoing = True
|
||||
|
||||
def gen_simulation(self, selfp):
|
||||
self.tx_packet.done = True
|
||||
self.phy.send(primitives["SYNC"])
|
||||
while True:
|
||||
yield from self.phy.receive()
|
||||
if self.debug:
|
||||
print_link(self.phy)
|
||||
self.phy.send(primitives["SYNC"])
|
||||
rx_dword = self.phy.rx.dword.dat
|
||||
rx_dword = self.remove_cont(rx_dword)
|
||||
if len(self.tx_packets) != 0:
|
||||
if self.tx_packet.done:
|
||||
self.tx_packet = self.tx_packets.pop(0)
|
||||
self.tx_packet.encode()
|
||||
self.send_state = "RDY"
|
||||
if not self.tx_packet.done:
|
||||
self.send(rx_dword)
|
||||
else:
|
||||
self.callback(rx_dword)
|
||||
self.insert_cont()
|
||||
|
||||
# Transport Layer model
|
||||
def print_transport(s):
|
||||
print_with_prefix(s, "[TRN]: ")
|
||||
|
||||
def get_field_data(field, packet):
|
||||
return (packet[field.dword] >> field.offset) & (2**field.width-1)
|
||||
|
||||
class FIS:
|
||||
def __init__(self, packet, description, direction="H2D"):
|
||||
self.packet = packet
|
||||
self.description = description
|
||||
self.direction = direction
|
||||
self.decode()
|
||||
|
||||
def decode(self):
|
||||
for k, v in self.description.items():
|
||||
setattr(self, k, get_field_data(v, self.packet))
|
||||
|
||||
def encode(self):
|
||||
for k, v in self.description.items():
|
||||
self.packet[v.dword] |= (getattr(self, k) << v.offset)
|
||||
|
||||
def __repr__(self):
|
||||
if self.direction == "H2D":
|
||||
r = ">>>>>>>>\n"
|
||||
else:
|
||||
r = "<<<<<<<<\n"
|
||||
for k in sorted(self.description.keys()):
|
||||
r += k + " : 0x%x" %getattr(self,k) + "\n"
|
||||
return r
|
||||
|
||||
class FIS_REG_H2D(FIS):
|
||||
def __init__(self, packet=[0]*fis_reg_h2d_cmd_len):
|
||||
FIS.__init__(self, packet, fis_reg_h2d_layout)
|
||||
self.type = fis_types["REG_H2D"]
|
||||
self.direction = "H2D"
|
||||
|
||||
def __repr__(self):
|
||||
r = "FIS_REG_H2D\n"
|
||||
r += FIS.__repr__(self)
|
||||
return r
|
||||
|
||||
class FIS_REG_D2H(FIS):
|
||||
def __init__(self, packet=[0]*fis_reg_d2h_cmd_len):
|
||||
FIS.__init__(self, packet, fis_reg_d2h_layout)
|
||||
self.type = fis_types["REG_D2H"]
|
||||
self.direction = "D2H"
|
||||
|
||||
def __repr__(self):
|
||||
r = "FIS_REG_D2H\n"
|
||||
r += FIS.__repr__(self)
|
||||
return r
|
||||
|
||||
class FIS_DMA_ACTIVATE_D2H(FIS):
|
||||
def __init__(self, packet=[0]*fis_dma_activate_d2h_cmd_len):
|
||||
FIS.__init__(self, packet, fis_dma_activate_d2h_layout)
|
||||
self.type = fis_types["DMA_ACTIVATE_D2H"]
|
||||
self.direction = "D2H"
|
||||
|
||||
def __repr__(self):
|
||||
r = "FIS_DMA_ACTIVATE_D2H\n"
|
||||
r += FIS.__repr__(self)
|
||||
return r
|
||||
|
||||
class FIS_DATA(FIS):
|
||||
def __init__(self, packet=[0], direction="H2D"):
|
||||
FIS.__init__(self, packet, fis_data_layout, direction)
|
||||
self.type = fis_types["DATA"]
|
||||
|
||||
def __repr__(self):
|
||||
r = "FIS_DATA\n"
|
||||
r += FIS.__repr__(self)
|
||||
for data in self.packet[1:]:
|
||||
r += "%08x\n" %data
|
||||
return r
|
||||
|
||||
class FIS_UNKNOWN(FIS):
|
||||
def __init__(self, packet=[0], direction="H2D"):
|
||||
FIS.__init__(self, packet, {}, direction)
|
||||
|
||||
def __repr__(self):
|
||||
r = "UNKNOWN\n"
|
||||
if self.direction == "H2D":
|
||||
r += ">>>>>>>>\n"
|
||||
else:
|
||||
r += "<<<<<<<<\n"
|
||||
for dword in self.packet:
|
||||
r += "%08x\n" %dword
|
||||
return r
|
||||
|
||||
class TransportLayer(Module):
|
||||
def __init__(self, link, debug=False, loopback=False):
|
||||
self.link = link
|
||||
self.debug = debug
|
||||
self.loopback = loopback
|
||||
self.link.set_transport_callback(self.callback)
|
||||
|
||||
def set_command_callback(self, callback):
|
||||
self.command_callback = callback
|
||||
|
||||
def send(self, fis):
|
||||
fis.encode()
|
||||
packet = LinkTXPacket(fis.packet)
|
||||
self.link.tx_packets.append(packet)
|
||||
if self.debug and not self.loopback:
|
||||
print_transport(fis)
|
||||
|
||||
def callback(self, packet):
|
||||
fis_type = packet[0] & 0xff
|
||||
if fis_type == fis_types["REG_H2D"]:
|
||||
fis = FIS_REG_H2D(packet)
|
||||
elif fis_type == fis_types["REG_D2H"]:
|
||||
fis = FIS_REG_D2H(packet)
|
||||
elif fis_type == fis_types["DMA_ACTIVATE_D2H"]:
|
||||
fis = FIS_DMA_ACTIVATE_D2H(packet)
|
||||
elif fis_type == fis_types["DATA"]:
|
||||
fis = FIS_DATA(packet, direction="H2D")
|
||||
else:
|
||||
fis = FIS_UNKNOWN(packet, direction="H2D")
|
||||
if self.debug:
|
||||
print_transport(fis)
|
||||
if self.loopback:
|
||||
self.send(fis)
|
||||
else:
|
||||
self.command_callback(fis)
|
||||
|
||||
# Command Layer model
|
||||
class CommandLayer(Module):
|
||||
def __init__(self, transport):
|
||||
self.transport = transport
|
||||
self.transport.set_command_callback(self.callback)
|
||||
|
||||
self.hdd = None
|
||||
|
||||
def set_hdd(self, hdd):
|
||||
self.hdd = hdd
|
||||
|
||||
def callback(self, fis):
|
||||
resp = None
|
||||
if isinstance(fis, FIS_REG_H2D):
|
||||
if fis.command == regs["WRITE_DMA_EXT"]:
|
||||
resp = self.hdd.write_dma_callback(fis)
|
||||
elif fis.command == regs["READ_DMA_EXT"]:
|
||||
resp = self.hdd.read_dma_callback(fis)
|
||||
elif isinstance(fis, FIS_DATA):
|
||||
resp = self.hdd.data_callback(fis)
|
||||
|
||||
if resp is not None:
|
||||
for packet in resp:
|
||||
self.transport.send(packet)
|
||||
|
||||
# HDD model
|
||||
def print_hdd(s):
|
||||
print_with_prefix(s, "[HDD]: ")
|
||||
|
||||
class HDDMemRegion:
|
||||
def __init__(self, base, count, sector_size):
|
||||
self.base = base
|
||||
self.count = count
|
||||
self.data = [0]*(count*sector_size//4)
|
||||
|
||||
class HDD(Module):
|
||||
def __init__(self,
|
||||
link_debug=False, link_random_level=0,
|
||||
transport_debug=False, transport_loopback=False,
|
||||
hdd_debug=False,
|
||||
):
|
||||
###
|
||||
self.submodules.phy = PHYLayer()
|
||||
self.submodules.link = LinkLayer(self.phy, link_debug, link_random_level)
|
||||
self.submodules.transport = TransportLayer(self.link, transport_debug, transport_loopback)
|
||||
self.submodules.command = CommandLayer(self.transport)
|
||||
|
||||
self.command.set_hdd(self)
|
||||
|
||||
self.debug = hdd_debug
|
||||
self.mem = None
|
||||
self.wr_sector = 0
|
||||
self.wr_end_sector = 0
|
||||
self.rd_sector = 0
|
||||
self.rx_end_sector = 0
|
||||
|
||||
def malloc(self, sector, count):
|
||||
if self.debug:
|
||||
s = "Allocating {n} sectors: {s} to {e}".format(n=count, s=sector, e=sector+count)
|
||||
s += " ({} KB)".format(count*logical_sector_size//1024)
|
||||
print_hdd(s)
|
||||
self.mem = HDDMemRegion(sector, count, logical_sector_size)
|
||||
|
||||
def write(self, sector, data):
|
||||
n = math.ceil(dwords2sectors(len(data)))
|
||||
if self.debug:
|
||||
if n == 1:
|
||||
s = "{}".format(sector)
|
||||
else:
|
||||
s = "{s} to {e}".format(s=sector, e=sector+n-1)
|
||||
print_hdd("Writing sector " + s)
|
||||
for i in range(len(data)):
|
||||
offset = sectors2dwords(sector)
|
||||
self.mem.data[offset+i] = data[i]
|
||||
|
||||
def read(self, sector, count):
|
||||
if self.debug:
|
||||
if count == 1:
|
||||
s = "{}".format(sector)
|
||||
else:
|
||||
s = "{s} to {e}".format(s=sector, e=sector+count-1)
|
||||
print_hdd("Reading sector " + s)
|
||||
data = []
|
||||
for i in range(sectors2dwords(count)):
|
||||
data.append(self.mem.data[sectors2dwords(sector)+i])
|
||||
return data
|
||||
|
||||
def write_dma_callback(self, fis):
|
||||
self.wr_sector = fis.lba_lsb + (fis.lba_msb << 32)
|
||||
self.wr_end_sector = self.wr_sector + fis.count
|
||||
return [FIS_DMA_ACTIVATE_D2H()]
|
||||
|
||||
def read_dma_callback(self, fis):
|
||||
self.rd_sector = fis.lba_lsb + (fis.lba_msb << 32)
|
||||
self.rd_end_sector = self.rd_sector + fis.count
|
||||
packets = []
|
||||
while self.rd_sector != self.rd_end_sector:
|
||||
count = min(self.rd_end_sector-self.rd_sector, (fis_max_dwords*4)//logical_sector_size)
|
||||
packet = self.read(self.rd_sector, count)
|
||||
packet.insert(0, 0)
|
||||
packets.append(FIS_DATA(packet, direction="D2H"))
|
||||
self.rd_sector += count
|
||||
packets.append(FIS_REG_D2H())
|
||||
return packets
|
||||
|
||||
def data_callback(self, fis):
|
||||
self.write(self.wr_sector, fis.packet[1:])
|
||||
self.wr_sector += dwords2sectors(len(fis.packet[1:]))
|
||||
if self.wr_sector == self.wr_end_sector:
|
||||
return [FIS_REG_D2H()]
|
||||
else:
|
||||
return [FIS_DMA_ACTIVATE_D2H()]
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
from litesata.common import *
|
||||
from litesata.core.link import LiteSATALink
|
||||
|
||||
from litesata.test.common import *
|
||||
from litesata.test.hdd import *
|
||||
|
||||
class LinkStreamer(PacketStreamer):
|
||||
def __init__(self):
|
||||
PacketStreamer.__init__(self, link_description(32), LinkTXPacket)
|
||||
|
||||
class LinkLogger(PacketLogger):
|
||||
def __init__(self):
|
||||
PacketLogger.__init__(self, link_description(32), LinkRXPacket)
|
||||
|
||||
class TB(Module):
|
||||
def __init__(self):
|
||||
self.submodules.hdd = HDD(
|
||||
link_debug=False, link_random_level=50,
|
||||
transport_debug=False, transport_loopback=True)
|
||||
self.submodules.link = InsertReset(LiteSATALink(self.hdd.phy, buffer_depth=512))
|
||||
|
||||
self.submodules.streamer = LinkStreamer()
|
||||
self.submodules.streamer_randomizer = Randomizer(link_description(32), level=50)
|
||||
|
||||
self.submodules.logger_randomizer = Randomizer(link_description(32), level=50)
|
||||
self.submodules.logger = LinkLogger()
|
||||
|
||||
self.submodules.pipeline = Pipeline(
|
||||
self.streamer,
|
||||
self.streamer_randomizer,
|
||||
self.link,
|
||||
self.logger_randomizer,
|
||||
self.logger
|
||||
)
|
||||
|
||||
def gen_simulation(self, selfp):
|
||||
for i in range(8):
|
||||
streamer_packet = LinkTXPacket([i for i in range(64)])
|
||||
yield from self.streamer.send(streamer_packet)
|
||||
yield from self.logger.receive()
|
||||
|
||||
# check results
|
||||
s, l, e = check(streamer_packet, self.logger.packet)
|
||||
print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
from litesata.common import *
|
||||
from litesata.phy.datapath import LiteSATAPHYDatapath
|
||||
|
||||
from litesata.test.common import *
|
||||
|
||||
class DataPacket(list):
|
||||
def __init__(self, data=[]):
|
||||
self.ongoing = False
|
||||
self.done = False
|
||||
for d in data:
|
||||
self.append(d)
|
||||
|
||||
class DataStreamer(PacketStreamer):
|
||||
def __init__(self):
|
||||
PacketStreamer.__init__(self, phy_description(32), DataPacket)
|
||||
|
||||
def do_simulation(self, selfp):
|
||||
PacketStreamer.do_simulation(self, selfp)
|
||||
selfp.source.charisk = 0
|
||||
# Note: for simplicity we generate charisk by detecting
|
||||
# primitives in data
|
||||
for k, v in primitives.items():
|
||||
try:
|
||||
if self.source_data == v:
|
||||
selfp.source.charisk = 0b0001
|
||||
except:
|
||||
pass
|
||||
|
||||
class DataLogger(PacketLogger):
|
||||
def __init__(self):
|
||||
PacketLogger.__init__(self, phy_description(32), DataPacket)
|
||||
|
||||
class TRX(Module):
|
||||
def __init__(self):
|
||||
self.sink = Sink(phy_description(32))
|
||||
self.source = Source(phy_description(32))
|
||||
self.comb += Record.connect(self.sink, self.source)
|
||||
|
||||
class CTRL(Module):
|
||||
def __init__(self):
|
||||
self.sink = Sink(phy_description(32))
|
||||
self.source = Source(phy_description(32))
|
||||
self.ready = Signal(reset=1)
|
||||
|
||||
class TB(Module):
|
||||
def __init__(self):
|
||||
# use sys_clk for each clock_domain
|
||||
self.clock_domains.cd_sata_rx = ClockDomain()
|
||||
self.clock_domains.cd_sata_tx = ClockDomain()
|
||||
self.comb += [
|
||||
self.cd_sata_rx.clk.eq(ClockSignal()),
|
||||
self.cd_sata_rx.rst.eq(ResetSignal()),
|
||||
self.cd_sata_tx.clk.eq(ClockSignal()),
|
||||
self.cd_sata_tx.rst.eq(ResetSignal()),
|
||||
]
|
||||
|
||||
self.submodules.streamer = DataStreamer()
|
||||
self.submodules.streamer_randomizer = Randomizer(phy_description(32), level=10)
|
||||
self.submodules.trx = TRX()
|
||||
self.submodules.ctrl = CTRL()
|
||||
self.submodules.datapath = LiteSATAPHYDatapath(self.trx, self.ctrl)
|
||||
self.submodules.logger_randomizer = Randomizer(phy_description(32), level=10)
|
||||
self.submodules.logger = DataLogger()
|
||||
|
||||
self.submodules.pipeline = Pipeline(
|
||||
self.streamer,
|
||||
self.streamer_randomizer,
|
||||
self.datapath,
|
||||
self.logger_randomizer,
|
||||
self.logger
|
||||
)
|
||||
|
||||
def gen_simulation(self, selfp):
|
||||
streamer_packet = DataPacket([seed_to_data(i, False) for i in range(512)])
|
||||
yield from self.streamer.send(streamer_packet)
|
||||
yield from self.logger.receive(512)
|
||||
for d in self.logger.packet:
|
||||
r = "%08x " %d
|
||||
r +=decode_primitive(d)
|
||||
print(r)
|
||||
|
||||
# check results
|
||||
#s, l, e = check(streamer_packet, self.logger.packet)
|
||||
#print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
run_simulation(TB(), ncycles=4096, vcd_name="my.vcd", keep_files=True)
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
// Adapted from SATA specification
|
||||
/****************************************************************************/
|
||||
/* */
|
||||
/* scramble.c */
|
||||
/* */
|
||||
/* This sample code generates the entire sequence of 65535 Dwords produced */
|
||||
/* by the scrambler defined in the Serial ATA specification. The */
|
||||
/* specification calls for an LFSR to generate a string of bits that will */
|
||||
/* be packaged into 32 bit Dwords to be XORed with the data Dwords. The */
|
||||
/* generator polynomial specified is: */
|
||||
/* 16 15 13 4 */
|
||||
/* G(x) = x + x + x + x + 1 */
|
||||
/* */
|
||||
/* Parallelized versions of the scrambler are initialized to a value */
|
||||
/* derived from the initialization value of 0xFFFF defined in the */
|
||||
/* specification. This implementation is initialized to 0xF0F6. Other */
|
||||
/* parallel implementations will have different initial values. The */
|
||||
/* important point is that the first Dword output of any implementation */
|
||||
/* must equal 0xC2D2768D. */
|
||||
/* This code does not represent an elegant solution for a C implementation, */
|
||||
/* but it does demonstrate a method of generating the sequence that can be */
|
||||
/* easily implemented in hardware. A block diagram of the circuit emulated */
|
||||
/* by this code is shown below. */
|
||||
/* */
|
||||
/* +-----------------------------------+ */
|
||||
/* | | */
|
||||
/* | | */
|
||||
/* | +---+ +---+ | */
|
||||
/* | | R | | * | | */
|
||||
/* +---->| e |----------+---->| M |----+----> Output(31 downto 16) */
|
||||
/* | g | | | 1 | */
|
||||
/* +---+ | +---+ */
|
||||
/* | */
|
||||
/* | +---+ */
|
||||
/* | | * | */
|
||||
/* +---->| M |---------> Output(15 downto 0) */
|
||||
/* | 2 | */
|
||||
/* +---+ */
|
||||
/* */
|
||||
/* The register shown in the block diagram is a 16 bit register. The two */
|
||||
/* boxes, *M1 and *M2, each represent a multiply by a 16 by 16 binary */
|
||||
/* matrix. A 16 by 16 matrix times a 16 bit vector yields a 16 bit vector. */
|
||||
/* The two vectors are the two halves of the 32 bit scrambler value. The */
|
||||
/* upper half of the scrambler value is stored back into the context */
|
||||
/* register to be used to generate the next value in the scrambler */
|
||||
/* */
|
||||
/****************************************************************************/
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
int i, j;
|
||||
unsigned int length;
|
||||
unsigned short context;
|
||||
unsigned long scrambler;
|
||||
unsigned char now[16];
|
||||
unsigned char next[32];
|
||||
context = 0xF0F6;
|
||||
|
||||
scanf("0x%8x", &length);
|
||||
|
||||
for (i = 0; i < length; ++i) {
|
||||
for (j = 0; j < 16; ++j) {
|
||||
now[j] = (context >> j) & 0x01;
|
||||
}
|
||||
next[31] = now[12] ^ now[10] ^ now[7] ^ now[3] ^ now[1] ^ now[0];
|
||||
next[30] = now[15] ^ now[14] ^ now[12] ^ now[11] ^ now[9] ^ now[6] ^ now[3] ^ now[2] ^ now[0];
|
||||
next[29] = now[15] ^ now[13] ^ now[12] ^ now[11] ^ now[10] ^ now[8] ^ now[5] ^ now[3] ^ now[2] ^ now[1];
|
||||
next[28] = now[14] ^ now[12] ^ now[11] ^ now[10] ^ now[9] ^ now[7] ^ now[4] ^ now[2] ^ now[1] ^ now[0];
|
||||
next[27] = now[15] ^ now[14] ^ now[13] ^ now[12] ^ now[11] ^ now[10] ^ now[9] ^ now[8] ^ now[6] ^ now[1] ^ now[0];
|
||||
next[26] = now[15] ^ now[13] ^ now[11] ^ now[10] ^ now[9] ^ now[8] ^ now[7] ^ now[5] ^ now[3] ^ now[0];
|
||||
next[25] = now[15] ^ now[10] ^ now[9] ^ now[8] ^ now[7] ^ now[6] ^ now[4] ^ now[3] ^ now[2];
|
||||
next[24] = now[14] ^ now[9] ^ now[8] ^ now[7] ^ now[6] ^ now[5] ^ now[3] ^ now[2] ^ now[1];
|
||||
next[23] = now[13] ^ now[8] ^ now[7] ^ now[6] ^ now[5] ^ now[4] ^ now[2] ^ now[1] ^ now[0];
|
||||
next[22] = now[15] ^ now[14] ^ now[7] ^ now[6] ^ now[5] ^ now[4] ^ now[1] ^ now[0];
|
||||
next[21] = now[15] ^ now[13] ^ now[12] ^ now[6] ^ now[5] ^ now[4] ^ now[0];
|
||||
next[20] = now[15] ^ now[11] ^ now[5] ^ now[4];
|
||||
next[19] = now[14] ^ now[10] ^ now[4] ^ now[3];
|
||||
next[18] = now[13] ^ now[9] ^ now[3] ^ now[2];
|
||||
next[17] = now[12] ^ now[8] ^ now[2] ^ now[1];
|
||||
next[16] = now[11] ^ now[7] ^ now[1] ^ now[0];
|
||||
|
||||
|
||||
next[15] = now[15] ^ now[14] ^ now[12] ^ now[10] ^ now[6] ^ now[3] ^ now[0];
|
||||
next[14] = now[15] ^ now[13] ^ now[12] ^ now[11] ^ now[9] ^ now[5] ^ now[3] ^ now[2];
|
||||
next[13] = now[14] ^ now[12] ^ now[11] ^ now[10] ^ now[8] ^ now[4] ^ now[2] ^ now[1];
|
||||
next[12] = now[13] ^ now[11] ^ now[10] ^ now[9] ^ now[7] ^ now[3] ^ now[1] ^ now[0];
|
||||
next[11] = now[15] ^ now[14] ^ now[10] ^ now[9] ^ now[8] ^ now[6] ^ now[3] ^ now[2] ^ now[0];
|
||||
next[10] = now[15] ^ now[13] ^ now[12] ^ now[9] ^ now[8] ^ now[7] ^ now[5] ^ now[3] ^ now[2] ^ now[1];
|
||||
next[9] = now[14] ^ now[12] ^ now[11] ^ now[8] ^ now[7] ^ now[6] ^ now[4] ^ now[2] ^ now[1] ^ now[0];
|
||||
next[8] = now[15] ^ now[14] ^ now[13] ^ now[12] ^ now[11] ^ now[10] ^ now[7] ^ now[6] ^ now[5] ^ now[1] ^ now[0];
|
||||
next[7] = now[15] ^ now[13] ^ now[11] ^ now[10] ^ now[9] ^ now[6] ^ now[5] ^ now[4] ^ now[3] ^ now[0];
|
||||
next[6] = now[15] ^ now[10] ^ now[9] ^ now[8] ^ now[5] ^ now[4] ^ now[2];
|
||||
next[5] = now[14] ^ now[9] ^ now[8] ^ now[7] ^ now[4] ^ now[3] ^ now[1];
|
||||
next[4] = now[13] ^ now[8] ^ now[7] ^ now[6] ^ now[3] ^ now[2] ^ now[0];
|
||||
next[3] = now[15] ^ now[14] ^ now[7] ^ now[6] ^ now[5] ^ now[3] ^ now[2] ^ now[1];
|
||||
next[2] = now[14] ^ now[13] ^ now[6] ^ now[5] ^ now[4] ^ now[2] ^ now[1] ^ now[0];
|
||||
next[1] = now[15] ^ now[14] ^ now[13] ^ now[5] ^ now[4] ^ now[1] ^ now[0];
|
||||
next[0] = now[15] ^ now[13] ^ now[4] ^ now[0];
|
||||
|
||||
scrambler = 0;
|
||||
for (j = 31; j >= 0; --j) {
|
||||
scrambler = scrambler << 1;
|
||||
scrambler |= next[j];
|
||||
}
|
||||
context = scrambler >> 16;
|
||||
printf("%08x\n", (unsigned int) scrambler);
|
||||
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
import subprocess
|
||||
|
||||
from litesata.common import *
|
||||
from litesata.core.link.scrambler import *
|
||||
|
||||
from litesata.test.common import *
|
||||
|
||||
class TB(Module):
|
||||
def __init__(self, length):
|
||||
self.submodules.scrambler = InsertReset(Scrambler())
|
||||
self.length = length
|
||||
|
||||
def get_c_values(self, length):
|
||||
stdin = "0x%08x" %length
|
||||
with subprocess.Popen("./scrambler", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
|
||||
process.stdin.write(stdin.encode("ASCII"))
|
||||
out, err = process.communicate()
|
||||
return [int(e, 16) for e in out.decode("ASCII").split("\n")[:-1]]
|
||||
|
||||
def gen_simulation(self, selfp):
|
||||
# init CRC
|
||||
selfp.scrambler.ce = 1
|
||||
selfp.scrambler.reset = 1
|
||||
yield
|
||||
selfp.scrambler.reset = 0
|
||||
|
||||
# log results
|
||||
yield
|
||||
sim_values = []
|
||||
for i in range(self.length):
|
||||
sim_values.append(selfp.scrambler.value)
|
||||
yield
|
||||
|
||||
# stop
|
||||
selfp.scrambler.ce = 0
|
||||
for i in range(32):
|
||||
yield
|
||||
|
||||
# get C code reference
|
||||
c_values = self.get_c_values(self.length)
|
||||
|
||||
# check results
|
||||
s, l, e = check(c_values, sim_values)
|
||||
print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
|
||||
|
||||
if __name__ == "__main__":
|
||||
from migen.sim.generic import run_simulation
|
||||
length = 8192
|
||||
run_simulation(TB(length), ncycles=length+100, vcd_name="my.vcd")
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
import sys, os, argparse, subprocess, struct, importlib
|
||||
|
||||
from mibuild.tools import write_to_file
|
||||
from migen.util.misc import autotype
|
||||
from migen.fhdl import verilog, edif
|
||||
from migen.fhdl.structure import _Fragment
|
||||
from migen.bank.description import CSRStatus
|
||||
from mibuild import tools
|
||||
from mibuild.xilinx_common import *
|
||||
|
||||
from litesata.common import *
|
||||
|
||||
def get_csr_csv(regions):
|
||||
r = ""
|
||||
for name, origin, busword, obj in regions:
|
||||
if not isinstance(obj, Memory):
|
||||
for csr in obj:
|
||||
nr = (csr.size + busword - 1)//busword
|
||||
r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
|
||||
origin += 4*nr
|
||||
return r
|
||||
|
||||
def _import(default, name):
|
||||
return importlib.import_module(default + "." + name)
|
||||
|
||||
def _get_args():
|
||||
parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
|
||||
description="""\
|
||||
LiteSATA - based on Migen.
|
||||
|
||||
This program builds and/or loads LiteSATA components.
|
||||
One or several actions can be specified:
|
||||
|
||||
clean delete previous build(s).
|
||||
build-rtl build verilog rtl.
|
||||
build-bitstream build-bitstream build FPGA bitstream.
|
||||
build-csr-csv save CSR map into CSV file.
|
||||
|
||||
load-bitstream load bitstream into volatile storage.
|
||||
|
||||
all clean, build-csr-csv, build-bitstream, load-bitstream.
|
||||
""")
|
||||
|
||||
parser.add_argument("-t", "--target", default="bist", help="Core type to build")
|
||||
parser.add_argument("-s", "--sub-target", default="", help="variant of the Core type to build")
|
||||
parser.add_argument("-p", "--platform", default=None, help="platform to build for")
|
||||
parser.add_argument("-Ot", "--target-option", default=[], nargs=2, action="append", help="set target-specific option")
|
||||
parser.add_argument("-Op", "--platform-option", default=[("programmer", "vivado")], nargs=2, action="append", help="set platform-specific option")
|
||||
parser.add_argument("--csr_csv", default="./test/csr.csv", help="CSV file to save the CSR map into")
|
||||
|
||||
parser.add_argument("action", nargs="+", help="specify an action")
|
||||
|
||||
return parser.parse_args()
|
||||
|
||||
# Note: misoclib need to be installed as a python library
|
||||
|
||||
if __name__ == "__main__":
|
||||
args = _get_args()
|
||||
|
||||
# create top-level Core object
|
||||
target_module = _import("targets", args.target)
|
||||
if args.sub_target:
|
||||
top_class = getattr(target_module, args.sub_target)
|
||||
else:
|
||||
top_class = target_module.default_subtarget
|
||||
|
||||
if args.platform is None:
|
||||
platform_name = top_class.default_platform
|
||||
else:
|
||||
platform_name = args.platform
|
||||
platform_module = _import("platforms", platform_name)
|
||||
platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
|
||||
platform = platform_module.Platform(**platform_kwargs)
|
||||
|
||||
build_name = top_class.__name__.lower() + "-" + platform_name
|
||||
top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
|
||||
soc = top_class(platform, **top_kwargs)
|
||||
soc.finalize()
|
||||
|
||||
# decode actions
|
||||
action_list = ["clean", "build-csr-csv", "build-core", "build-bitstream", "load-bitstream", "all"]
|
||||
actions = {k: False for k in action_list}
|
||||
for action in args.action:
|
||||
if action in actions:
|
||||
actions[action] = True
|
||||
else:
|
||||
print("Unknown action: "+action+". Valid actions are:")
|
||||
for a in action_list:
|
||||
print(" "+a)
|
||||
sys.exit(1)
|
||||
|
||||
|
||||
revision = soc.sata_phy.revision
|
||||
has_bist = hasattr(soc.sata, "bist")
|
||||
user_ports = len(soc.sata.crossbar.users)
|
||||
|
||||
print("""
|
||||
__ _ __ _______ _________
|
||||
/ / (_) /____ / __/ _ /_ __/ _ |
|
||||
/ /__/ / __/ -_)\ \/ __ |/ / / __ |
|
||||
/____/_/\__/\__/___/_/ |_/_/ /_/ |_|
|
||||
|
||||
A small footprint and configurable SATA core
|
||||
powered by Migen
|
||||
|
||||
====== Building options: ======
|
||||
{} / {} Gbps
|
||||
System Clk: {} MHz (min: {} MHz)
|
||||
User ports: {}
|
||||
BIST: {}
|
||||
===============================""".format(
|
||||
revision.replace("sata_", "SATA "), bitrates[revision],
|
||||
soc.clk_freq/1000000, frequencies[revision],
|
||||
user_ports,
|
||||
has_bist
|
||||
)
|
||||
)
|
||||
|
||||
# dependencies
|
||||
if actions["all"]:
|
||||
actions["build-csr-csv"] = True
|
||||
actions["build-bitstream"] = True
|
||||
actions["load-bitstream"] = True
|
||||
|
||||
if actions["build-bitstream"]:
|
||||
actions["build-csr-csv"] = True
|
||||
actions["build-bitstream"] = True
|
||||
actions["load-bitstream"] = True
|
||||
|
||||
if actions["clean"]:
|
||||
subprocess.call(["rm", "-rf", "build/*"])
|
||||
|
||||
if actions["build-csr-csv"]:
|
||||
csr_csv = get_csr_csv(soc.cpu_csr_regions)
|
||||
write_to_file(args.csr_csv, csr_csv)
|
||||
|
||||
if actions["build-core"]:
|
||||
ios = soc.get_ios()
|
||||
if not isinstance(soc, _Fragment):
|
||||
soc = soc.get_fragment()
|
||||
platform.finalize(soc)
|
||||
so = {
|
||||
NoRetiming: XilinxNoRetiming,
|
||||
MultiReg: XilinxMultiReg,
|
||||
AsyncResetSynchronizer: XilinxAsyncResetSynchronizer
|
||||
}
|
||||
src = verilog.convert(soc, ios, special_overrides=so)
|
||||
tools.write_to_file("build/litesata.v", src)
|
||||
|
||||
if actions["build-bitstream"]:
|
||||
vns = platform.build(soc, build_name=build_name, run=True)
|
||||
if hasattr(soc, "do_exit") and vns is not None:
|
||||
if hasattr(soc.do_exit, '__call__'):
|
||||
soc.do_exit(vns)
|
||||
|
||||
if actions["load-bitstream"]:
|
||||
prog = platform.create_programmer()
|
||||
prog.load_bitstream("build/" + build_name + platform.bitstream_ext)
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
from mibuild.generic_platform import *
|
||||
from mibuild.crg import SimpleCRG
|
||||
from mibuild.xilinx_common import CRG_DS
|
||||
from mibuild.xilinx_ise import XilinxISEPlatform
|
||||
from mibuild.xilinx_vivado import XilinxVivadoPlatform
|
||||
from mibuild.programmer import *
|
||||
|
||||
def _run_vivado(cmds):
|
||||
with subprocess.Popen("vivado -mode tcl", stdin=subprocess.PIPE, shell=True) as process:
|
||||
process.stdin.write(cmds.encode("ASCII"))
|
||||
process.communicate()
|
||||
|
||||
class VivadoProgrammer(Programmer):
|
||||
needs_bitreverse = False
|
||||
|
||||
def load_bitstream(self, bitstream_file):
|
||||
cmds = """open_hw
|
||||
connect_hw_server
|
||||
open_hw_target [lindex [get_hw_targets -of_objects [get_hw_servers localhost]] 0]
|
||||
|
||||
set_property PROBES.FILE {{}} [lindex [get_hw_devices] 0]
|
||||
set_property PROGRAM.FILE {{{bitstream}}} [lindex [get_hw_devices] 0]
|
||||
|
||||
program_hw_devices [lindex [get_hw_devices] 0]
|
||||
refresh_hw_device [lindex [get_hw_devices] 0]
|
||||
|
||||
quit
|
||||
""".format(bitstream=bitstream_file)
|
||||
_run_vivado(cmds)
|
||||
|
||||
def flash(self, address, data_file):
|
||||
raise NotImplementedError
|
||||
|
||||
_io = [
|
||||
("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),
|
||||
("user_led", 1, Pins("AA8"), IOStandard("LVCMOS15")),
|
||||
("user_led", 2, Pins("AC9"), IOStandard("LVCMOS15")),
|
||||
("user_led", 3, Pins("AB9"), IOStandard("LVCMOS15")),
|
||||
("user_led", 4, Pins("AE26"), IOStandard("LVCMOS25")),
|
||||
("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")),
|
||||
("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")),
|
||||
("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
|
||||
|
||||
("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")),
|
||||
|
||||
("clk200", 0,
|
||||
Subsignal("p", Pins("AD12"), IOStandard("LVDS")),
|
||||
Subsignal("n", Pins("AD11"), IOStandard("LVDS"))
|
||||
),
|
||||
|
||||
("clk156", 0,
|
||||
Subsignal("p", Pins("K28"), IOStandard("LVDS_25")),
|
||||
Subsignal("n", Pins("K29"), IOStandard("LVDS_25"))
|
||||
),
|
||||
|
||||
|
||||
("serial", 0,
|
||||
Subsignal("cts", Pins("L27")),
|
||||
Subsignal("rts", Pins("K23")),
|
||||
Subsignal("tx", Pins("K24")),
|
||||
Subsignal("rx", Pins("M19")),
|
||||
IOStandard("LVCMOS25")
|
||||
),
|
||||
|
||||
("sata", 0,
|
||||
Subsignal("refclk_p", Pins("C8")),
|
||||
Subsignal("refclk_n", Pins("C7")),
|
||||
Subsignal("txp", Pins("D2")),
|
||||
Subsignal("txn", Pins("D1")),
|
||||
Subsignal("rxp", Pins("E4")),
|
||||
Subsignal("rxn", Pins("E3")),
|
||||
),
|
||||
]
|
||||
|
||||
def Platform(*args, toolchain="vivado", programmer="xc3sprog", **kwargs):
|
||||
if toolchain == "ise":
|
||||
xilinx_platform = XilinxISEPlatform
|
||||
elif toolchain == "vivado":
|
||||
xilinx_platform = XilinxVivadoPlatform
|
||||
else:
|
||||
raise ValueError
|
||||
|
||||
class RealPlatform(xilinx_platform):
|
||||
bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
|
||||
|
||||
def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk200", "cpu_reset")):
|
||||
xilinx_platform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory)
|
||||
|
||||
def create_programmer(self):
|
||||
if programmer == "xc3sprog":
|
||||
return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit")
|
||||
elif programmer == "vivado":
|
||||
return VivadoProgrammer()
|
||||
else:
|
||||
raise ValueError
|
||||
|
||||
def do_finalize(self, fragment):
|
||||
try:
|
||||
self.add_period_constraint(self.lookup_request("clk156").p, 6.4)
|
||||
except ConstraintError:
|
||||
pass
|
||||
try:
|
||||
self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
|
||||
except ConstraintError:
|
||||
pass
|
||||
try:
|
||||
self.add_period_constraint(self.lookup_request("sata_host").refclk_p, 6.66)
|
||||
except ConstraintError:
|
||||
pass
|
||||
self.add_platform_command("""
|
||||
create_clock -name sys_clk -period 6 [get_nets sys_clk]
|
||||
create_clock -name sata_rx_clk -period 3.33 [get_nets sata_rx_clk]
|
||||
create_clock -name sata_tx_clk -period 3.33 [get_nets sata_tx_clk]
|
||||
|
||||
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
|
||||
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]
|
||||
set_false_path -from [get_clocks sata_rx_clk] -to [get_clocks sys_clk]
|
||||
set_false_path -from [get_clocks sata_tx_clk] -to [get_clocks sys_clk]
|
||||
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property CONFIG_VOLTAGE 2.5 [current_design]
|
||||
""")
|
||||
|
||||
return RealPlatform(*args, **kwargs)
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
from mibuild.generic_platform import *
|
||||
from mibuild.xilinx_common import CRG_DS
|
||||
from mibuild.xilinx_vivado import XilinxVivadoPlatform
|
||||
|
||||
_io = [
|
||||
("sys_clk", 0, Pins("X")),
|
||||
("sys_rst", 1, Pins("X")),
|
||||
|
||||
("sata", 0,
|
||||
Subsignal("refclk_p", Pins("C8")),
|
||||
Subsignal("refclk_n", Pins("C7")),
|
||||
Subsignal("txp", Pins("D2")),
|
||||
Subsignal("txn", Pins("D1")),
|
||||
Subsignal("rxp", Pins("E4")),
|
||||
Subsignal("rxn", Pins("E3")),
|
||||
),
|
||||
]
|
||||
|
||||
class Platform(XilinxVivadoPlatform):
|
||||
def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk200", "cpu_reset"), **kwargs):
|
||||
XilinxVivadoPlatform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory)
|
||||
|
||||
def do_finalize(self, *args, **kwargs):
|
||||
pass
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
import sys, os
|
||||
from setuptools import setup
|
||||
from setuptools import find_packages
|
||||
|
||||
here = os.path.abspath(os.path.dirname(__file__))
|
||||
README = open(os.path.join(here, "README")).read()
|
||||
|
||||
required_version = (3, 3)
|
||||
if sys.version_info < required_version:
|
||||
raise SystemExit("LiteSATA requires python {0} or greater".format(
|
||||
".".join(map(str, required_version))))
|
||||
|
||||
setup(
|
||||
name="litesata",
|
||||
version="unknown",
|
||||
description="small footprint and configurable SATA gen1/2/3 core",
|
||||
long_description=README,
|
||||
author="Florent Kermarrec",
|
||||
author_email="florent@enjoy-digital.fr",
|
||||
url="http://enjoy-digital.fr",
|
||||
download_url="https://github.com/enjoy-digital/litesata",
|
||||
packages=find_packages(here),
|
||||
license="GPL",
|
||||
platforms=["Any"],
|
||||
keywords="HDL ASIC FPGA hardware design",
|
||||
classifiers=[
|
||||
"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
|
||||
"Environment :: Console",
|
||||
"Development Status :: Alpha",
|
||||
"Intended Audience :: Developers",
|
||||
"License :: OSI Approved :: GNU General Public License (GPL)",
|
||||
"Operating System :: OS Independent",
|
||||
"Programming Language :: Python",
|
||||
],
|
||||
)
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
import subprocess
|
||||
|
||||
from migen.fhdl.std import *
|
||||
from migen.bank.description import *
|
||||
|
||||
def get_id():
|
||||
output = subprocess.check_output(["git", "rev-parse", "HEAD"]).decode("ascii")
|
||||
return int(output[:8], 16)
|
||||
|
||||
class Identifier(Module, AutoCSR):
|
||||
def __init__(self, sysid, frequency, revision=None):
|
||||
self._r_sysid = CSRStatus(16)
|
||||
self._r_revision = CSRStatus(32)
|
||||
self._r_frequency = CSRStatus(32)
|
||||
|
||||
###
|
||||
|
||||
if revision is None:
|
||||
revision = get_id()
|
||||
|
||||
self.comb += [
|
||||
self._r_sysid.status.eq(sysid),
|
||||
self._r_revision.status.eq(revision),
|
||||
self._r_frequency.status.eq(frequency),
|
||||
]
|
||||
|
||||
|
|
@ -0,0 +1,221 @@
|
|||
import os
|
||||
|
||||
from litesata.common import *
|
||||
from migen.bank import csrgen
|
||||
from migen.bus import wishbone, csr
|
||||
from migen.bus import wishbone2csr
|
||||
from migen.genlib.cdc import *
|
||||
from migen.genlib.resetsync import AsyncResetSynchronizer
|
||||
from migen.bank.description import *
|
||||
|
||||
from targets import *
|
||||
|
||||
from litescope.common import *
|
||||
from litescope.bridge.uart2wb import LiteScopeUART2WB
|
||||
from litescope.frontend.la import LiteScopeLA
|
||||
from litescope.core.port import LiteScopeTerm
|
||||
|
||||
from litesata.common import *
|
||||
from litesata.phy import LiteSATAPHY
|
||||
from litesata import LiteSATA
|
||||
|
||||
class _CRG(Module):
|
||||
def __init__(self, platform):
|
||||
self.clock_domains.cd_sys = ClockDomain()
|
||||
self.reset = Signal()
|
||||
|
||||
clk200 = platform.request("clk200")
|
||||
clk200_se = Signal()
|
||||
self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
|
||||
|
||||
pll_locked = Signal()
|
||||
pll_fb = Signal()
|
||||
pll_sys = Signal()
|
||||
self.specials += [
|
||||
Instance("PLLE2_BASE",
|
||||
p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
|
||||
|
||||
# VCO @ 1GHz
|
||||
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
|
||||
p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
|
||||
i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
|
||||
|
||||
# 166MHz
|
||||
p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
|
||||
|
||||
p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
|
||||
|
||||
p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=,
|
||||
|
||||
p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
|
||||
|
||||
p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
|
||||
),
|
||||
Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
|
||||
AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.reset),
|
||||
]
|
||||
|
||||
class GenSoC(Module):
|
||||
csr_base = 0x00000000
|
||||
csr_data_width = 32
|
||||
csr_map = {
|
||||
"bridge": 0,
|
||||
"identifier": 1,
|
||||
}
|
||||
interrupt_map = {}
|
||||
cpu_type = None
|
||||
def __init__(self, platform, clk_freq):
|
||||
self.clk_freq = clk_freq
|
||||
# UART <--> Wishbone bridge
|
||||
self.submodules.bridge = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=921600)
|
||||
|
||||
# CSR bridge 0x00000000 (shadow @0x00000000)
|
||||
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
|
||||
self._wb_masters = [self.bridge.wishbone]
|
||||
self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
|
||||
self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
|
||||
|
||||
# CSR
|
||||
self.submodules.identifier = Identifier(0, int(clk_freq))
|
||||
|
||||
def add_cpu_memory_region(self, name, origin, length):
|
||||
self.cpu_memory_regions.append((name, origin, length))
|
||||
|
||||
def add_cpu_csr_region(self, name, origin, busword, obj):
|
||||
self.cpu_csr_regions.append((name, origin, busword, obj))
|
||||
|
||||
def do_finalize(self):
|
||||
# Wishbone
|
||||
self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
|
||||
self._wb_slaves, register=True)
|
||||
|
||||
# CSR
|
||||
self.submodules.csrbankarray = csrgen.BankArray(self,
|
||||
lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
|
||||
data_width=self.csr_data_width)
|
||||
self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
|
||||
for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
|
||||
self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
|
||||
for name, memory, mapaddr, mmap in self.csrbankarray.srams:
|
||||
self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
|
||||
|
||||
class BISTLeds(Module):
|
||||
def __init__(self, platform, sata_phy):
|
||||
# 1Hz blinking leds (sata_rx and sata_tx clocks)
|
||||
sata_rx_led = platform.request("user_led", 0)
|
||||
sata_tx_led = platform.request("user_led", 1)
|
||||
|
||||
sata_rx_cnt = Signal(32)
|
||||
sata_tx_cnt = Signal(32)
|
||||
|
||||
sata_freq = int(frequencies[sata_phy.revision]*1000*1000)
|
||||
|
||||
self.sync.sata_rx += \
|
||||
If(sata_rx_cnt == 0,
|
||||
sata_rx_led.eq(~sata_rx_led),
|
||||
sata_rx_cnt.eq(sata_freq//2)
|
||||
).Else(
|
||||
sata_rx_cnt.eq(sata_rx_cnt-1)
|
||||
)
|
||||
|
||||
self.sync.sata_tx += \
|
||||
If(sata_tx_cnt == 0,
|
||||
sata_tx_led.eq(~sata_tx_led),
|
||||
sata_tx_cnt.eq(sata_freq//2)
|
||||
).Else(
|
||||
sata_tx_cnt.eq(sata_tx_cnt-1)
|
||||
)
|
||||
|
||||
# ready leds (crg and ctrl)
|
||||
self.comb += platform.request("user_led", 2).eq(sata_phy.crg.ready)
|
||||
self.comb += platform.request("user_led", 3).eq(sata_phy.ctrl.ready)
|
||||
|
||||
class BISTSoC(GenSoC, AutoCSR):
|
||||
default_platform = "kc705"
|
||||
csr_map = {
|
||||
"sata": 10,
|
||||
}
|
||||
csr_map.update(GenSoC.csr_map)
|
||||
def __init__(self, platform):
|
||||
clk_freq = 166*1000000
|
||||
GenSoC.__init__(self, platform, clk_freq)
|
||||
self.submodules.crg = _CRG(platform)
|
||||
|
||||
# SATA PHY/Core/Frontend
|
||||
self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq)
|
||||
self.comb += self.crg.reset.eq(self.sata_phy.ctrl.need_reset) # XXX FIXME
|
||||
self.submodules.sata = LiteSATA(self.sata_phy, with_bist=True, with_bist_csr=True)
|
||||
|
||||
# Status Leds
|
||||
self.submodules.leds = BISTLeds(platform, self.sata_phy)
|
||||
|
||||
class BISTSoCDevel(BISTSoC, AutoCSR):
|
||||
csr_map = {
|
||||
"la": 20
|
||||
}
|
||||
csr_map.update(BISTSoC.csr_map)
|
||||
def __init__(self, platform):
|
||||
BISTSoC.__init__(self, platform)
|
||||
|
||||
self.sata_core_link_rx_fsm_state = Signal(4)
|
||||
self.sata_core_link_tx_fsm_state = Signal(4)
|
||||
self.sata_core_transport_rx_fsm_state = Signal(4)
|
||||
self.sata_core_transport_tx_fsm_state = Signal(4)
|
||||
self.sata_core_command_rx_fsm_state = Signal(4)
|
||||
self.sata_core_command_tx_fsm_state = Signal(4)
|
||||
|
||||
debug = (
|
||||
self.sata_phy.ctrl.ready,
|
||||
|
||||
self.sata_phy.source.stb,
|
||||
self.sata_phy.source.data,
|
||||
self.sata_phy.source.charisk,
|
||||
|
||||
self.sata_phy.sink.stb,
|
||||
self.sata_phy.sink.data,
|
||||
self.sata_phy.sink.charisk,
|
||||
|
||||
self.sata.core.command.sink.stb,
|
||||
self.sata.core.command.sink.sop,
|
||||
self.sata.core.command.sink.eop,
|
||||
self.sata.core.command.sink.ack,
|
||||
self.sata.core.command.sink.write,
|
||||
self.sata.core.command.sink.read,
|
||||
self.sata.core.command.sink.identify,
|
||||
|
||||
self.sata.core.command.source.stb,
|
||||
self.sata.core.command.source.sop,
|
||||
self.sata.core.command.source.eop,
|
||||
self.sata.core.command.source.ack,
|
||||
self.sata.core.command.source.write,
|
||||
self.sata.core.command.source.read,
|
||||
self.sata.core.command.source.identify,
|
||||
self.sata.core.command.source.failed,
|
||||
self.sata.core.command.source.data,
|
||||
|
||||
self.sata_core_link_rx_fsm_state,
|
||||
self.sata_core_link_tx_fsm_state,
|
||||
self.sata_core_transport_rx_fsm_state,
|
||||
self.sata_core_transport_tx_fsm_state,
|
||||
self.sata_core_command_rx_fsm_state,
|
||||
self.sata_core_command_tx_fsm_state,
|
||||
)
|
||||
|
||||
self.submodules.la = LiteScopeLA(debug, 2048)
|
||||
self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
|
||||
|
||||
def do_finalize(self):
|
||||
BISTSoC.do_finalize(self)
|
||||
self.comb += [
|
||||
self.sata_core_link_rx_fsm_state.eq(self.sata.core.link.rx.fsm.state),
|
||||
self.sata_core_link_tx_fsm_state.eq(self.sata.core.link.tx.fsm.state),
|
||||
self.sata_core_transport_rx_fsm_state.eq(self.sata.core.transport.rx.fsm.state),
|
||||
self.sata_core_transport_tx_fsm_state.eq(self.sata.core.transport.tx.fsm.state),
|
||||
self.sata_core_command_rx_fsm_state.eq(self.sata.core.command.rx.fsm.state),
|
||||
self.sata_core_command_tx_fsm_state.eq(self.sata.core.command.tx.fsm.state)
|
||||
]
|
||||
|
||||
def do_exit(self, vns):
|
||||
self.la.export(vns, "test/la.csv")
|
||||
|
||||
default_subtarget = BISTSoC
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
from migen.genlib.resetsync import AsyncResetSynchronizer
|
||||
|
||||
from targets import *
|
||||
|
||||
from litesata.common import *
|
||||
from litesata.phy import LiteSATAPHY
|
||||
from litesata import LiteSATA
|
||||
|
||||
class LiteSATACore(Module):
|
||||
default_platform = "verilog_backend"
|
||||
def __init__(self, platform, clk_freq=166*1000000, nports=4):
|
||||
self.clk_freq = clk_freq
|
||||
|
||||
# SATA PHY/Core/Frontend
|
||||
self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq)
|
||||
self.submodules.sata = LiteSATA(self.sata_phy, with_bist=True)
|
||||
|
||||
# Get user ports from crossbar
|
||||
self.user_ports = self.sata.crossbar.get_ports(nports)
|
||||
|
||||
def get_ios(self):
|
||||
ios = set()
|
||||
|
||||
# Transceiver
|
||||
for e in dir(self.sata_phy.pads):
|
||||
obj = getattr(self.sata_phy.pads, e)
|
||||
if isinstance(obj, Signal):
|
||||
ios = ios.union({obj})
|
||||
|
||||
# Status
|
||||
ios = ios.union({
|
||||
self.sata_phy.crg.ready,
|
||||
self.sata_phy.ctrl.ready
|
||||
})
|
||||
|
||||
# BIST
|
||||
if hasattr(self.sata, "bist"):
|
||||
for bist_unit in ["generator", "checker"]:
|
||||
for signal in ["start", "sector", "count", "random", "done", "aborted", "errors"]:
|
||||
ios = ios.union({getattr(getattr(self.sata.bist, bist_unit), signal)})
|
||||
ios = ios.union({
|
||||
self.sata.bist.identify.start,
|
||||
self.sata.bist.identify.done,
|
||||
self.sata.bist.identify.source.stb,
|
||||
self.sata.bist.identify.source.data,
|
||||
self.sata.bist.identify.source.ack
|
||||
})
|
||||
|
||||
# User ports
|
||||
def _iter_layout(layout):
|
||||
for e in layout:
|
||||
if isinstance(e[1], list):
|
||||
yield from _iter_layout(e[1])
|
||||
else:
|
||||
yield e
|
||||
|
||||
for port in self.user_ports:
|
||||
for endpoint in [port.sink, port.source]:
|
||||
for e in _iter_layout(endpoint.layout):
|
||||
obj = getattr(endpoint, e[0])
|
||||
ios = ios.union({obj})
|
||||
return ios
|
||||
|
||||
|
||||
default_subtarget = LiteSATACore
|
||||
|
|
@ -0,0 +1,198 @@
|
|||
import time
|
||||
import argparse
|
||||
import random as rand
|
||||
from collections import OrderedDict
|
||||
from config import *
|
||||
|
||||
KB = 1024
|
||||
MB = 1024*KB
|
||||
GB = 1024*MB
|
||||
|
||||
logical_sector_size = 512
|
||||
|
||||
class Timer:
|
||||
def __init__(self):
|
||||
self.value = None
|
||||
|
||||
def start(self):
|
||||
self._start = time.time()
|
||||
|
||||
def stop(self):
|
||||
self._stop = time.time()
|
||||
self.value = max(self._stop - self._start, 1/1000000)
|
||||
|
||||
class LiteSATABISTUnitDriver:
|
||||
def __init__(self, regs, name):
|
||||
self.regs = regs
|
||||
self.name = name
|
||||
self.frequency = regs.identifier_frequency.read()
|
||||
self.time = 0
|
||||
for s in ["start", "sector", "count", "loops", "random", "done", "aborted", "errors", "cycles"]:
|
||||
setattr(self, s, getattr(regs, name + "_"+ s))
|
||||
|
||||
def run(self, sector, count, loops, random, blocking=True, hw_timer=True):
|
||||
self.sector.write(sector)
|
||||
self.count.write(count)
|
||||
self.loops.write(loops)
|
||||
self.random.write(random)
|
||||
timer = Timer()
|
||||
timer.start()
|
||||
self.start.write(1)
|
||||
if blocking:
|
||||
while (self.done.read() == 0):
|
||||
pass
|
||||
timer.stop()
|
||||
aborted = self.aborted.read()
|
||||
if not aborted:
|
||||
if hw_timer:
|
||||
self.time = self.cycles.read()/self.frequency
|
||||
else:
|
||||
self.time = timer.value
|
||||
speed = (loops*count*logical_sector_size)/self.time
|
||||
errors = self.errors.read()
|
||||
else:
|
||||
speed = 0
|
||||
errors = -1
|
||||
return (aborted, errors, speed)
|
||||
|
||||
class LiteSATABISTGeneratorDriver(LiteSATABISTUnitDriver):
|
||||
def __init__(self, regs, name):
|
||||
LiteSATABISTUnitDriver.__init__(self, regs, name + "_generator")
|
||||
|
||||
class LiteSATABISTCheckerDriver(LiteSATABISTUnitDriver):
|
||||
def __init__(self, regs, name):
|
||||
LiteSATABISTUnitDriver.__init__(self, regs, name + "_checker")
|
||||
|
||||
class LiteSATABISTIdentifyDriver:
|
||||
def __init__(self, regs, name):
|
||||
self.regs = regs
|
||||
self.name = name
|
||||
for s in ["start", "done", "source_stb", "source_ack", "source_data"]:
|
||||
setattr(self, s, getattr(regs, name + "_identify_"+ s))
|
||||
self.data = []
|
||||
|
||||
def read_fifo(self):
|
||||
self.data = []
|
||||
while self.source_stb.read():
|
||||
dword = self.source_data.read()
|
||||
word_lsb = dword & 0xffff
|
||||
word_msb = (dword >> 16) & 0xffff
|
||||
self.data += [word_lsb, word_msb]
|
||||
self.source_ack.write(1)
|
||||
|
||||
def run(self, blocking=True):
|
||||
self.read_fifo() # flush the fifo before we start
|
||||
self.start.write(1)
|
||||
if blocking:
|
||||
while (self.done.read() == 0):
|
||||
pass
|
||||
self.read_fifo()
|
||||
self.decode()
|
||||
|
||||
def decode(self):
|
||||
self.serial_number = ""
|
||||
for i, word in enumerate(self.data[10:20]):
|
||||
s = word.to_bytes(2, byteorder='big').decode("utf-8")
|
||||
self.serial_number += s
|
||||
self.firmware_revision = ""
|
||||
for i, word in enumerate(self.data[23:27]):
|
||||
s = word.to_bytes(2, byteorder='big').decode("utf-8")
|
||||
self.firmware_revision += s
|
||||
self.model_number = ""
|
||||
for i, word in enumerate(self.data[27:46]):
|
||||
s = word.to_bytes(2, byteorder='big').decode("utf-8")
|
||||
self.model_number += s
|
||||
|
||||
self.total_sectors = self.data[100]
|
||||
self.total_sectors += (self.data[101] << 16)
|
||||
self.total_sectors += (self.data[102] << 32)
|
||||
self.total_sectors += (self.data[103] << 48)
|
||||
|
||||
self.capabilities = OrderedDict()
|
||||
self.capabilities["SATA Gen1"] = (self.data[76] >> 1) & 0x1
|
||||
self.capabilities["SATA Gen2"] = (self.data[76] >> 2) & 0x1
|
||||
self.capabilities["SATA Gen3"] = (self.data[76] >> 3) & 0x1
|
||||
self.capabilities["48 bits LBA supported"] = (self.data[83] >> 10) & 0x1
|
||||
|
||||
def hdd_info(self):
|
||||
info = "Serial Number: " + self.serial_number + "\n"
|
||||
info += "Firmware Revision: " + self.firmware_revision + "\n"
|
||||
info += "Model Number: " + self.model_number + "\n"
|
||||
info += "Capacity: %3.2f GB\n" %((self.total_sectors*logical_sector_size)/GB)
|
||||
for k, v in self.capabilities.items():
|
||||
info += k + ": " + str(v) + "\n"
|
||||
print(info, end="")
|
||||
|
||||
def _get_args():
|
||||
parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
|
||||
description="""\
|
||||
SATA BIST utility.
|
||||
""")
|
||||
parser.add_argument("-s", "--transfer_size", default=1024, help="transfer sizes (in KB, up to 16MB)")
|
||||
parser.add_argument("-l", "--total_length", default=256, help="total transfer length (in MB, up to HDD capacity)")
|
||||
parser.add_argument("-n", "--loops", default=1, help="number of loop per transfer (allow more precision on speed calculation for small transfers)")
|
||||
parser.add_argument("-r", "--random", action="store_true", help="use random data")
|
||||
parser.add_argument("-c", "--continuous", action="store_true", help="continuous mode (Escape to exit)")
|
||||
parser.add_argument("-i", "--identify", action="store_true", help="only run identify")
|
||||
parser.add_argument("-t", "--software_timer", action="store_true", help="use software timer")
|
||||
parser.add_argument("-a", "--random_addressing", action="store_true", help="use random addressing")
|
||||
return parser.parse_args()
|
||||
|
||||
if __name__ == "__main__":
|
||||
args = _get_args()
|
||||
wb.open()
|
||||
###
|
||||
identify = LiteSATABISTIdentifyDriver(wb.regs, "sata_bist")
|
||||
generator = LiteSATABISTGeneratorDriver(wb.regs, "sata_bist")
|
||||
checker = LiteSATABISTCheckerDriver(wb.regs, "sata_bist")
|
||||
|
||||
identify.run()
|
||||
identify.hdd_info()
|
||||
|
||||
if not int(args.identify):
|
||||
sector = 0
|
||||
count = int(args.transfer_size)*KB//logical_sector_size
|
||||
loops = int(args.loops)
|
||||
length = int(args.total_length)*MB
|
||||
random = int(args.random)
|
||||
continuous = int(args.continuous)
|
||||
sw_timer = int(args.software_timer)
|
||||
random_addressing = int(args.random_addressing)
|
||||
|
||||
run_sectors = 0
|
||||
try:
|
||||
while ((run_sectors*logical_sector_size < length) or continuous) and (sector < identify.total_sectors):
|
||||
retry = 0
|
||||
# generator (write data to HDD)
|
||||
write_done = False
|
||||
while not write_done:
|
||||
write_aborted, write_errors, write_speed = generator.run(sector, count, loops, random, True, not sw_timer)
|
||||
write_done = not write_aborted
|
||||
if not write_done:
|
||||
retry += 1
|
||||
|
||||
# checker (read and check data from HDD)
|
||||
read_done = False
|
||||
while not read_done:
|
||||
read_aborted, read_errors, read_speed = checker.run(sector, count, loops, random, True, not sw_timer)
|
||||
read_done = not read_aborted
|
||||
if not read_done:
|
||||
retry += 1
|
||||
|
||||
print("sector=%d(%dMB) wr_speed=%4.2fMB/s rd_speed=%4.2fMB/s errors=%d retry=%d" %(
|
||||
sector,
|
||||
run_sectors*logical_sector_size/MB,
|
||||
write_speed/MB,
|
||||
read_speed/MB,
|
||||
write_errors + read_errors,
|
||||
retry))
|
||||
if random_addressing:
|
||||
sector = rand.randint(0, identify.total_sectors//(256*2))*256
|
||||
else:
|
||||
sector += count
|
||||
run_sectors += count
|
||||
|
||||
except KeyboardInterrupt:
|
||||
pass
|
||||
###
|
||||
wb.close()
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
from litescope.host.driver.uart import LiteScopeUARTDriver
|
||||
|
||||
csr_csv_file = "./csr.csv"
|
||||
busword = 32
|
||||
debug_wb = False
|
||||
|
||||
com = 2
|
||||
baud = 921600
|
||||
wb = LiteScopeUARTDriver(com, baud, csr_csv_file, busword, debug_wb)
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
import sys
|
||||
from config import *
|
||||
from tools import *
|
||||
from bist import *
|
||||
from litescope.host.driver.la import LiteScopeLADriver
|
||||
|
||||
la = LiteScopeLADriver(wb.regs, "la")
|
||||
identify = LiteSATABISTIdentifyDriver(wb.regs, "sata_bist")
|
||||
generator = LiteSATABISTGeneratorDriver(wb.regs, "sata_bist")
|
||||
checker = LiteSATABISTCheckerDriver(wb.regs, "sata_bist")
|
||||
wb.open()
|
||||
regs = wb.regs
|
||||
###
|
||||
|
||||
trig = "now"
|
||||
if len(sys.argv) < 2:
|
||||
print("No trigger condition, triggering immediately!")
|
||||
else:
|
||||
trig = sys.argv[1]
|
||||
|
||||
conditions = {}
|
||||
conditions["now"] = {}
|
||||
conditions["id_cmd"] = {
|
||||
"sata_command_tx_sink_stb" : 1,
|
||||
"sata_command_tx_sink_payload_identify" : 1,
|
||||
}
|
||||
conditions["id_resp"] = {
|
||||
"source_source_payload_data" : primitives["X_RDY"],
|
||||
}
|
||||
conditions["wr_cmd"] = {
|
||||
"sata_command_tx_sink_stb" : 1,
|
||||
"sata_command_tx_sink_payload_write" : 1,
|
||||
}
|
||||
conditions["wr_resp"] = {
|
||||
"sata_command_rx_source_stb" : 1,
|
||||
"sata_command_rx_source_payload_write" : 1,
|
||||
}
|
||||
conditions["rd_cmd"] = {
|
||||
"sata_command_tx_sink_stb" : 1,
|
||||
"sata_command_tx_sink_payload_read" : 1,
|
||||
}
|
||||
conditions["rd_resp"] = {
|
||||
"sata_command_rx_source_stb" : 1,
|
||||
"sata_command_rx_source_payload_read" : 1,
|
||||
}
|
||||
|
||||
la.configure_term(port=0, cond=conditions[trig])
|
||||
la.configure_sum("term")
|
||||
|
||||
# Run Logic Analyzer
|
||||
la.run(offset=64, length=1024)
|
||||
|
||||
#identify.run(blocking=False)
|
||||
generator.run(0, 2, 1, 0, blocking=False)
|
||||
#checker.run(0, 2, 1, 0, blocking=False)
|
||||
|
||||
while not la.done():
|
||||
pass
|
||||
|
||||
la.upload()
|
||||
la.save("dump.vcd")
|
||||
###
|
||||
wb.close()
|
||||
|
||||
f = open("dump_link.txt", "w")
|
||||
data = link_trace(la,
|
||||
tx_data_name="sink_sink_payload_data",
|
||||
rx_data_name="source_source_payload_data"
|
||||
)
|
||||
f.write(data)
|
||||
f.close()
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
from config import *
|
||||
|
||||
wb.open()
|
||||
regs = wb.regs
|
||||
###
|
||||
print("sysid : 0x%04x" %regs.identifier_sysid.read())
|
||||
print("revision : 0x%04x" %regs.identifier_revision.read())
|
||||
print("frequency : %d MHz" %(regs.identifier_frequency.read()/1000000))
|
||||
###
|
||||
wb.close()
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
from litescope.host.dump import *
|
||||
|
||||
primitives = {
|
||||
"ALIGN" : 0x7B4A4ABC,
|
||||
"CONT" : 0X9999AA7C,
|
||||
"SYNC" : 0xB5B5957C,
|
||||
"R_RDY" : 0x4A4A957C,
|
||||
"R_OK" : 0x3535B57C,
|
||||
"R_ERR" : 0x5656B57C,
|
||||
"R_IP" : 0X5555B57C,
|
||||
"X_RDY" : 0x5757B57C,
|
||||
"CONT" : 0x9999AA7C,
|
||||
"WTRM" : 0x5858B57C,
|
||||
"SOF" : 0x3737B57C,
|
||||
"EOF" : 0xD5D5B57C,
|
||||
"HOLD" : 0xD5D5AA7C,
|
||||
"HOLDA" : 0X9595AA7C
|
||||
}
|
||||
|
||||
def decode_primitive(dword):
|
||||
for k, v in primitives.items():
|
||||
if dword == v:
|
||||
return k
|
||||
return ""
|
||||
|
||||
def link_trace(mila, tx_data_name, rx_data_name):
|
||||
r = ""
|
||||
dump = Dump()
|
||||
dump.add_from_layout(mila.layout, mila.dat)
|
||||
|
||||
for var in dump.vars:
|
||||
if var.name == tx_data_name:
|
||||
tx_data = var.values
|
||||
if var.name == rx_data_name:
|
||||
rx_data = var.values
|
||||
|
||||
for i in range(len(tx_data)):
|
||||
tx = "%08x " %tx_data[i]
|
||||
tx += decode_primitive(tx_data[i])
|
||||
tx += " "*(16-len(tx))
|
||||
|
||||
rx = "%08x " %rx_data[i]
|
||||
rx += decode_primitive(rx_data[i])
|
||||
rx += " "*(16-len(rx))
|
||||
|
||||
r += tx + rx + "\n"
|
||||
|
||||
return r
|
||||
Loading…
Reference in New Issue