Merge pull request #620 from antmicro/add_litex_json2dts
Add Linux DT generation script
This commit is contained in:
enjoy-digital
GitHub
commit
b64209b38b
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@ -0,0 +1,521 @@
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#!/usr/bin/env python3
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import sys
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import json
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import argparse
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def generate_dts(d):
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kB = 1024
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mB = kB*1024
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aliases = {}
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# Header -------------------------------------------------------------------------------------------
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dts = """
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "enjoy-digital,litex-vexriscv-soclinux";
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model = "VexRiscv SoCLinux";
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"""
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# Boot Arguments -----------------------------------------------------------------------------------
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dts += """
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chosen {{
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bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi root=/dev/ram0 init=/sbin/init swiotlb=32";
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linux,initrd-start = <0x{linux_initrd_start:x}>;
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linux,initrd-end = <0x{linux_initrd_end:x}>;
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}};
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""".format(main_ram_base=d["memories"]["main_ram"]["base"],
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main_ram_size=d["memories"]["main_ram"]["size"],
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main_ram_size_mb=d["memories"]["main_ram"]["size"] // mB,
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linux_initrd_start=d["memories"]["main_ram"]["base"] + 8*mB,
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linux_initrd_end=d["memories"]["main_ram"]["base"] + 16*mB)
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# CPU ----------------------------------------------------------------------------------------------
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dts += """
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cpus {{
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <{sys_clk_freq}>;
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cpu@0 {{
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clock-frequency = <0x0>;
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compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
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d-cache-block-size = <0x40>;
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d-cache-sets = <0x40>;
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d-cache-size = <0x8000>;
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d-tlb-sets = <0x1>;
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d-tlb-size = <0x20>;
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device_type = "cpu";
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i-cache-block-size = <0x40>;
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i-cache-sets = <0x40>;
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i-cache-size = <0x8000>;
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i-tlb-sets = <0x1>;
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i-tlb-size = <0x20>;
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mmu-type = "riscv,sv32";
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reg = <0x0>;
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riscv,isa = "rv32ima";
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sifive,itim = <0x1>;
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status = "okay";
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tlb-split;
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}};
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}};
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""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
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# Memory -------------------------------------------------------------------------------------------
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dts += """
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memory@{main_ram_base:x} {{
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device_type = "memory";
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reg = <0x{main_ram_base:x} 0x{main_ram_size:x}>;
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}};
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""".format(main_ram_base=d["memories"]["main_ram"]["base"],
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main_ram_size=d["memories"]["main_ram"]["size"])
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if "emulator" in d["memories"]:
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dts += """
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reserved-memory {{
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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vexriscv_emulator@{emulator_base:x} {{
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reg = <0x{emulator_base:x} 0x{emulator_size:x}>;
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}};
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}};
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""".format(emulator_base=d["memories"]["emulator"]["base"],
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emulator_size=d["memories"]["emulator"]["size"])
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# SoC ----------------------------------------------------------------------------------------------
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dts += """
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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"""
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# Interrupt controller -----------------------------------------------------------------------------
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dts += """
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intc0: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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compatible = "vexriscv,intc0";
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status = "okay";
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};
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"""
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# SoC Controller -----------------------------------------------------------------------------------
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dts += """
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soc_ctrl0: soc_controller@{soc_ctrl_csr_base:x} {{
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compatible = "litex,soc_controller";
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reg = <0x{soc_ctrl_csr_base:x} 0xc>;
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status = "okay";
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}};
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""".format(soc_ctrl_csr_base=d["csr_bases"]["ctrl"])
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# UART ---------------------------------------------------------------------------------------------
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if "uart" in d["csr_bases"]:
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aliases["serial0"] = "liteuart0"
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dts += """
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liteuart0: serial@{uart_csr_base:x} {{
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device_type = "serial";
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compatible = "litex,liteuart";
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reg = <0x{uart_csr_base:x} 0x100>;
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status = "okay";
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}};
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""".format(uart_csr_base=d["csr_bases"]["uart"])
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# Ethernet MAC -------------------------------------------------------------------------------------
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if "ethphy" in d["csr_bases"] and "ethmac" in d["csr_bases"]:
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dts += """
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mac0: mac@{ethmac_csr_base:x} {{
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compatible = "litex,liteeth";
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reg = <0x{ethmac_csr_base:x} 0x7c
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0x{ethphy_csr_base:x} 0x0a
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0x{ethmac_mem_base:x} 0x2000>;
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tx-fifo-depth = <{ethmac_tx_slots}>;
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rx-fifo-depth = <{ethmac_rx_slots}>;
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}};
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""".format(ethphy_csr_base=d["csr_bases"]["ethphy"],
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ethmac_csr_base=d["csr_bases"]["ethmac"],
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ethmac_mem_base=d["memories"]["ethmac"]["base"],
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ethmac_tx_slots=d["constants"]["ethmac_tx_slots"],
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ethmac_rx_slots=d["constants"]["ethmac_rx_slots"])
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# Leds ---------------------------------------------------------------------------------------------
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if "leds" in d["csr_bases"]:
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dts += """
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leds: gpio@{leds_csr_base:x} {{
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compatible = "litex,gpio";
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reg = <0x{leds_csr_base:x} 0x4>;
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litex,direction = "out";
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status = "disabled";
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}};
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""".format(leds_csr_base=d["csr_bases"]["leds"])
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# RGB Led ------------------------------------------------------------------------------------------
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for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
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if name in d["csr_bases"]:
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dts += """
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{pwm_name}: pwm@{pwm_csr_base:x} {{
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compatible = "litex,pwm";
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reg = <0x{pwm_csr_base:x} 0x24>;
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clock = <100000000>;
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#pwm-cells = <3>;
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status = "okay";
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}};
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""".format(pwm_name=name,
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pwm_csr_base=d["csr_bases"][name])
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# Switches -----------------------------------------------------------------------------------------
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if "switches" in d["csr_bases"]:
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dts += """
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switches: gpio@{switches_csr_base:x} {{
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compatible = "litex,gpio";
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reg = <0x{switches_csr_base:x} 0x4>;
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litex,direction = "in";
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status = "disabled";
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}};
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""".format(switches_csr_base=d["csr_bases"]["switches"])
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# SPI ----------------------------------------------------------------------------------------------
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if "spi" in d["csr_bases"]:
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aliases["spi0"] = "litespi0"
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dts += """
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litespi0: spi@{spi_csr_base:x} {{
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compatible = "litex,litespi";
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reg = <0x{spi_csr_base:x} 0x100>;
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status = "okay";
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litespi,max-bpw = <8>;
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litespi,sck-frequency = <1000000>;
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litespi,num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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spidev0: spidev@0 {{
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compatible = "linux,spidev";
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reg = <0>;
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spi-max-frequency = <1000000>;
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status = "okay";
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}};
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}};
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""".format(spi_csr_base=d["csr_bases"]["spi"])
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# SPIFLASH -------------------------------------------------------------------------------------------
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if "spiflash" in d["csr_bases"]:
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aliases["spiflash"] = "litespiflash"
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dts += """
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litespiflash: spiflash@{spiflash_csr_base:x} {{
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "litex,spiflash";
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reg = <0x{spiflash_csr_base:x} 0x100>;
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flash: flash@0 {{
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compatible = "jedec,spi-nor";
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reg = <0x0 0x{spiflash_size:x}>;
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}};
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}};
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""".format(spiflash_csr_base=d["csr_bases"]["spiflash"],
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spiflash_size=d["memories"]["spiflash"]["size"])
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# SPISDCARD ----------------------------------------------------------------------------------------
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if "spisdcard" in d["csr_bases"]:
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aliases["sdcard0"] = "litespisdcard0"
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dts += """
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litespisdcard0: spi@{spisdcard_csr_base:x} {{
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compatible = "litex,litespi";
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reg = <0x{spisdcard_csr_base:x} 0x100>;
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status = "okay";
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litespi,max-bpw = <8>;
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litespi,sck-frequency = <1500000>;
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litespi,num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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mmc-slot@0 {{
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compatible = "mmc-spi-slot";
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reg = <0>;
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voltage-ranges = <3300 3300>;
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spi-max-frequency = <1500000>;
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status = "okay";
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}};
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}};
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""".format(spisdcard_csr_base=d["csr_bases"]["spisdcard"])
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# I2C ----------------------------------------------------------------------------------------------
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if "i2c0" in d["csr_bases"]:
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dts += """
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i2c0: i2c@{i2c0_csr_base:x} {{
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compatible = "litex,i2c";
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reg = <0x{i2c0_csr_base:x} 0x5>;
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status = "okay";
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}};
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""".format(i2c0_csr_base=d["csr_bases"]["i2c0"])
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# XADC ---------------------------------------------------------------------------------------------
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if "xadc" in d["csr_bases"]:
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dts += """
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hwmon0: xadc@{xadc_csr_base:x} {{
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compatible = "litex,hwmon-xadc";
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reg = <0x{xadc_csr_base:x} 0x20>;
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status = "okay";
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}};
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""".format(xadc_csr_base=d["csr_bases"]["xadc"])
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# Framebuffer --------------------------------------------------------------------------------------
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if "framebuffer" in d["csr_bases"]:
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# FIXME: dynamic framebuffer base and size
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framebuffer_base = 0xc8000000
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framebuffer_width = d["constants"]["litevideo_h_active"]
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framebuffer_height = d["constants"]["litevideo_v_active"]
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dts += """
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framebuffer0: framebuffer@f0000000 {{
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compatible = "simple-framebuffer";
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reg = <0x{framebuffer_base:x} 0x{framebuffer_size:x}>;
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width = <{framebuffer_width}>;
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height = <{framebuffer_height}>;
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stride = <{framebuffer_stride}>;
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format = "a8b8g8r8";
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}};
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""".format(framebuffer_base=framebuffer_base,
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framebuffer_width=framebuffer_width,
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framebuffer_height=framebuffer_height,
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framebuffer_size=framebuffer_width * framebuffer_height * 4,
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framebuffer_stride=framebuffer_width * 4)
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dts += """
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litevideo0: gpu@{litevideo_base:x} {{
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compatible = "litex,litevideo";
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reg = <0x{litevideo_base:x} 0x100>;
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litevideo,pixel-clock = <{litevideo_pixel_clock}>;
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litevideo,h-active = <{litevideo_h_active}>;
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litevideo,h-blanking = <{litevideo_h_blanking}>;
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litevideo,h-sync = <{litevideo_h_sync}>;
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litevideo,h-front-porch = <{litevideo_h_front_porch}>;
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litevideo,v-active = <{litevideo_v_active}>;
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litevideo,v-blanking = <{litevideo_v_blanking}>;
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litevideo,v-sync = <{litevideo_v_sync}>;
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litevideo,v-front-porch = <{litevideo_v_front_porch}>;
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litevideo,dma-offset = <0x{litevideo_dma_offset:x}>;
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litevideo,dma-length = <0x{litevideo_dma_length:x}>;
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}};
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""".format(litevideo_base=d["csr_bases"]["framebuffer"],
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litevideo_pixel_clock=int(d["constants"]["litevideo_pix_clk"] / 1e3),
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litevideo_h_active=d["constants"]["litevideo_h_active"],
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litevideo_h_blanking=d["constants"]["litevideo_h_blanking"],
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litevideo_h_sync=d["constants"]["litevideo_h_sync"],
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litevideo_h_front_porch=d["constants"]["litevideo_h_front_porch"],
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litevideo_v_active=d["constants"]["litevideo_v_active"],
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litevideo_v_blanking=d["constants"]["litevideo_v_blanking"],
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litevideo_v_sync=d["constants"]["litevideo_v_sync"],
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litevideo_v_front_porch=d["constants"]["litevideo_v_front_porch"],
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litevideo_dma_offset=framebuffer_base - d["memories"]["main_ram"]["base"],
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litevideo_dma_length=framebuffer_width * framebuffer_height * 4)
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# ICAPBitstream ------------------------------------------------------------------------------------
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if "icap_bit" in d["csr_bases"]:
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dts += """
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fpga0: icap@{icap_csr_base:x} {{
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compatible = "litex,fpga-icap";
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reg = <0x{icap_csr_base:x} 0x14>;
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status = "okay";
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}};
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""".format(icap_csr_base=d["csr_bases"]["icap_bit"])
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# CLK ----------------------------------------------------------------------------------------------
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def add_clkout(clkout_nr, clk_f, clk_p, clk_dn, clk_dd, clk_margin, clk_margin_exp):
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return """
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CLKOUT{clkout_nr}: CLKOUT{clkout_nr} {{
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compatible = "litex,clk";
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#clock-cells = <0>;
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clock-output-names = "CLKOUT{clkout_nr}";
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reg = <{clkout_nr}>;
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litex,clock-frequency = <{clk_f}>;
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litex,clock-phase = <{clk_p}>;
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litex,clock-duty-num = <{clk_dn}>;
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litex,clock-duty-den = <{clk_dd}>;
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litex,clock-margin = <{clk_margin}>;
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litex,clock-margin-exp = <{clk_margin_exp}>;
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}};
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""".format(clkout_nr=clkout_nr,
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clk_f=clk_f,
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clk_p=clk_p,
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clk_dn=clk_dn,
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clk_dd=clk_dd,
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clk_margin=clk_margin,
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clk_margin_exp=clk_margin_exp)
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if "mmcm" in d["csr_bases"]:
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nclkout = d["constants"]["nclkout"]
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dts += """
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clk0: clk@{mmcm_csr_base:x} {{
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compatible = "litex,clk";
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reg = <0x{mmcm_csr_base:x} 0x100>;
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#clock-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-output-names =
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""".format(mmcm_csr_base=d["csr_bases"]["mmcm"])
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for clkout_nr in range(nclkout - 1):
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dts += """
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"CLKOUT{clkout_nr}",
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""".format(clkout_nr=clkout_nr)
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dts += """
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"CLKOUT{nclkout}";
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""".format(nclkout=(nclkout - 1))
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dts += """
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litex,lock-timeout = <{mmcm_lock_timeout}>;
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litex,drdy-timeout = <{mmcm_drdy_timeout}>;
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litex,sys-clock-frequency = <{sys_clk}>;
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litex,divclk-divide-min = <{divclk_divide_range[0]}>;
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litex,divclk-divide-max = <{divclk_divide_range[1]}>;
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litex,clkfbout-mult-min = <{clkfbout_mult_frange[0]}>;
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litex,clkfbout-mult-max = <{clkfbout_mult_frange[1]}>;
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litex,vco-freq-min = <{vco_freq_range[0]}>;
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litex,vco-freq-max = <{vco_freq_range[1]}>;
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litex,clkout-divide-min = <{clkout_divide_range[0]}>;
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litex,clkout-divide-max = <{clkout_divide_range[1]}>;
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litex,vco-margin = <{vco_margin}>;
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""".format(mmcm_lock_timeout=d["constants"]["mmcm_lock_timeout"],
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mmcm_drdy_timeout=d["constants"]["mmcm_drdy_timeout"],
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sys_clk=d["constants"]["config_clock_frequency"],
|
||||
divclk_divide_range=(d["constants"]["divclk_divide_range_min"], d["constants"]["divclk_divide_range_max"]),
|
||||
clkfbout_mult_frange=(d["constants"]["clkfbout_mult_frange_min"], d["constants"]["clkfbout_mult_frange_max"]),
|
||||
vco_freq_range=(d["constants"]["vco_freq_range_min"], d["constants"]["vco_freq_range_max"]),
|
||||
clkout_divide_range=(d["constants"]["clkout_divide_range_min"], d["constants"]["clkout_divide_range_max"]),
|
||||
vco_margin=d["constants"]["vco_margin"])
|
||||
|
||||
for clkout_nr in range(nclkout):
|
||||
dts += add_clkout(clkout_nr,
|
||||
d["constants"]["clkout_def_freq"],
|
||||
d["constants"]["clkout_def_phase"],
|
||||
d["constants"]["clkout_def_duty_num"],
|
||||
d["constants"]["clkout_def_duty_den"],
|
||||
d["constants"]["clkout_margin"],
|
||||
d["constants"]["clkout_margin_exp"])
|
||||
|
||||
dts += """
|
||||
};"""
|
||||
|
||||
# SDCARD -------------------------------------------------------------------------------------------
|
||||
|
||||
if "sdcore" in d["csr_bases"]:
|
||||
|
||||
dts += """
|
||||
mmc0: mmc@{mmc_csr_base:x} {{
|
||||
compatible = "litex,mmc";
|
||||
bus-width = <4>;
|
||||
reg = <
|
||||
0x{sdphy_csr_base:x} 0x100
|
||||
0x{sdcore_csr_base:x} 0x100
|
||||
>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(mmc_csr_base=d["csr_bases"]["sdcore"],
|
||||
sdphy_csr_base=d["csr_bases"]["sdphy"],
|
||||
sdcore_csr_base=d["csr_bases"]["sdcore"])
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# Aliases ------------------------------------------------------------------------------------------
|
||||
|
||||
if aliases:
|
||||
dts += """
|
||||
aliases {
|
||||
"""
|
||||
for alias in aliases:
|
||||
|
||||
dts += """
|
||||
{} = &{};
|
||||
""".format(alias, aliases[alias])
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# Leds & switches ----------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
&leds {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
&switches {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
return dts
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
|
||||
parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
|
||||
parser.add_argument("csr_json", help="CSR JSON file")
|
||||
args = parser.parse_args()
|
||||
|
||||
d = json.load(open(args.csr_json))
|
||||
|
||||
print(generate_dts(d))
|
||||
Loading…
Reference in New Issue