LM32: make IP read-only and interrupt lines level-sensitive
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@ -93,7 +93,7 @@ parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts
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input clk_i; // Clock
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input clk_i; // Clock
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input rst_i; // Reset
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input rst_i; // Reset
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input [interrupts-1:0] interrupt; // Interrupt pins, active-low
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input [interrupts-1:0] interrupt; // Interrupt pins
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input stall_x; // Stall X pipeline stage
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input stall_x; // Stall X pipeline stage
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@ -126,8 +126,6 @@ reg [`LM32_WORD_RNG] csr_read_data;
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// Internal nets and registers
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// Internal nets and registers
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/////////////////////////////////////////////////////
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/////////////////////////////////////////////////////
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wire [interrupts-1:0] asserted; // Which interrupts are currently being asserted
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//pragma attribute asserted preserve_signal true
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wire [interrupts-1:0] interrupt_n_exception;
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wire [interrupts-1:0] interrupt_n_exception;
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// Interrupt CSRs
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// Interrupt CSRs
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@ -150,9 +148,6 @@ assign interrupt_n_exception = ip & im;
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// Determine if any unmasked interrupts have occured
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// Determine if any unmasked interrupts have occured
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assign interrupt_exception = (|interrupt_n_exception) & ie;
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assign interrupt_exception = (|interrupt_n_exception) & ie;
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// Determine which interrupts are currently being asserted (active-low) or are already pending
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assign asserted = ip | interrupt;
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assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
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assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
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`ifdef CFG_DEBUG_ENABLED
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`ifdef CFG_DEBUG_ENABLED
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bie,
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bie,
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@ -231,7 +226,7 @@ begin
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else
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else
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begin
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begin
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// Set IP bit when interrupt line is asserted
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// Set IP bit when interrupt line is asserted
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ip <= asserted;
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ip <= interrupt;
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`ifdef CFG_DEBUG_ENABLED
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`ifdef CFG_DEBUG_ENABLED
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if (non_debug_exception == `TRUE)
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if (non_debug_exception == `TRUE)
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begin
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begin
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@ -276,8 +271,6 @@ begin
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end
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end
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if (csr == `LM32_CSR_IM)
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if (csr == `LM32_CSR_IM)
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im <= csr_write_data[interrupts-1:0];
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im <= csr_write_data[interrupts-1:0];
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if (csr == `LM32_CSR_IP)
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ip <= asserted & ~csr_write_data[interrupts-1:0];
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end
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end
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end
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end
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end
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end
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@ -300,7 +293,7 @@ begin
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else
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else
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begin
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begin
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// Set IP bit when interrupt line is asserted
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// Set IP bit when interrupt line is asserted
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ip <= asserted;
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ip <= interrupt;
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`ifdef CFG_DEBUG_ENABLED
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`ifdef CFG_DEBUG_ENABLED
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if (non_debug_exception == `TRUE)
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if (non_debug_exception == `TRUE)
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begin
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begin
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@ -343,8 +336,6 @@ begin
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bie <= csr_write_data[2];
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bie <= csr_write_data[2];
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`endif
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`endif
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end
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end
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if (csr == `LM32_CSR_IP)
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ip <= asserted & ~csr_write_data[interrupts-1:0];
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end
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end
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end
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end
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end
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end
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