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fhdl/verilog: Move inline verilog attribute to previous line to improve readability of the generated verilog.

This commit is contained in:
Florent Kermarrec 2022-10-21 19:19:28 +02:00
parent 096f2184e6
commit b6e672a060
1 changed files with 9 additions and 14 deletions
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23
litex/gen/fhdl/verilog.py
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@ -340,25 +340,24 @@ def _print_node(ns, at, level, node, target_filter=None):
def _print_attribute(attr, attr_translate): def _print_attribute(attr, attr_translate):
r = "" r = ""
firsta = True first = True
for attr in sorted(attr, for attr in sorted(attr, key=lambda x: ("", x) if isinstance(x, str) else x):
key=lambda x: ("", x) if isinstance(x, str) else x):
if isinstance(attr, tuple): if isinstance(attr, tuple):
# platform-dependent attribute # Platform-dependent attribute.
attr_name, attr_value = attr attr_name, attr_value = attr
else: else:
# translated attribute # Translated attribute.
at = attr_translate.get(attr, None) at = attr_translate.get(attr, None)
if at is None: if at is None:
continue continue
attr_name, attr_value = at attr_name, attr_value = at
if not firsta: if not first:
r += ", " r += ", "
firsta = False first = False
const_expr = "\"" + attr_value + "\"" if not isinstance(attr_value, int) else str(attr_value) const_expr = "\"" + attr_value + "\"" if not isinstance(attr_value, int) else str(attr_value)
r += attr_name + " = " + const_expr r += attr_name + " = " + const_expr
if r: if r:
r = "(* " + r + " *)" r = "(* " + r + " *)\n"
return r return r
# ------------------------------------------------------------------------------------------------ # # ------------------------------------------------------------------------------------------------ #
@ -418,9 +417,7 @@ def _print_signals(f, ios, name, ns, attr_translate):
r = "" r = ""
for sig in sorted(sigs - ios, key=lambda x: x.duid): for sig in sorted(sigs - ios, key=lambda x: x.duid):
attr = _print_attribute(sig.attr, attr_translate) r += _print_attribute(sig.attr, attr_translate)
if attr:
r += attr + " "
if sig in wires: if sig in wires:
r += "wire " + _print_signal(ns, sig) + ";\n" r += "wire " + _print_signal(ns, sig) + ";\n"
else: else:
@ -494,9 +491,7 @@ def _print_specials(name, overrides, specials, namespace, add_data_file, attr_tr
r = "" r = ""
for special in sorted(specials, key=lambda x: x.duid): for special in sorted(specials, key=lambda x: x.duid):
if hasattr(special, "attr"): if hasattr(special, "attr"):
attr = _print_attribute(special.attr, attr_translate) r += _print_attribute(special.attr, attr_translate)
if attr:
r += attr + " "
# Replace Migen Memory's emit_verilog with LiteX's implementation. # Replace Migen Memory's emit_verilog with LiteX's implementation.
if isinstance(special, Memory): if isinstance(special, Memory):
from litex.gen.fhdl.memory import memory_emit_verilog from litex.gen.fhdl.memory import memory_emit_verilog