Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

misoclib/com/uart: replace revered Migen FIFO function with specific _get_uart_fifo function for our use case.

This commit is contained in:
Florent Kermarrec 2015-07-24 13:57:57 +02:00
parent 0a115f609e
commit b75b93df43
1 changed files with 11 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
misoclib/com/uart/__init__.py
View File

@ -2,7 +2,15 @@ from migen.fhdl.std import *
from migen.bank.description import * from migen.bank.description import *
from migen.bank.eventmanager import * from migen.bank.eventmanager import *
from migen.genlib.record import Record from migen.genlib.record import Record
from migen.actorlib.fifo import FIFO from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
def _get_uart_fifo(depth, sink_cd="sys", source_cd="sys"):
if sink_cd != source_cd:
fifo = AsyncFIFO([("data", 8)], depth)
return ClockDomainsRenamer({"write": sink_cd, "read": source_cd})(fifo)
else:
return SyncFIFO([("data", 8)], depth)
class UART(Module, AutoCSR): class UART(Module, AutoCSR):
@ -22,7 +30,7 @@ class UART(Module, AutoCSR):
# # # # # #
# TX # TX
tx_fifo = FIFO([("data", 8)], tx_fifo_depth, source_cd=phy_cd) tx_fifo = _get_uart_fifo(tx_fifo_depth, source_cd=phy_cd)
self.submodules += tx_fifo self.submodules += tx_fifo
tx_irqs = { tx_irqs = {
@ -40,7 +48,7 @@ class UART(Module, AutoCSR):
# RX # RX
rx_fifo = FIFO([("data", 8)], rx_fifo_depth, sink_cd=phy_cd) rx_fifo = _get_uart_fifo(rx_fifo_depth, sink_cd=phy_cd)
self.submodules += rx_fifo self.submodules += rx_fifo
rx_irqs = { rx_irqs = {