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uart2csr: add pads parameter

This commit is contained in:
Florent Kermarrec 2013-09-25 15:07:23 +02:00
parent 69009c8405
commit b766af0d99
2 changed files with 4 additions and 10 deletions
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5
examples/de0_nano/top.py
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@ -58,10 +58,7 @@ class SoC(Module):
self.submodules.mila = MiLa(mila_width, mila_depth, [term], rle=True) self.submodules.mila = MiLa(mila_width, mila_depth, [term], rle=True)
# Uart2Csr # Uart2Csr
self.submodules.uart2csr = uart2csr.Uart2Csr(clk_freq, 115200) self.submodules.uart2csr = uart2csr.Uart2Csr(platform.request("serial"), clk_freq, 115200)
uart_pads = platform.request("serial")
self.comb += uart_pads.tx.eq(self.uart2csr.tx)
self.comb += self.uart2csr.rx.eq(uart_pads.rx)
# Csr Interconnect # Csr Interconnect
self.submodules.csrbankarray = csrgen.BankArray(self, self.submodules.csrbankarray = csrgen.BankArray(self,

9
miscope/com/uart2csr/__init__.py
View File

@ -10,10 +10,7 @@ READ_CMD = 0x02
CLOSE_CMD = 0x03 CLOSE_CMD = 0x03
class Uart2Csr(Module): class Uart2Csr(Module):
def __init__(self, clk_freq, baud): def __init__(self, pads, clk_freq, baud):
# Uart interface
self.rx = Signal()
self.tx = Signal()
# Csr interface # Csr interface
self.csr = csr.Interface() self.csr = csr.Interface()
@ -27,8 +24,8 @@ class Uart2Csr(Module):
# In/Out # In/Out
# #
self.comb +=[ self.comb +=[
uart.rx.eq(self.rx), uart.rx.eq(pads.rx),
self.tx.eq(uart.tx) pads.tx.eq(uart.tx)
] ]
cmd = Signal(8) cmd = Signal(8)