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Move systemverilog files to python-data

This commit is contained in:
developandplay 2021-06-26 15:38:39 +02:00
parent 16b3e08c17
commit b787ee4411
9 changed files with 4 additions and 2159 deletions
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238
litex/soc/cores/cpu/blackparrot/bp_litex/bp2wb_convertor.v
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@ -1,238 +0,0 @@
/**
* bp2wb_convertor.v
* DESCRIPTION: THIS MODULE ADAPTS BP MEMORY BUS TO 64-BIT WISHBONE
*/
module bp2wb_convertor
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_cce_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_single_core_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
// , parameter [paddr_width_p-1:0] dram_offset_p = '0
, localparam num_block_words_lp = cce_block_width_p / 64
, localparam num_block_bytes_lp = cce_block_width_p / 8
, localparam num_word_bytes_lp = dword_width_p / 8
, localparam block_offset_bits_lp = `BSG_SAFE_CLOG2(num_block_bytes_lp)
, localparam word_offset_bits_lp = `BSG_SAFE_CLOG2(num_block_words_lp)
, localparam byte_offset_bits_lp = `BSG_SAFE_CLOG2(num_word_bytes_lp)
, localparam wbone_data_width = 64
, localparam wbone_addr_ubound = paddr_width_p
, localparam mem_granularity = 64 //TODO: adapt selection bit parametrized
, localparam wbone_addr_lbound = 3 //`BSG_SAFE_CLOG2(wbone_data_width / mem_granularity) //dword granularity
, localparam total_datafetch_cycle_lp = cce_block_width_p / wbone_data_width
, localparam total_datafetch_cycle_width = `BSG_SAFE_CLOG2(total_datafetch_cycle_lp)
, localparam cached_addr_base = 32'h7000_0000//6000_0000 //32'h4000_4000//
)
( input clk_i
,(* mark_debug = "true" *) input reset_i
// BP side
,(* mark_debug = "true" *) input [cce_mem_msg_width_lp-1:0] mem_cmd_i
,(* mark_debug = "true" *) input mem_cmd_v_i
,(* mark_debug = "true" *) output mem_cmd_ready_o
, output [cce_mem_msg_width_lp-1:0] mem_resp_o
, (* mark_debug = "true" *) output mem_resp_v_o
, (* mark_debug = "true" *) input mem_resp_yumi_i
// Wishbone side
, (* mark_debug = "true" *) input [63:0] dat_i
, (* mark_debug = "true" *) output logic [63:0] dat_o
, (* mark_debug = "true" *) input ack_i
, input err_i
// , input rty_i
, (* mark_debug = "true" *) output logic [wbone_addr_ubound-wbone_addr_lbound-1:0] adr_o//TODO: Double check!!!
, (* mark_debug = "true" *) output logic stb_o
, output cyc_o
, output [7:0] sel_o //TODO: double check!!!
, (* mark_debug = "true" *) output we_o
, output [2:0] cti_o //TODO: hardwire in Litex
, output [1:0] bte_o //TODO: hardwire in Litex
, input rty_i //TODO: hardwire in Litex
);
`declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p);
//locals
(* mark_debug = "true" *) logic [total_datafetch_cycle_width:0] ack_ctr = 0;
(* mark_debug = "true" *) bp_cce_mem_msg_s mem_cmd_cast_i, mem_resp_cast_o, mem_cmd_debug, mem_cmd_debug2;
(* mark_debug = "true" *) logic ready_li, v_li, stb_justgotack;
(* mark_debug = "true" *) logic [cce_block_width_p-1:0] data_lo;
(* mark_debug = "true" *) logic [cce_block_width_p-1:0] data_li;
(* mark_debug = "true" *) wire [paddr_width_p-1:0] mem_cmd_addr_l;
(* mark_debug = "true" *) logic set_stb;
//Handshaking between Wishbone and BlackParrot through convertor
//3.1.3:At every rising edge of [CLK_I] the terminating signal(ACK) is sampled. If it
//is asserted, then [STB_O] is negated.
assign ready_li = ( ack_ctr == 0 ) & !set_stb & !mem_resp_v_o;
assign mem_cmd_ready_o = ready_li;//!stb_o then ready to take!
// assign v_li = (ack_ctr == total_datafetch_cycle_lp-1);
assign mem_resp_v_o = v_li;
assign stb_o = (set_stb) && !stb_justgotack;
assign cyc_o = stb_o;
assign sel_o = mem_cmd_r.header.size == e_mem_msg_size_4 ? ('h0F << wr_byte_shift) : 'hFF;
assign cti_o = 0;
assign bte_o = 0;
initial begin
ack_ctr = 0;
end
//Flip stb after each ack--->RULE 3.20:
// Every time we get an ACK from WB, increment counter until the counter reaches to total_datafetch_cycle_lp
always_ff @(posedge clk_i)
begin
if(reset_i)
begin
ack_ctr <= 0;
set_stb <= 0;
v_li <=0;
end
// else if (v_li)
// begin
else if (mem_resp_yumi_i)
begin
v_li <= 0;
ack_ctr <= 0;
end
// end
else if (mem_cmd_v_i)
begin
//data_li <= 0;
set_stb <= 1;
v_li <= 0;
stb_justgotack <= 0;
end
else
begin
if (ack_i)//stb should be negated after ack
begin
stb_justgotack <= 1;
data_li[(ack_ctr*wbone_data_width) +: wbone_data_width] <= dat_i;
if ((ack_ctr == total_datafetch_cycle_lp-1) || (mem_cmd_addr_l < cached_addr_base && mem_cmd_r.header.msg_type == e_cce_mem_uc_wr )) //if uncached store, just one cycle is fine
begin
v_li <=1;
set_stb <= 0;
end
else
ack_ctr <= ack_ctr + 1;
end
else
begin
stb_justgotack <= 0;
v_li <=0;
end
end
end
//Packet Pass from BP to BP2WB
assign mem_cmd_cast_i = mem_cmd_i;
bp_cce_mem_msg_s mem_cmd_r;
bsg_dff_reset_en
#(.width_p(cce_mem_msg_width_lp))
mshr_reg
(.clk_i(clk_i)
,.reset_i(reset_i)
,.en_i(mem_cmd_v_i)//when
,.data_i(mem_cmd_i)
,.data_o(mem_cmd_r)
);
//Addr && Data && Command Pass from BP2WB to WB
logic [wbone_addr_lbound-1:0] throw_away;
assign mem_cmd_addr_l = mem_cmd_r.header.addr;
assign data_lo = mem_cmd_r.data;
logic [39:0] mem_cmd_addr_l_zero64;
always_comb begin
if( mem_cmd_addr_l < cached_addr_base )
begin
adr_o = mem_cmd_addr_l[wbone_addr_ubound-1:wbone_addr_lbound];//no need to change address for uncached stores/loads
dat_o = mem_cmd_r.header.size == e_mem_msg_size_4 ? data_lo[(0*wbone_data_width) +: wbone_data_width] << rd_byte_offset*8 : data_lo[(0*wbone_data_width) +: wbone_data_width];//unchached data is stored in LS 64bits
end
else
begin
mem_cmd_addr_l_zero64 = mem_cmd_addr_l >> 6 << 6;
{adr_o,throw_away} = mem_cmd_addr_l_zero64 + (ack_ctr*8);//TODO:careful
dat_o = mem_cmd_r.header.size == e_mem_msg_size_4 ? data_lo[(ack_ctr*wbone_data_width) +: wbone_data_width] << rd_byte_offset*8 : data_lo[(ack_ctr*wbone_data_width) +: wbone_data_width];
end
end
assign we_o = (mem_cmd_r.header.msg_type inside {e_cce_mem_uc_wr, e_cce_mem_wr});
//Data Pass from BP2WB to BP
wire [cce_block_width_p-1:0] rd_word_offset = mem_cmd_r.header.addr[3+:3];
wire [cce_block_width_p-1:0] rd_byte_offset = mem_cmd_r.header.addr[0+:3];
wire [cce_block_width_p-1:0] wr_byte_shift = rd_byte_offset;
wire [cce_block_width_p-1:0] rd_bit_shift = rd_word_offset*64; // We rely on receiver to adjust bits
(* mark_debug = "true" *) wire [cce_block_width_p-1:0] data_li_resp = (mem_cmd_r.header.msg_type == e_cce_mem_uc_rd)
? data_li >> rd_bit_shift
: data_li;
assign mem_resp_cast_o = '{data : data_li_resp
,header :'{payload : mem_cmd_r.header.payload
,size : mem_cmd_r.header.size
,addr : mem_cmd_r.header.addr
,msg_type: mem_cmd_r.header.msg_type
}
};
assign mem_resp_o = mem_resp_cast_o;
/*********************************************/
/*DEBUG SECTION*/
/*wire [3:0] fake_msg_type;
wire [10:0] fake_payload;
wire [2:0] fake_size;
wire [39:0] fake_addr;
assign fake_payload = mem_cmd_r.header.payload;
assign fake_size = mem_cmd_r.header.size;
assign fake_addr = mem_cmd_r.header.addr;
assign fake_msg_type = mem_cmd_r.header.msg_type;
*/
/*(* mark_debug = "true" *) logic debug_wire;
initial begin
debug_wire = 0;
end
assign mem_cmd_debug = mem_cmd_i;
always_ff @(posedge clk_i)
debug_wire <= (ack_i && mem_cmd_debug.header.addr >= 32'h80000000);
always_ff @(posedge clk_i)
begin
if(mem_cmd_v_i && mem_cmd_debug.header.addr <= 32'h60000000)
begin
debug_wire <= 1;
// $display("addr == %x", mem_cmd_debug.header.addr);
end
/* if (mem_resp_v_o && debug_ctr < 64 && mem_cmd_debug.header.addr >= 32'h80000000)
begin
debug_gotdata[((debug_ctr-1)*512) +: 512] <= data_li_resp;
$display("data == %x", data_li_resp);
end*/
// end
wire [3:0] typean;
assign typean = mem_cmd_r.header.msg_type;
endmodule

55
litex/soc/cores/cpu/blackparrot/bp_litex/bsg_mem_1rw_sync_mask_write_bit.v
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@ -1,55 +0,0 @@
/*
* bsg_mem_1rw_sync_mask_write_bit.v
*
* distributed synchronous 1-port ram for xilinx ultrascale or ultrascale plus FPGA
* Write mode: No-change | Read mode: No-change
* Note:
* There are 2 basic BRAM library primitives, RAMB18E2 and RAMB36E2 in Vivado.
* But none of them support bit-wise mask. They have Byte-wide write enable ports though.
* So we use the RAM_STYLE attribute to instruct the tool to infer distributed LUT RAM instead.
*
* To save resources, the code is written to be inferred as Signle-port distributed ram RAM64X1S.
* https://www.xilinx.com/support/documentation/user_guides/ug574-ultrascale-clb.pdf
*
*/
module bsg_mem_1rw_sync_mask_write_bit #(
parameter width_p = "inv"
, parameter els_p = "inv"
, parameter latch_last_read_p=0
, parameter enable_clock_gating_p=0
, localparam addr_width_lp = `BSG_SAFE_CLOG2(els_p)
) (
input clk_i
, input reset_i
, input [ width_p-1:0] data_i
, input [addr_width_lp-1:0] addr_i
, input v_i
, input [ width_p-1:0] w_mask_i
, input w_i
, output [ width_p-1:0] data_o
);
wire unused = reset_i;
(* ram_style = "distributed" *) logic [width_p-1:0] mem [els_p-1:0];
logic [width_p-1:0] data_r;
always_ff @(posedge clk_i) begin
if (v_i & ~w_i)
data_r <= mem[addr_i];
end
assign data_o = data_r;
for (genvar i=0; i<width_p; i=i+1) begin
always_ff @(posedge clk_i) begin
if (v_i)
if (w_i & w_mask_i[i])
mem[addr_i][i] <= data_i[i];
end
end
endmodule

79
litex/soc/cores/cpu/blackparrot/bp_litex/cce_ucode.mem
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@ -1,79 +0,0 @@
0000000000000000000000000001000010
0000000000000000000000100010101010
0000000000000000000001100001000010
0100000100000000000000000010011001
0001111000000001111000000000001110
0000000000000000000000000110010110
0000000000000000010000000001000000
1100000001100000000000000000000001
0000000000000000100010100001010010
0000000000000000000000000001111010
0000000000000000000000000000011110
0000000000000000000000010000000101
0100001010100000000000100101010100
0011010000010001000000010010001110
0010000000000000000000000000010110
0000000101000001000000010000001101
0000000000000000000000000001001101
0100001110100011001110000011010100
0000000000010101000100010000111101
0000000000000001000000000010101110
1100000100100000000000000000000001
0100000100100000000000100001000100
0100001101000000000000000011000100
0000000000010001000001000010001110
0000000000000000000000000000010110
1100000100100000000000000000000001
0000000000010001000001100010001110
0000000000000000000000000000010110
1100000100100000000000000000000001
0100010010000001000000000001001100
0001010000010001001011000000001110
0000000000000000000000000110011110
0100001111100000000001000001000001
0100010001100000000000010001000100
0011010000010001001000100010001110
0000000000000000000000000110010110
0100010101000000000000000011000100
0100010100000000001110001001010100
0000000000000000100011100001001010
1100010101100000000000000000000001
0000000000000000010011100001001010
1100010101100000000000000000000001
0000000000000001100011100001001010
1100010110100000000010000011011100
0000000000000000000000000001000110
1100011001000010000000000001001100
0000000000010001000100010001000101
0001000000010001000010100000001110
0000000000000001000000000100101110
1100000100100000000000000000000001
0000000000010101000100010000111101
1100100011100000001100000001001100
0000000000000001000000000100101110
0100100000100000000000000011000100
0000000000000000010011100001001010
0001001000010011000001100000001110
0000000000010011001100010001000101
0001001000010011000100000000001110
0001001000010011000011000000001110
0000000000000000000000000110011110
0100011101100000000001000001000001
0100011111100000000000010001000100
0011001000010011000000100010001110
0000000000000000000000000110010110
1100000100100000000000000000000001
0000000000000000000011100001001010
0001001000010011000001100000001110
0000000000010011001100010001000101
0000000000000001100011100001001010
0001001000010011000100000000001110
1100000100100000000000000000000001
0100100101100000000000000011000100
0100100110100000000010001001010100
0000000000000001000000000010101110
1100000100100000000000000000000001
0000000000001101000000000110101110
1100000100100000000000000000000001
0000000000000011000000000110101110
1100000100100000000000000000000001

269
litex/soc/cores/cpu/blackparrot/bp_litex/flist.fpga
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@ -1,269 +0,0 @@
+incdir+$BASEJUMP_STL_DIR/bsg_dataflow
+incdir+$BASEJUMP_STL_DIR/bsg_mem
+incdir+$BASEJUMP_STL_DIR/bsg_misc
+incdir+$BASEJUMP_STL_DIR/bsg_test
+incdir+$BASEJUMP_STL_DIR/bsg_noc
+incdir+$BP_COMMON_DIR/src/include
+incdir+$BP_FE_DIR/src/include
+incdir+$BP_BE_DIR/src/include
+incdir+$BP_BE_DIR/src/include/bp_be_dcache
+incdir+$BP_ME_DIR/src/include/v
+incdir+$BP_TOP_DIR/src/include
$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_pkg.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_noc_pkg.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_pkg.v
$BP_COMMON_DIR/src/include/bp_common_rv64_pkg.vh
$BP_COMMON_DIR/src/include/bp_common_pkg.vh
$BP_COMMON_DIR/src/include/bp_common_aviary_pkg.vh
$BP_COMMON_DIR/src/include/bp_common_cfg_link_pkg.vh
$BP_FE_DIR/src/include/bp_fe_icache_pkg.vh
$BP_FE_DIR/src/include/bp_fe_pkg.vh
$BP_BE_DIR/src/include/bp_be_pkg.vh
$BP_BE_DIR/src/include/bp_be_dcache/bp_be_dcache_pkg.vh
$BP_ME_DIR/src/include/v/bp_me_pkg.vh
$BP_ME_DIR/src/include/v/bp_cce_pkg.v
$BASEJUMP_STL_DIR/bsg_async/bsg_async_fifo.v
$BASEJUMP_STL_DIR/bsg_async/bsg_launch_sync_sync.v
$BASEJUMP_STL_DIR/bsg_async/bsg_async_ptr_gray.v
$BASEJUMP_STL_DIR/bsg_cache/bsg_cache.v
$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_dma.v
$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_miss.v
$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_decode.v
$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_sbuf.v
$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_sbuf_queue.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel_in.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel_out.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_1_to_n_tagged_fifo.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_1_to_n_tagged.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_large.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_pseudo_large.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_small.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_small_unhardened.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1rw_large.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_tracker.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_flow_counter.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_one_fifo.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_parallel_in_serial_out.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_parallel_in_serial_out_dynamic.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_1_to_n.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_2_to_2.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_n_to_1.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out_dynamic.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out_full.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_shift_reg.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_two_fifo.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_cam_1r1w.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_sync.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_sync_synth.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_synth.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync.v
//$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v
$BP_LITEX_DIR/bsg_mem_1rw_sync_mask_write_bit.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_synth.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_synth.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_2r1w_sync.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_2r1w_sync_synth.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_adder_cin.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_adder_ripple_carry.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_arb_fixed.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_array_concentrate_static.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_buf.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_buf_ctrl.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_circular_ptr.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_concentrate_static.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_clear_up.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_set_down.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_set_en.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_up_down.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_up_down_variable.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_crossbar_o_by_i.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_cycle_counter.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_decode.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_decode_with_v.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_dff.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en_bypass.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset_en_bypass.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_chain.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset_en.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_edge_detect.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_encode_one_hot.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_expand_bitmask.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_hash_bank.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_hash_bank_reverse.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_idiv_iterative.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_idiv_iterative_controller.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_lfsr.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_lru_pseudo_tree_decode.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_lru_pseudo_tree_encode.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_mux.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_butterfly.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_one_hot.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_segmented.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_muxi2_gatestack.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_nor2.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_nor3.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_nand.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode_one_hot_out.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_reduce.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_reduce_segmented.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_round_robin_arb.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_scan.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_strobe.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_swap.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_thermometer_count.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_transpose.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_unconcentrate_static.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_xnor.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_mesh_stitch.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_noc_repeater_node.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator_in.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator_out.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_in.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_out.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_decoder_dor.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_input_control.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_output_control.v
$BP_COMMON_DIR/src/v/bsg_fifo_1r1w_rolly.v
$BP_COMMON_DIR/src/v/bp_pma.v
$BP_COMMON_DIR/src/v/bp_tlb.v
$BP_COMMON_DIR/src/v/bp_tlb_replacement.v
$BP_BE_DIR/src/v/bp_be_top.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_bypass.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_calculator_top.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_instr_decoder.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_int_alu.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_fp.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_int.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_ctrl.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_long.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_mem.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_mul.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_regfile.v
$BP_BE_DIR/src/v/bp_be_checker/bp_be_checker_top.v
$BP_BE_DIR/src/v/bp_be_checker/bp_be_detector.v
$BP_BE_DIR/src/v/bp_be_checker/bp_be_director.v
$BP_BE_DIR/src/v/bp_be_checker/bp_be_scheduler.v
$BP_BE_DIR/src/v/bp_be_mem/bp_be_ptw.v
$BP_BE_DIR/src/v/bp_be_mem/bp_be_csr.v
$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache.v
$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce_cmd.v
$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce.v
$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce_req.v
$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf.v
$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf_queue.v
$BP_BE_DIR/src/v/bp_be_mem/bp_be_mem_top.v
$BP_FE_DIR/src/v/bp_fe_bht.v
$BP_FE_DIR/src/v/bp_fe_btb.v
$BP_FE_DIR/src/v/bp_fe_lce_cmd.v
$BP_FE_DIR/src/v/bp_fe_icache.v
$BP_FE_DIR/src/v/bp_fe_instr_scan.v
$BP_FE_DIR/src/v/bp_fe_lce.v
$BP_FE_DIR/src/v/bp_fe_lce_req.v
$BP_FE_DIR/src/v/bp_fe_mem.v
$BP_FE_DIR/src/v/bp_fe_pc_gen.v
$BP_FE_DIR/src/v/bp_fe_top.v
$BP_ME_DIR/src/v/cache/bp_me_cache_dma_to_cce.v
$BP_ME_DIR/src/v/cache/bp_me_cache_slice.v
$BP_ME_DIR/src/v/cache/bp_me_cce_to_cache.v
$BP_ME_DIR/src/v/cce/bp_cce.v
$BP_ME_DIR/src/v/cce/bp_cce_alu.v
$BP_ME_DIR/src/v/cce/bp_cce_arbitrate.v
$BP_ME_DIR/src/v/cce/bp_cce_branch.v
$BP_ME_DIR/src/v/cce/bp_cce_buffered.v
$BP_ME_DIR/src/v/cce/bp_cce_dir.v
$BP_ME_DIR/src/v/cce/bp_cce_dir_lru_extract.v
$BP_ME_DIR/src/v/cce/bp_cce_dir_segment.v
$BP_ME_DIR/src/v/cce/bp_cce_dir_tag_checker.v
$BP_ME_DIR/src/v/cce/bp_cce_gad.v
$BP_ME_DIR/src/v/cce/bp_cce_inst_decode.v
$BP_ME_DIR/src/v/cce/bp_cce_inst_predecode.v
$BP_ME_DIR/src/v/cce/bp_cce_inst_ram.v
$BP_ME_DIR/src/v/cce/bp_cce_inst_stall.v
$BP_ME_DIR/src/v/cce/bp_cce_msg.v
$BP_ME_DIR/src/v/cce/bp_cce_pending_bits.v
$BP_ME_DIR/src/v/cce/bp_cce_reg.v
$BP_ME_DIR/src/v/cce/bp_cce_spec_bits.v
$BP_ME_DIR/src/v/cce/bp_cce_src_sel.v
$BP_ME_DIR/src/v/cce/bp_io_cce.v
$BP_ME_DIR/src/v/cce/bp_cce_fsm.v
$BP_ME_DIR/src/v/cce/bp_cce_wrapper.v
$BP_ME_DIR/src/v/cce/bp_uce.v
$BP_ME_DIR/src/v/wormhole/bp_me_addr_to_cce_id.v
$BP_ME_DIR/src/v/wormhole/bp_me_cce_id_to_cord.v
$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_bidir.v
$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_client.v
$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_master.v
$BP_ME_DIR/src/v/wormhole/bp_me_cord_to_id.v
$BP_ME_DIR/src/v/wormhole/bp_me_lce_id_to_cord.v
$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_cmd.v
$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_req.v
$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_resp.v
$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_cmd.v
$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_resp.v
$BP_TOP_DIR/src/v/bp_nd_socket.v
$BP_TOP_DIR/src/v/bp_cacc_vdp.v
$BP_TOP_DIR/src/v/bp_cacc_tile.v
$BP_TOP_DIR/src/v/bp_cacc_tile_node.v
$BP_TOP_DIR/src/v/bp_cacc_complex.v
$BP_TOP_DIR/src/v/bp_sacc_vdp.v
$BP_TOP_DIR/src/v/bp_sacc_tile.v
$BP_TOP_DIR/src/v/bp_sacc_tile_node.v
$BP_TOP_DIR/src/v/bp_sacc_complex.v
$BP_TOP_DIR/src/v/bp_cfg.v
$BP_TOP_DIR/src/v/bp_core.v
$BP_TOP_DIR/src/v/bp_core_complex.v
$BP_TOP_DIR/src/v/bp_core_minimal.v
//$BP_TOP_DIR/src/v/bp_clint.v
$BP_TOP_DIR/src/v/bp_clint_node.v
$BP_TOP_DIR/src/v/bp_clint_slice.v
$BP_TOP_DIR/src/v/bp_l2e_tile.v
$BP_TOP_DIR/src/v/bp_l2e_tile_node.v
$BP_TOP_DIR/src/v/bp_io_complex.v
$BP_TOP_DIR/src/v/bp_io_link_to_lce.v
$BP_TOP_DIR/src/v/bp_io_tile.v
$BP_TOP_DIR/src/v/bp_io_tile_node.v
$BP_TOP_DIR/src/v/bp_mem_complex.v
$BP_TOP_DIR/src/v/bp_processor.v
$BP_TOP_DIR/src/v/bp_softcore.v
$BP_TOP_DIR/src/v/bp_tile.v
$BP_TOP_DIR/src/v/bp_tile_node.v
$BP_TOP_DIR/src/v/bsg_async_noc_link.v
$BASEJUMP_STL_DIR/bsg_fsb/bsg_fsb_node_trace_replay.v
//$BP_BE_DIR/test/common/bp_be_nonsynth_perf.v
//$BP_BE_DIR/test/common/bp_be_nonsynth_npc_tracer.v
//$BP_BE_DIR/test/common/bp_be_nonsynth_vm_tracer.v
//$BP_ME_DIR/test/common/bp_mem.v
//$BP_ME_DIR/test/common/bp_mem_transducer.v
//$BP_ME_DIR/test/common/bp_mem_delay_model.v
//$BP_ME_DIR/test/common/bp_mem_storage_sync.v
$BP_ME_DIR/test/common/bp_cce_mmio_cfg_loader.v
//$BP_ME_DIR/test/common/dramsim2_wrapper.cpp
//$BP_ME_DIR/test/common/bp_mem_utils.cpp
//$BP_ME_DIR/test/common/bp_me_nonsynth_cce_tracer.v
//$BP_ME_DIR/test/common/bp_mem_nonsynth_tracer.v
//$BP_TOP_DIR/test/common/bp_nonsynth_watchdog.v
//$BP_TOP_DIR/test/common/bp_nonsynth_cosim.v
//$BP_TOP_DIR/test/common/bp_nonsynth_host.v
//$BP_TOP_DIR/test/common/bp_nonsynth_if_verif.v
//$BP_TOP_DIR/test/common/bp_nonsynth_commit_tracer.v
//$BP_TOP_DIR/test/common/bp_nonsynth_cache_tracer.v
$BP_TOP_DIR/test/common/bp_nonsynth_nbf_loader.v
//$BP_TOP_DIR/test/common/bp_monitor.cpp
//$BP_TOP_DIR/test/common/dromajo_cosim.cpp
//$BP_TOP_DIR/test/common/bp_nonsynth_core_profiler.v
//$BP_TOP_DIR/test/common/bp_nonsynth_pc_profiler.v
//$BP_TOP_DIR/test/common/bp_nonsynth_branch_profiler.v
$BP_LITEX_DIR/bp2wb_convertor.v
$BP_LITEX_DIR/fpga/ExampleBlackParrotSystem.v

269
litex/soc/cores/cpu/blackparrot/bp_litex/flist.verilator
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@ -1,269 +0,0 @@
+incdir+$BASEJUMP_STL_DIR/bsg_dataflow
+incdir+$BASEJUMP_STL_DIR/bsg_mem
+incdir+$BASEJUMP_STL_DIR/bsg_misc
+incdir+$BASEJUMP_STL_DIR/bsg_test
+incdir+$BASEJUMP_STL_DIR/bsg_noc
+incdir+$BP_COMMON_DIR/src/include
+incdir+$BP_FE_DIR/src/include
+incdir+$BP_BE_DIR/src/include
+incdir+$BP_BE_DIR/src/include/bp_be_dcache
+incdir+$BP_ME_DIR/src/include/v
+incdir+$BP_TOP_DIR/src/include
$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_pkg.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_noc_pkg.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_pkg.v
$BP_COMMON_DIR/src/include/bp_common_rv64_pkg.vh
$BP_COMMON_DIR/src/include/bp_common_pkg.vh
$BP_COMMON_DIR/src/include/bp_common_aviary_pkg.vh
$BP_COMMON_DIR/src/include/bp_common_cfg_link_pkg.vh
$BP_FE_DIR/src/include/bp_fe_icache_pkg.vh
$BP_FE_DIR/src/include/bp_fe_pkg.vh
$BP_BE_DIR/src/include/bp_be_pkg.vh
$BP_BE_DIR/src/include/bp_be_dcache/bp_be_dcache_pkg.vh
$BP_ME_DIR/src/include/v/bp_me_pkg.vh
$BP_ME_DIR/src/include/v/bp_cce_pkg.v
$BASEJUMP_STL_DIR/bsg_async/bsg_async_fifo.v
$BASEJUMP_STL_DIR/bsg_async/bsg_launch_sync_sync.v
$BASEJUMP_STL_DIR/bsg_async/bsg_async_ptr_gray.v
$BASEJUMP_STL_DIR/bsg_cache/bsg_cache.v
$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_dma.v
$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_miss.v
$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_decode.v
$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_sbuf.v
$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_sbuf_queue.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel_in.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel_out.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_1_to_n_tagged_fifo.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_1_to_n_tagged.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_large.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_pseudo_large.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_small.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_small_unhardened.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1rw_large.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_tracker.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_flow_counter.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_one_fifo.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_parallel_in_serial_out.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_parallel_in_serial_out_dynamic.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_1_to_n.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_2_to_2.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_n_to_1.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out_dynamic.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out_full.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_shift_reg.v
$BASEJUMP_STL_DIR/bsg_dataflow/bsg_two_fifo.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_cam_1r1w.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_sync.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_sync_synth.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_synth.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v
//$BP_LITEX_DIR/bsg_mem_1rw_sync_mask_write_bit.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_synth.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_synth.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_2r1w_sync.v
$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_2r1w_sync_synth.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_adder_cin.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_adder_ripple_carry.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_arb_fixed.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_array_concentrate_static.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_buf.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_buf_ctrl.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_circular_ptr.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_concentrate_static.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_clear_up.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_set_down.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_set_en.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_up_down.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_up_down_variable.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_crossbar_o_by_i.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_cycle_counter.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_decode.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_decode_with_v.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_dff.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en_bypass.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset_en_bypass.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_chain.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset_en.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_edge_detect.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_encode_one_hot.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_expand_bitmask.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_hash_bank.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_hash_bank_reverse.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_idiv_iterative.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_idiv_iterative_controller.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_lfsr.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_lru_pseudo_tree_decode.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_lru_pseudo_tree_encode.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_mux.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_butterfly.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_one_hot.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_segmented.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_muxi2_gatestack.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_nor2.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_nor3.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_nand.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode_one_hot_out.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_reduce.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_reduce_segmented.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_round_robin_arb.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_scan.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_strobe.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_swap.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_thermometer_count.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_transpose.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_unconcentrate_static.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_xnor.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_mesh_stitch.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_noc_repeater_node.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator_in.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator_out.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_in.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_out.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_decoder_dor.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_input_control.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_output_control.v
$BP_COMMON_DIR/src/v/bsg_fifo_1r1w_rolly.v
$BP_COMMON_DIR/src/v/bp_pma.v
$BP_COMMON_DIR/src/v/bp_tlb.v
$BP_COMMON_DIR/src/v/bp_tlb_replacement.v
$BP_BE_DIR/src/v/bp_be_top.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_bypass.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_calculator_top.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_instr_decoder.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_int_alu.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_fp.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_int.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_ctrl.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_long.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_mem.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_mul.v
$BP_BE_DIR/src/v/bp_be_calculator/bp_be_regfile.v
$BP_BE_DIR/src/v/bp_be_checker/bp_be_checker_top.v
$BP_BE_DIR/src/v/bp_be_checker/bp_be_detector.v
$BP_BE_DIR/src/v/bp_be_checker/bp_be_director.v
$BP_BE_DIR/src/v/bp_be_checker/bp_be_scheduler.v
$BP_BE_DIR/src/v/bp_be_mem/bp_be_ptw.v
$BP_BE_DIR/src/v/bp_be_mem/bp_be_csr.v
$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache.v
$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce_cmd.v
$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce.v
$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce_req.v
$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf.v
$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf_queue.v
$BP_BE_DIR/src/v/bp_be_mem/bp_be_mem_top.v
$BP_FE_DIR/src/v/bp_fe_bht.v
$BP_FE_DIR/src/v/bp_fe_btb.v
$BP_FE_DIR/src/v/bp_fe_lce_cmd.v
$BP_FE_DIR/src/v/bp_fe_icache.v
$BP_FE_DIR/src/v/bp_fe_instr_scan.v
$BP_FE_DIR/src/v/bp_fe_lce.v
$BP_FE_DIR/src/v/bp_fe_lce_req.v
$BP_FE_DIR/src/v/bp_fe_mem.v
$BP_FE_DIR/src/v/bp_fe_pc_gen.v
$BP_FE_DIR/src/v/bp_fe_top.v
$BP_ME_DIR/src/v/cache/bp_me_cache_dma_to_cce.v
$BP_ME_DIR/src/v/cache/bp_me_cache_slice.v
$BP_ME_DIR/src/v/cache/bp_me_cce_to_cache.v
$BP_ME_DIR/src/v/cce/bp_cce.v
$BP_ME_DIR/src/v/cce/bp_cce_alu.v
$BP_ME_DIR/src/v/cce/bp_cce_arbitrate.v
$BP_ME_DIR/src/v/cce/bp_cce_branch.v
$BP_ME_DIR/src/v/cce/bp_cce_buffered.v
$BP_ME_DIR/src/v/cce/bp_cce_dir.v
$BP_ME_DIR/src/v/cce/bp_cce_dir_lru_extract.v
$BP_ME_DIR/src/v/cce/bp_cce_dir_segment.v
$BP_ME_DIR/src/v/cce/bp_cce_dir_tag_checker.v
$BP_ME_DIR/src/v/cce/bp_cce_gad.v
$BP_ME_DIR/src/v/cce/bp_cce_inst_decode.v
$BP_ME_DIR/src/v/cce/bp_cce_inst_predecode.v
$BP_ME_DIR/src/v/cce/bp_cce_inst_ram.v
$BP_ME_DIR/src/v/cce/bp_cce_inst_stall.v
$BP_ME_DIR/src/v/cce/bp_cce_msg.v
$BP_ME_DIR/src/v/cce/bp_cce_pending_bits.v
$BP_ME_DIR/src/v/cce/bp_cce_reg.v
$BP_ME_DIR/src/v/cce/bp_cce_spec_bits.v
$BP_ME_DIR/src/v/cce/bp_cce_src_sel.v
$BP_ME_DIR/src/v/cce/bp_io_cce.v
$BP_ME_DIR/src/v/cce/bp_cce_fsm.v
$BP_ME_DIR/src/v/cce/bp_cce_wrapper.v
$BP_ME_DIR/src/v/cce/bp_uce.v
$BP_ME_DIR/src/v/wormhole/bp_me_addr_to_cce_id.v
$BP_ME_DIR/src/v/wormhole/bp_me_cce_id_to_cord.v
$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_bidir.v
$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_client.v
$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_master.v
$BP_ME_DIR/src/v/wormhole/bp_me_cord_to_id.v
$BP_ME_DIR/src/v/wormhole/bp_me_lce_id_to_cord.v
$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_cmd.v
$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_req.v
$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_resp.v
$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_cmd.v
$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_resp.v
$BP_TOP_DIR/src/v/bp_nd_socket.v
$BP_TOP_DIR/src/v/bp_cacc_vdp.v
$BP_TOP_DIR/src/v/bp_cacc_tile.v
$BP_TOP_DIR/src/v/bp_cacc_tile_node.v
$BP_TOP_DIR/src/v/bp_cacc_complex.v
$BP_TOP_DIR/src/v/bp_sacc_vdp.v
$BP_TOP_DIR/src/v/bp_sacc_tile.v
$BP_TOP_DIR/src/v/bp_sacc_tile_node.v
$BP_TOP_DIR/src/v/bp_sacc_complex.v
$BP_TOP_DIR/src/v/bp_cfg.v
$BP_TOP_DIR/src/v/bp_core.v
$BP_TOP_DIR/src/v/bp_core_complex.v
$BP_TOP_DIR/src/v/bp_core_minimal.v
$BP_TOP_DIR/src/v/bp_clint.v
$BP_TOP_DIR/src/v/bp_clint_node.v
$BP_TOP_DIR/src/v/bp_clint_slice.v
$BP_TOP_DIR/src/v/bp_l2e_tile.v
$BP_TOP_DIR/src/v/bp_l2e_tile_node.v
$BP_TOP_DIR/src/v/bp_io_complex.v
$BP_TOP_DIR/src/v/bp_io_link_to_lce.v
$BP_TOP_DIR/src/v/bp_io_tile.v
$BP_TOP_DIR/src/v/bp_io_tile_node.v
$BP_TOP_DIR/src/v/bp_mem_complex.v
$BP_TOP_DIR/src/v/bp_processor.v
$BP_TOP_DIR/src/v/bp_softcore.v
$BP_TOP_DIR/src/v/bp_tile.v
$BP_TOP_DIR/src/v/bp_tile_node.v
$BP_TOP_DIR/src/v/bsg_async_noc_link.v
$BASEJUMP_STL_DIR/bsg_fsb/bsg_fsb_node_trace_replay.v
//$BP_BE_DIR/test/common/bp_be_nonsynth_perf.v
//$BP_BE_DIR/test/common/bp_be_nonsynth_npc_tracer.v
//$BP_BE_DIR/test/common/bp_be_nonsynth_vm_tracer.v
//$BP_ME_DIR/test/common/bp_mem.v
//$BP_ME_DIR/test/common/bp_mem_transducer.v
//$BP_ME_DIR/test/common/bp_mem_delay_model.v
//$BP_ME_DIR/test/common/bp_mem_storage_sync.v
$BP_ME_DIR/test/common/bp_cce_mmio_cfg_loader.v
//$BP_ME_DIR/test/common/dramsim2_wrapper.cpp
//$BP_ME_DIR/test/common/bp_mem_utils.cpp
//$BP_ME_DIR/test/common/bp_me_nonsynth_cce_tracer.v
$BP_ME_DIR/test/common/bp_mem_nonsynth_tracer.v
//$BP_TOP_DIR/test/common/bp_nonsynth_watchdog.v
//$BP_TOP_DIR/test/common/bp_nonsynth_cosim.v
//$BP_TOP_DIR/test/common/bp_nonsynth_host.v
//$BP_TOP_DIR/test/common/bp_nonsynth_if_verif.v
$BP_TOP_DIR/test/common/bp_nonsynth_commit_tracer.v
//$BP_TOP_DIR/test/common/bp_nonsynth_cache_tracer.v
$BP_TOP_DIR/test/common/bp_nonsynth_nbf_loader.v
//$BP_TOP_DIR/test/common/bp_monitor.cpp
//$BP_TOP_DIR/test/common/dromajo_cosim.cpp
//$BP_TOP_DIR/test/common/bp_nonsynth_core_profiler.v
//$BP_TOP_DIR/test/common/bp_nonsynth_pc_profiler.v
//$BP_TOP_DIR/test/common/bp_nonsynth_branch_profiler.v
$BP_LITEX_DIR/bp2wb_convertor.v
$BP_LITEX_DIR/simulation/ExampleBlackParrotSystem.v

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litex/soc/cores/cpu/blackparrot/bp_litex/fpga/ExampleBlackParrotSystem.v
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@ -1,623 +0,0 @@
/**
*
* ExampleBlackParrotSystem.v
*
*/
`include "bsg_noc_links.vh"
module ExampleBlackParrotSystem
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_be_pkg::*;
import bp_common_rv64_pkg::*;
import bp_cce_pkg::*;
import bp_me_pkg::*;
import bp_common_cfg_link_pkg::*;
import bsg_noc_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_softcore_no_l2_cfg// e_bp_softcore_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_fe_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p)
`declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
// Tracing parameters
, parameter calc_trace_p = 0
, parameter cce_trace_p = 0
, parameter cmt_trace_p = 0
, parameter dram_trace_p = 0
, parameter npc_trace_p = 0
, parameter icache_trace_p = 0
, parameter dcache_trace_p = 0
, parameter vm_trace_p = 0
, parameter core_profile_p = 0
, parameter preload_mem_p = 0
, parameter load_nbf_p = 0
, parameter skip_init_p = 0
, parameter cosim_p = 0
, parameter cosim_cfg_file_p = "prog.cfg"
, parameter cosim_instr_p = 0
, parameter warmup_instr_p = 0
, parameter mem_zero_p = 1
, parameter mem_file_p = "prog.mem"
, parameter mem_cap_in_bytes_p = 2**28
, parameter [paddr_width_p-1:0] mem_offset_p = dram_base_addr_gp
// Number of elements in the fake BlackParrot memory
/*, parameter use_max_latency_p = 0
, parameter use_random_latency_p = 0
, parameter use_dramsim2_latency_p = 0
, parameter max_latency_p = 15
, parameter dram_clock_period_in_ps_p = `BP_SIM_CLK_PERIOD
, parameter dram_cfg_p = "dram_ch.ini"
, parameter dram_sys_cfg_p = "dram_sys.ini"
, parameter dram_capacity_p = 16384
*/
)
(input clk_i
, input reset_i
//Wishbone interface
, input [63:0] wbm_dat_i
, output [63:0] wbm_dat_o
, input wbm_ack_i
, input wbm_err_i
, input wbm_rty_i
, output [36:0] wbm_adr_o //TODO parametrize this
, output wbm_stb_o
, output wbm_cyc_o
, output [7:0] wbm_sel_o
, output wbm_we_o
, output [2:0] wbm_cti_o //TODO:
, output [1:0] wbm_bte_o
// , input [3:0] interrupts
);
`declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
initial begin
if (num_core_p > 1) begin
assert (cosim_p == 0) else $error("cosim_p not supported for num_core_p > 1");
end
end
logic [num_core_p-1:0] program_finish_lo;
logic cosim_finish_lo;
bp_cce_mem_msg_s proc_mem_cmd_lo;
logic proc_mem_cmd_v_lo, proc_mem_cmd_ready_li;
bp_cce_mem_msg_s proc_mem_resp_li;
logic proc_mem_resp_v_li, proc_mem_resp_yumi_lo;
bp_cce_mem_msg_s proc_io_cmd_lo;
logic proc_io_cmd_v_lo, proc_io_cmd_ready_li;
bp_cce_mem_msg_s proc_io_resp_li;
logic proc_io_resp_v_li, proc_io_resp_yumi_lo;
bp_cce_mem_msg_s io_cmd_lo;
logic io_cmd_v_lo, io_cmd_ready_li;
bp_cce_mem_msg_s io_resp_li;
logic io_resp_v_li, io_resp_yumi_lo;
bp_cce_mem_msg_s nbf_cmd_lo;
logic nbf_cmd_v_lo, nbf_cmd_yumi_li;
bp_cce_mem_msg_s nbf_resp_li;
logic nbf_resp_v_li, nbf_resp_ready_lo;
bp_cce_mem_msg_s cfg_cmd_lo;
logic cfg_cmd_v_lo, cfg_cmd_yumi_li;
bp_cce_mem_msg_s cfg_resp_li;
logic cfg_resp_v_li, cfg_resp_ready_lo;
bp_cce_mem_msg_s load_cmd_lo;
logic load_cmd_v_lo, load_cmd_yumi_li;
bp_cce_mem_msg_s load_resp_li;
logic load_resp_v_li, load_resp_ready_lo;
bp_softcore
#(.bp_params_p(bp_params_p))
softcore
(.clk_i(clk_i)
,.reset_i(reset_i)
,.io_cmd_o(proc_io_cmd_lo)
,.io_cmd_v_o(proc_io_cmd_v_lo)
,.io_cmd_ready_i(proc_io_cmd_ready_li)
,.io_resp_i(proc_io_resp_li)
,.io_resp_v_i(proc_io_resp_v_li)
,.io_resp_yumi_o(proc_io_resp_yumi_lo)
,.io_cmd_i(load_cmd_lo)
,.io_cmd_v_i(load_cmd_v_lo)
,.io_cmd_yumi_o(load_cmd_yumi_li)
,.io_resp_o(load_resp_li)
,.io_resp_v_o(load_resp_v_li)
,.io_resp_ready_i(load_resp_ready_lo)
,.mem_cmd_o(proc_mem_cmd_lo)
,.mem_cmd_v_o(proc_mem_cmd_v_lo)
,.mem_cmd_ready_i(proc_mem_cmd_ready_li)
,.mem_resp_i(proc_mem_resp_li)
,.mem_resp_v_i(proc_mem_resp_v_li)
,.mem_resp_yumi_o(proc_mem_resp_yumi_lo)
);
bp2wb_convertor
#(.bp_params_p(bp_params_p))
bp2wb
(.clk_i(clk_i)
,.reset_i(reset_i)
,.mem_cmd_i(proc_mem_cmd_lo)
,.mem_cmd_v_i(proc_mem_cmd_ready_li & proc_mem_cmd_v_lo)
,.mem_cmd_ready_o(proc_mem_cmd_ready_li)
,.mem_resp_o(proc_mem_resp_li)
,.mem_resp_v_o(proc_mem_resp_v_li)
,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
,.dat_i(wbm_dat_i)
,.dat_o(wbm_dat_o)
,.ack_i(wbm_ack_i)
,.adr_o(wbm_adr_o)
,.stb_o(wbm_stb_o)
,.cyc_o(wbm_cyc_o)
,.sel_o(wbm_sel_o )
,.we_o(wbm_we_o)
,.cti_o(wbm_cti_o)
,.bte_o(wbm_bte_o )
// ,.rty_i(wbm_rty_i)
,.err_i(wbm_err_i)
);
assign proc_io_cmd_ready_li = 1;//TODO: make sure this is necessary
logic nbf_done_lo, cfg_done_lo;
if (load_nbf_p)
begin : nbf
bp_nonsynth_nbf_loader
#(.bp_params_p(bp_params_p))
nbf_loader
(.clk_i(clk_i)
,.reset_i(reset_i | ~cfg_done_lo)
,.lce_id_i(lce_id_width_p'('b10))
,.io_cmd_o(nbf_cmd_lo)
,.io_cmd_v_o(nbf_cmd_v_lo)
,.io_cmd_yumi_i(nbf_cmd_yumi_li)
,.io_resp_i(nbf_resp_li)
,.io_resp_v_i(nbf_resp_v_li)
,.io_resp_ready_o(nbf_resp_ready_lo)
,.done_o(nbf_done_lo)
);
end
else
begin : no_nbf
assign nbf_resp_ready_lo = 1'b1;
assign nbf_cmd_v_lo = '0;
assign nbf_cmd_lo = '0;
assign nbf_done_lo = 1'b1;
end
localparam cce_instr_ram_addr_width_lp = `BSG_SAFE_CLOG2(num_cce_instr_ram_els_p);
bp_cce_mmio_cfg_loader
#(.bp_params_p(bp_params_p)
,.inst_width_p($bits(bp_cce_inst_s))
,.inst_ram_addr_width_p(cce_instr_ram_addr_width_lp)
,.inst_ram_els_p(num_cce_instr_ram_els_p)
,.skip_ram_init_p(skip_init_p)
,.clear_freeze_p(!load_nbf_p)
,.cce_ucode_filename_p("/tmp/cce_ucode.mem")
)
cfg_loader
(.clk_i(clk_i)
,.reset_i(reset_i)
,.lce_id_i(lce_id_width_p'('b10))
,.io_cmd_o(cfg_cmd_lo)
,.io_cmd_v_o(cfg_cmd_v_lo)
,.io_cmd_yumi_i(cfg_cmd_yumi_li)
,.io_resp_i(cfg_resp_li)
,.io_resp_v_i(cfg_resp_v_li)
,.io_resp_ready_o(cfg_resp_ready_lo)
,.done_o(cfg_done_lo)
);
// CFG and NBF are mutex, so we can just use fixed arbitration here
always_comb
if (~cfg_done_lo)
begin
load_cmd_lo = cfg_cmd_lo;
load_cmd_v_lo = cfg_cmd_v_lo;
nbf_cmd_yumi_li = '0;
cfg_cmd_yumi_li = load_cmd_yumi_li;
load_resp_ready_lo = cfg_resp_ready_lo;
nbf_resp_li = '0;
nbf_resp_v_li = '0;
cfg_resp_li = load_resp_li;
cfg_resp_v_li = load_resp_v_li;
end
else
begin
load_cmd_lo = nbf_cmd_lo;
load_cmd_v_lo = nbf_cmd_v_lo;
nbf_cmd_yumi_li = load_cmd_yumi_li;
cfg_cmd_yumi_li = '0;
load_resp_ready_lo = nbf_resp_ready_lo;
nbf_resp_li = load_resp_li;
nbf_resp_v_li = load_resp_v_li;
cfg_resp_li = '0;
cfg_resp_v_li = '0;
end
/*bp_nonsynth_host
#(.bp_params_p(bp_params_p))
host
(.clk_i(clk_i)
,.reset_i(reset_i)
,.io_cmd_i(proc_io_cmd_lo)
,.io_cmd_v_i(proc_io_cmd_v_lo & proc_io_cmd_ready_li)
,.io_cmd_ready_o(proc_io_cmd_ready_li)
,.io_resp_o(proc_io_resp_li)
,.io_resp_v_o(proc_io_resp_v_li)
,.io_resp_yumi_i(proc_io_resp_yumi_lo)
,.program_finish_o(program_finish_lo)
);
*/
/*bind bp_be_top
bp_nonsynth_commit_tracer
#(.bp_params_p(bp_params_p))
commit_tracer
(.clk_i(clk_i & (ExampleBlackParrotSystem.cmt_trace_p == 1))
,.reset_i(reset_i)
,.freeze_i(be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.mhartid_i('0)
,.decode_i(be_calculator.reservation_n.decode)
,.commit_v_i(be_calculator.commit_pkt.instret)
,.commit_pc_i(be_calculator.commit_pkt.pc)
,.commit_instr_i(be_calculator.commit_pkt.instr)
,.rd_w_v_i(be_checker.scheduler.wb_pkt.rd_w_v)
,.rd_addr_i(be_checker.scheduler.wb_pkt.rd_addr)
,.rd_data_i(be_checker.scheduler.wb_pkt.rd_data)
);
*/
/* if (num_core_p == 1)
begin : cosim
bind bp_be_top
bp_nonsynth_cosim
#(.bp_params_p(bp_params_p))
cosim
(.clk_i(clk_i)
,.reset_i(reset_i)
,.freeze_i(be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.en_i(ExampleBlackParrotSystem.cosim_p == 1)
,.cosim_instr_i(ExampleBlackParrotSystem.cosim_instr_p)
,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
// Want to pass config file as a parameter, but cannot in Verilator 4.025
// Parameter-resolved constants must not use dotted references
,.config_file_i(ExampleBlackParrotSystem.cosim_cfg_file_p)
,.decode_i(be_calculator.reservation_n.decode)
,.commit_v_i(be_calculator.commit_pkt.instret)
,.commit_pc_i(be_calculator.commit_pkt.pc)
,.commit_instr_i(be_calculator.commit_pkt.instr)
,.rd_w_v_i(be_checker.scheduler.wb_pkt.rd_w_v)
,.rd_addr_i(be_checker.scheduler.wb_pkt.rd_addr)
,.rd_data_i(be_checker.scheduler.wb_pkt.rd_data)
,.interrupt_v_i(be_mem.csr.trap_pkt_cast_o._interrupt)
,.cause_i(be_mem.csr.trap_pkt_cast_o.cause)
,.finish_o(ExampleBlackParrotSystem.cosim_finish_lo)
);
end
else
begin : no_cosim*/
assign cosim_finish_lo = '0;
// end
/*bind bp_be_top
bp_be_nonsynth_perf
#(.bp_params_p(bp_params_p))
perf
(.clk_i(clk_i)
,.reset_i(reset_i)
,.freeze_i(be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.warmup_instr_i(ExampleBlackParrotSystem.warmup_instr_p)
,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
,.commit_v_i(be_calculator.commit_pkt.instret)
,.program_finish_i(ExampleBlackParrotSystem.program_finish_lo | ExampleBlackParrotSystem.cosim_finish_lo)
);
*/
/* bind bp_be_top
bp_nonsynth_watchdog
#(.bp_params_p(bp_params_p)
,.timeout_cycles_p(100000)
,.heartbeat_instr_p(100000)
)
watchdog
(.clk_i(clk_i)
,.reset_i(reset_i)
,.freeze_i(be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
,.npc_i(be_checker.director.npc_r)
,.instret_i(be_calculator.commit_pkt.instret)
);
*/
/* bind bp_be_director
bp_be_nonsynth_npc_tracer
#(.bp_params_p(bp_params_p))
npc_tracer
(.clk_i(clk_i & (ExampleBlackParrotSystem.npc_trace_p == 1))
,.reset_i(reset_i)
,.freeze_i(be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
,.npc_w_v(npc_w_v)
,.npc_n(npc_n)
,.npc_r(npc_r)
,.expected_npc_o(expected_npc_o)
,.fe_cmd_i(fe_cmd)
,.fe_cmd_v(fe_cmd_v)
,.commit_pkt_i(commit_pkt)
);
*/
/* bind bp_be_dcache
bp_nonsynth_cache_tracer
#(.bp_params_p(bp_params_p)
,.assoc_p(dcache_assoc_p)
,.sets_p(dcache_sets_p)
,.block_width_p(dcache_block_width_p)
,.trace_file_p("dcache"))
dcache_tracer
(.clk_i(clk_i & (ExampleBlackParrotSystem.dcache_trace_p == 1))
,.reset_i(reset_i)
,.freeze_i(cfg_bus_cast_i.freeze)
,.mhartid_i(cfg_bus_cast_i.core_id)
,.v_tl_r(v_tl_r)
,.v_tv_r(v_tv_r)
,.addr_tv_r(paddr_tv_r)
,.lr_miss_tv(lr_miss_tv)
,.sc_op_tv_r(sc_op_tv_r)
,.sc_success(sc_success)
,.cache_req_v_o(cache_req_v_o)
,.cache_req_o(cache_req_o)
,.cache_req_metadata_o(cache_req_metadata_o)
,.cache_req_metadata_v_o(cache_req_metadata_v_o)
,.cache_req_complete_i(cache_req_complete_i)
,.v_o(v_o)
,.load_data(data_o)
,.cache_miss_o(dcache_miss_o)
,.wt_req(wt_req)
,.store_data(data_tv_r)
,.data_mem_pkt_v_i(data_mem_pkt_v_i)
,.data_mem_pkt_i(data_mem_pkt_i)
,.data_mem_pkt_yumi_o(data_mem_pkt_yumi_o)
,.tag_mem_pkt_v_i(tag_mem_pkt_v_i)
,.tag_mem_pkt_i(tag_mem_pkt_i)
,.tag_mem_pkt_yumi_o(tag_mem_pkt_yumi_o)
,.stat_mem_pkt_v_i(stat_mem_pkt_v_i)
,.stat_mem_pkt_i(stat_mem_pkt_i)
,.stat_mem_pkt_yumi_o(stat_mem_pkt_yumi_o)
);
*/
/* bind bp_fe_icache
bp_nonsynth_cache_tracer
#(.bp_params_p(bp_params_p)
,.assoc_p(icache_assoc_p)
,.sets_p(icache_sets_p)
,.block_width_p(icache_block_width_p)
,.trace_file_p("icache"))
icache_tracer
(.clk_i(clk_i & (ExampleBlackParrotSystem.icache_trace_p == 1))
,.reset_i(reset_i)
,.freeze_i(cfg_bus_cast_i.freeze)
,.mhartid_i(cfg_bus_cast_i.core_id)
,.v_tl_r(v_tl_r)
,.v_tv_r(v_tv_r)
,.addr_tv_r(addr_tv_r)
,.lr_miss_tv(1'b0)
,.sc_op_tv_r(1'b0)
,.sc_success(1'b0)
,.cache_req_v_o(cache_req_v_o)
,.cache_req_o(cache_req_o)
,.cache_req_metadata_o(cache_req_metadata_o)
,.cache_req_metadata_v_o(cache_req_metadata_v_o)
,.cache_req_complete_i(cache_req_complete_i)
,.v_o(data_v_o)
,.load_data(dword_width_p'(data_o))
,.cache_miss_o(miss_o)
,.wt_req()
,.store_data(dword_width_p'(0))
,.data_mem_pkt_v_i(data_mem_pkt_v_i)
,.data_mem_pkt_i(data_mem_pkt_i)
,.data_mem_pkt_yumi_o(data_mem_pkt_yumi_o)
,.tag_mem_pkt_v_i(tag_mem_pkt_v_i)
,.tag_mem_pkt_i(tag_mem_pkt_i)
,.tag_mem_pkt_yumi_o(tag_mem_pkt_yumi_o)
,.stat_mem_pkt_v_i(stat_mem_pkt_v_i)
,.stat_mem_pkt_i(stat_mem_pkt_i)
,.stat_mem_pkt_yumi_o(stat_mem_pkt_yumi_o)
);
*/
/* bind bp_core_minimal
bp_be_nonsynth_vm_tracer
#(.bp_params_p(bp_params_p))
vm_tracer
(.clk_i(clk_i & (ExampleBlackParrotSystem.vm_trace_p == 1))
,.reset_i(reset_i)
,.freeze_i(be.be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.mhartid_i(be.be_checker.scheduler.int_regfile.cfg_bus.core_id)
,.itlb_clear_i(fe.mem.itlb.flush_i)
,.itlb_fill_v_i(fe.mem.itlb.v_i & fe.mem.itlb.w_i)
,.itlb_vtag_i(fe.mem.itlb.vtag_i)
,.itlb_entry_i(fe.mem.itlb.entry_i)
,.dtlb_clear_i(be.be_mem.dtlb.flush_i)
,.dtlb_fill_v_i(be.be_mem.dtlb.v_i & be.be_mem.dtlb.w_i)
,.dtlb_vtag_i(be.be_mem.dtlb.vtag_i)
,.dtlb_entry_i(be.be_mem.dtlb.entry_i)
);
*/
/* bp_mem_nonsynth_tracer
#(.bp_params_p(bp_params_p))
bp_mem_tracer
(.clk_i(clk_i & (ExampleBlackParrotSystem.dram_trace_p == 1))
,.reset_i(reset_i)
,.mem_cmd_i(proc_mem_cmd_lo)
,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
,.mem_cmd_ready_i(proc_mem_cmd_ready_li)
,.mem_resp_i(proc_mem_resp_li)
,.mem_resp_v_i(proc_mem_resp_v_li)
,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
);
*/
/* bind bp_core_minimal
bp_nonsynth_core_profiler
#(.bp_params_p(bp_params_p))
core_profiler
(.clk_i(clk_i & (ExampleBlackParrotSystem.core_profile_p == 1))
,.reset_i(reset_i)
,.freeze_i(be.be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.mhartid_i(be.be_checker.scheduler.int_regfile.cfg_bus.core_id)
,.fe_wait_stall(fe.pc_gen.is_wait)
,.fe_queue_stall(~fe.pc_gen.fe_queue_ready_i)
,.itlb_miss(fe.mem.itlb_miss_r)
,.icache_miss(~fe.mem.icache.vaddr_ready_o | fe.pc_gen.icache_miss)
,.icache_fence(fe.mem.icache.fencei_req)
,.branch_override(fe.pc_gen.ovr_taken & ~fe.pc_gen.ovr_ret)
,.ret_override(fe.pc_gen.ovr_ret)
,.fe_cmd(fe.pc_gen.fe_cmd_yumi_o & ~fe.pc_gen.attaboy_v)
,.mispredict(be.be_checker.director.npc_mismatch_v)
,.target(be.be_checker.director.isd_status.isd_pc)
,.dtlb_miss(be.be_mem.dtlb_miss_r)
,.dcache_miss(~be.be_mem.dcache.ready_o)
,.long_haz(be.be_checker.detector.long_haz_v)
,.exception(be.be_checker.director.trap_pkt.exception)
,.eret(be.be_checker.director.trap_pkt.eret)
,._interrupt(be.be_checker.director.trap_pkt._interrupt)
,.control_haz(be.be_checker.detector.control_haz_v)
,.data_haz(be.be_checker.detector.data_haz_v)
,.load_dep((be.be_checker.detector.dep_status_li[0].mem_iwb_v
| be.be_checker.detector.dep_status_li[1].mem_iwb_v
) & be.be_checker.detector.data_haz_v
)
,.mul_dep((be.be_checker.detector.dep_status_li[0].mul_iwb_v
| be.be_checker.detector.dep_status_li[1].mul_iwb_v
| be.be_checker.detector.dep_status_li[2].mul_iwb_v
) & be.be_checker.detector.data_haz_v
)
,.struct_haz(be.be_checker.detector.struct_haz_v)
,.reservation(be.be_calculator.reservation_n)
,.commit_pkt(be.be_calculator.commit_pkt)
,.trap_pkt(be.be_mem.csr.trap_pkt_o)
);
*/
/* bind bp_core_minimal
bp_nonsynth_pc_profiler
#(.bp_params_p(bp_params_p))
pc_profiler
(.clk_i(clk_i & (ExampleBlackParrotSystem.core_profile_p == 1))
,.reset_i(reset_i)
,.freeze_i(be.be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.mhartid_i(be.be_checker.scheduler.int_regfile.cfg_bus.core_id)
,.commit_pkt(be.be_calculator.commit_pkt)
,.program_finish_i(ExampleBlackParrotSystem.program_finish_lo)
);
*/
/* bind bp_be_director
bp_nonsynth_branch_profiler
#(.bp_params_p(bp_params_p))
pc_profiler
(.clk_i(clk_i & (ExampleBlackParrotSystem.core_profile_p == 1))
,.reset_i(reset_i)
,.freeze_i(cfg_bus_cast_i.freeze)
,.mhartid_i(cfg_bus_cast_i.core_id)
,.fe_cmd_o(fe_cmd_o)
,.fe_cmd_v_o(fe_cmd_v_o)
,.fe_cmd_ready_i(fe_cmd_ready_i)
,.commit_v_i(commit_pkt.instret)
,.program_finish_i(ExampleBlackParrotSystem.program_finish_lo)
);
*/
/* bp_nonsynth_if_verif
#(.bp_params_p(bp_params_p))
if_verif
();
*/
endmodule

622
litex/soc/cores/cpu/blackparrot/bp_litex/simulation/ExampleBlackParrotSystem.v
View File

@ -1,622 +0,0 @@
/**
*
* ExampleBlackParrotSystem.v
*
*/
`include "bsg_noc_links.vh"
module ExampleBlackParrotSystem
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_be_pkg::*;
import bp_common_rv64_pkg::*;
import bp_cce_pkg::*;
import bp_me_pkg::*;
import bp_common_cfg_link_pkg::*;
import bsg_noc_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_softcore_no_l2_cfg// e_bp_softcore_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_fe_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p)
`declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
// Tracing parameters
, parameter calc_trace_p = 0
, parameter cce_trace_p = 0
, parameter cmt_trace_p = 0
, parameter dram_trace_p = 0
, parameter npc_trace_p = 0
, parameter icache_trace_p = 0
, parameter dcache_trace_p = 0
, parameter vm_trace_p = 0
, parameter core_profile_p = 0
, parameter preload_mem_p = 0
, parameter load_nbf_p = 0
, parameter skip_init_p = 0
, parameter cosim_p = 0
, parameter cosim_cfg_file_p = "prog.cfg"
, parameter cosim_instr_p = 0
, parameter warmup_instr_p = 0
, parameter mem_zero_p = 1
, parameter mem_file_p = "prog.mem"
, parameter mem_cap_in_bytes_p = 2**28
, parameter [paddr_width_p-1:0] mem_offset_p = dram_base_addr_gp
// Number of elements in the fake BlackParrot memory
/*, parameter use_max_latency_p = 0
, parameter use_random_latency_p = 0
, parameter use_dramsim2_latency_p = 0
, parameter max_latency_p = 15
, parameter dram_clock_period_in_ps_p = `BP_SIM_CLK_PERIOD
, parameter dram_cfg_p = "dram_ch.ini"
, parameter dram_sys_cfg_p = "dram_sys.ini"
, parameter dram_capacity_p = 16384
*/
)
(input clk_i
, input reset_i
//Wishbone interface
, input [63:0] wbm_dat_i
, output [63:0] wbm_dat_o
, input wbm_ack_i
, input wbm_err_i
, input wbm_rty_i
, output [36:0] wbm_adr_o //TODO parametrize this
, output wbm_stb_o
, output wbm_cyc_o
, output [7:0] wbm_sel_o
, output wbm_we_o
, output [2:0] wbm_cti_o //TODO:
, output [1:0] wbm_bte_o
// , input [3:0] interrupts
);
`declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
initial begin
if (num_core_p > 1) begin
assert (cosim_p == 0) else $error("cosim_p not supported for num_core_p > 1");
end
end
logic [num_core_p-1:0] program_finish_lo;
logic cosim_finish_lo;
bp_cce_mem_msg_s proc_mem_cmd_lo;
logic proc_mem_cmd_v_lo, proc_mem_cmd_ready_li;
bp_cce_mem_msg_s proc_mem_resp_li;
logic proc_mem_resp_v_li, proc_mem_resp_yumi_lo;
bp_cce_mem_msg_s proc_io_cmd_lo;
logic proc_io_cmd_v_lo, proc_io_cmd_ready_li;
bp_cce_mem_msg_s proc_io_resp_li;
logic proc_io_resp_v_li, proc_io_resp_yumi_lo;
bp_cce_mem_msg_s io_cmd_lo;
logic io_cmd_v_lo, io_cmd_ready_li;
bp_cce_mem_msg_s io_resp_li;
logic io_resp_v_li, io_resp_yumi_lo;
bp_cce_mem_msg_s nbf_cmd_lo;
logic nbf_cmd_v_lo, nbf_cmd_yumi_li;
bp_cce_mem_msg_s nbf_resp_li;
logic nbf_resp_v_li, nbf_resp_ready_lo;
bp_cce_mem_msg_s cfg_cmd_lo;
logic cfg_cmd_v_lo, cfg_cmd_yumi_li;
bp_cce_mem_msg_s cfg_resp_li;
logic cfg_resp_v_li, cfg_resp_ready_lo;
bp_cce_mem_msg_s load_cmd_lo;
logic load_cmd_v_lo, load_cmd_yumi_li;
bp_cce_mem_msg_s load_resp_li;
logic load_resp_v_li, load_resp_ready_lo;
bp_softcore
#(.bp_params_p(bp_params_p))
softcore
(.clk_i(clk_i)
,.reset_i(reset_i)
,.io_cmd_o(proc_io_cmd_lo)
,.io_cmd_v_o(proc_io_cmd_v_lo)
,.io_cmd_ready_i(proc_io_cmd_ready_li)
,.io_resp_i(proc_io_resp_li)
,.io_resp_v_i(proc_io_resp_v_li)
,.io_resp_yumi_o(proc_io_resp_yumi_lo)
,.io_cmd_i(load_cmd_lo)
,.io_cmd_v_i(load_cmd_v_lo)
,.io_cmd_yumi_o(load_cmd_yumi_li)
,.io_resp_o(load_resp_li)
,.io_resp_v_o(load_resp_v_li)
,.io_resp_ready_i(load_resp_ready_lo)
,.mem_cmd_o(proc_mem_cmd_lo)
,.mem_cmd_v_o(proc_mem_cmd_v_lo)
,.mem_cmd_ready_i(proc_mem_cmd_ready_li)
,.mem_resp_i(proc_mem_resp_li)
,.mem_resp_v_i(proc_mem_resp_v_li)
,.mem_resp_yumi_o(proc_mem_resp_yumi_lo)
);
bp2wb_convertor
#(.bp_params_p(bp_params_p))
bp2wb
(.clk_i(clk_i)
,.reset_i(reset_i)
,.mem_cmd_i(proc_mem_cmd_lo)
,.mem_cmd_v_i(proc_mem_cmd_ready_li & proc_mem_cmd_v_lo)
,.mem_cmd_ready_o(proc_mem_cmd_ready_li)
,.mem_resp_o(proc_mem_resp_li)
,.mem_resp_v_o(proc_mem_resp_v_li)
,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
,.dat_i(wbm_dat_i)
,.dat_o(wbm_dat_o)
,.ack_i(wbm_ack_i)
,.adr_o(wbm_adr_o)
,.stb_o(wbm_stb_o)
,.cyc_o(wbm_cyc_o)
,.sel_o(wbm_sel_o )
,.we_o(wbm_we_o)
,.cti_o(wbm_cti_o)
,.bte_o(wbm_bte_o )
// ,.rty_i(wbm_rty_i)
,.err_i(wbm_err_i)
);
assign proc_io_cmd_ready_li = 1;//TODO: make sure this is necessary
logic nbf_done_lo, cfg_done_lo;
if (load_nbf_p)
begin : nbf
bp_nonsynth_nbf_loader
#(.bp_params_p(bp_params_p))
nbf_loader
(.clk_i(clk_i)
,.reset_i(reset_i | ~cfg_done_lo)
,.lce_id_i(lce_id_width_p'('b10))
,.io_cmd_o(nbf_cmd_lo)
,.io_cmd_v_o(nbf_cmd_v_lo)
,.io_cmd_yumi_i(nbf_cmd_yumi_li)
,.io_resp_i(nbf_resp_li)
,.io_resp_v_i(nbf_resp_v_li)
,.io_resp_ready_o(nbf_resp_ready_lo)
,.done_o(nbf_done_lo)
);
end
else
begin : no_nbf
assign nbf_resp_ready_lo = 1'b1;
assign nbf_cmd_v_lo = '0;
assign nbf_cmd_lo = '0;
assign nbf_done_lo = 1'b1;
end
localparam cce_instr_ram_addr_width_lp = `BSG_SAFE_CLOG2(num_cce_instr_ram_els_p);
bp_cce_mmio_cfg_loader
#(.bp_params_p(bp_params_p)
,.inst_width_p($bits(bp_cce_inst_s))
,.inst_ram_addr_width_p(cce_instr_ram_addr_width_lp)
,.inst_ram_els_p(num_cce_instr_ram_els_p)
,.skip_ram_init_p(skip_init_p)
,.clear_freeze_p(!load_nbf_p)
,.cce_ucode_filename_p("/tmp/cce_ucode.mem")
)
cfg_loader
(.clk_i(clk_i)
,.reset_i(reset_i)
,.lce_id_i(lce_id_width_p'('b10))
,.io_cmd_o(cfg_cmd_lo)
,.io_cmd_v_o(cfg_cmd_v_lo)
,.io_cmd_yumi_i(cfg_cmd_yumi_li)
,.io_resp_i(cfg_resp_li)
,.io_resp_v_i(cfg_resp_v_li)
,.io_resp_ready_o(cfg_resp_ready_lo)
,.done_o(cfg_done_lo)
);
// CFG and NBF are mutex, so we can just use fixed arbitration here
always_comb
if (~cfg_done_lo)
begin
load_cmd_lo = cfg_cmd_lo;
load_cmd_v_lo = cfg_cmd_v_lo;
nbf_cmd_yumi_li = '0;
cfg_cmd_yumi_li = load_cmd_yumi_li;
load_resp_ready_lo = cfg_resp_ready_lo;
nbf_resp_li = '0;
nbf_resp_v_li = '0;
cfg_resp_li = load_resp_li;
cfg_resp_v_li = load_resp_v_li;
end
else
begin
load_cmd_lo = nbf_cmd_lo;
load_cmd_v_lo = nbf_cmd_v_lo;
nbf_cmd_yumi_li = load_cmd_yumi_li;
cfg_cmd_yumi_li = '0;
load_resp_ready_lo = nbf_resp_ready_lo;
nbf_resp_li = load_resp_li;
nbf_resp_v_li = load_resp_v_li;
cfg_resp_li = '0;
cfg_resp_v_li = '0;
end
/*bp_nonsynth_host
#(.bp_params_p(bp_params_p))
host
(.clk_i(clk_i)
,.reset_i(reset_i)
,.io_cmd_i(proc_io_cmd_lo)
,.io_cmd_v_i(proc_io_cmd_v_lo & proc_io_cmd_ready_li)
,.io_cmd_ready_o(proc_io_cmd_ready_li)
,.io_resp_o(proc_io_resp_li)
,.io_resp_v_o(proc_io_resp_v_li)
,.io_resp_yumi_i(proc_io_resp_yumi_lo)
,.program_finish_o(program_finish_lo)
);
*/
bind bp_be_top
bp_nonsynth_commit_tracer
#(.bp_params_p(bp_params_p))
commit_tracer
(.clk_i(clk_i & (ExampleBlackParrotSystem.cmt_trace_p == 1))
,.reset_i(reset_i)
,.freeze_i(be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.mhartid_i('0)
,.decode_i(be_calculator.reservation_n.decode)
,.commit_v_i(be_calculator.commit_pkt.instret)
,.commit_pc_i(be_calculator.commit_pkt.pc)
,.commit_instr_i(be_calculator.commit_pkt.instr)
,.rd_w_v_i(be_checker.scheduler.wb_pkt.rd_w_v)
,.rd_addr_i(be_checker.scheduler.wb_pkt.rd_addr)
,.rd_data_i(be_checker.scheduler.wb_pkt.rd_data)
);
/* if (num_core_p == 1)
begin : cosim
bind bp_be_top
bp_nonsynth_cosim
#(.bp_params_p(bp_params_p))
cosim
(.clk_i(clk_i)
,.reset_i(reset_i)
,.freeze_i(be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.en_i(ExampleBlackParrotSystem.cosim_p == 1)
,.cosim_instr_i(ExampleBlackParrotSystem.cosim_instr_p)
,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
// Want to pass config file as a parameter, but cannot in Verilator 4.025
// Parameter-resolved constants must not use dotted references
,.config_file_i(ExampleBlackParrotSystem.cosim_cfg_file_p)
,.decode_i(be_calculator.reservation_n.decode)
,.commit_v_i(be_calculator.commit_pkt.instret)
,.commit_pc_i(be_calculator.commit_pkt.pc)
,.commit_instr_i(be_calculator.commit_pkt.instr)
,.rd_w_v_i(be_checker.scheduler.wb_pkt.rd_w_v)
,.rd_addr_i(be_checker.scheduler.wb_pkt.rd_addr)
,.rd_data_i(be_checker.scheduler.wb_pkt.rd_data)
,.interrupt_v_i(be_mem.csr.trap_pkt_cast_o._interrupt)
,.cause_i(be_mem.csr.trap_pkt_cast_o.cause)
,.finish_o(ExampleBlackParrotSystem.cosim_finish_lo)
);
end
else
begin : no_cosim*/
assign cosim_finish_lo = '0;
// end
/*bind bp_be_top
bp_be_nonsynth_perf
#(.bp_params_p(bp_params_p))
perf
(.clk_i(clk_i)
,.reset_i(reset_i)
,.freeze_i(be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.warmup_instr_i(ExampleBlackParrotSystem.warmup_instr_p)
,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
,.commit_v_i(be_calculator.commit_pkt.instret)
,.program_finish_i(ExampleBlackParrotSystem.program_finish_lo | ExampleBlackParrotSystem.cosim_finish_lo)
);
*/
/* bind bp_be_top
bp_nonsynth_watchdog
#(.bp_params_p(bp_params_p)
,.timeout_cycles_p(100000)
,.heartbeat_instr_p(100000)
)
watchdog
(.clk_i(clk_i)
,.reset_i(reset_i)
,.freeze_i(be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
,.npc_i(be_checker.director.npc_r)
,.instret_i(be_calculator.commit_pkt.instret)
);
*/
/* bind bp_be_director
bp_be_nonsynth_npc_tracer
#(.bp_params_p(bp_params_p))
npc_tracer
(.clk_i(clk_i & (ExampleBlackParrotSystem.npc_trace_p == 1))
,.reset_i(reset_i)
,.freeze_i(be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
,.npc_w_v(npc_w_v)
,.npc_n(npc_n)
,.npc_r(npc_r)
,.expected_npc_o(expected_npc_o)
,.fe_cmd_i(fe_cmd)
,.fe_cmd_v(fe_cmd_v)
,.commit_pkt_i(commit_pkt)
);
*/
/* bind bp_be_dcache
bp_nonsynth_cache_tracer
#(.bp_params_p(bp_params_p)
,.assoc_p(dcache_assoc_p)
,.sets_p(dcache_sets_p)
,.block_width_p(dcache_block_width_p)
,.trace_file_p("dcache"))
dcache_tracer
(.clk_i(clk_i & (ExampleBlackParrotSystem.dcache_trace_p == 1))
,.reset_i(reset_i)
,.freeze_i(cfg_bus_cast_i.freeze)
,.mhartid_i(cfg_bus_cast_i.core_id)
,.v_tl_r(v_tl_r)
,.v_tv_r(v_tv_r)
,.addr_tv_r(paddr_tv_r)
,.lr_miss_tv(lr_miss_tv)
,.sc_op_tv_r(sc_op_tv_r)
,.sc_success(sc_success)
,.cache_req_v_o(cache_req_v_o)
,.cache_req_o(cache_req_o)
,.cache_req_metadata_o(cache_req_metadata_o)
,.cache_req_metadata_v_o(cache_req_metadata_v_o)
,.cache_req_complete_i(cache_req_complete_i)
,.v_o(v_o)
,.load_data(data_o)
,.cache_miss_o(dcache_miss_o)
,.wt_req(wt_req)
,.store_data(data_tv_r)
,.data_mem_pkt_v_i(data_mem_pkt_v_i)
,.data_mem_pkt_i(data_mem_pkt_i)
,.data_mem_pkt_yumi_o(data_mem_pkt_yumi_o)
,.tag_mem_pkt_v_i(tag_mem_pkt_v_i)
,.tag_mem_pkt_i(tag_mem_pkt_i)
,.tag_mem_pkt_yumi_o(tag_mem_pkt_yumi_o)
,.stat_mem_pkt_v_i(stat_mem_pkt_v_i)
,.stat_mem_pkt_i(stat_mem_pkt_i)
,.stat_mem_pkt_yumi_o(stat_mem_pkt_yumi_o)
);
*/
/* bind bp_fe_icache
bp_nonsynth_cache_tracer
#(.bp_params_p(bp_params_p)
,.assoc_p(icache_assoc_p)
,.sets_p(icache_sets_p)
,.block_width_p(icache_block_width_p)
,.trace_file_p("icache"))
icache_tracer
(.clk_i(clk_i & (ExampleBlackParrotSystem.icache_trace_p == 1))
,.reset_i(reset_i)
,.freeze_i(cfg_bus_cast_i.freeze)
,.mhartid_i(cfg_bus_cast_i.core_id)
,.v_tl_r(v_tl_r)
,.v_tv_r(v_tv_r)
,.addr_tv_r(addr_tv_r)
,.lr_miss_tv(1'b0)
,.sc_op_tv_r(1'b0)
,.sc_success(1'b0)
,.cache_req_v_o(cache_req_v_o)
,.cache_req_o(cache_req_o)
,.cache_req_metadata_o(cache_req_metadata_o)
,.cache_req_metadata_v_o(cache_req_metadata_v_o)
,.cache_req_complete_i(cache_req_complete_i)
,.v_o(data_v_o)
,.load_data(dword_width_p'(data_o))
,.cache_miss_o(miss_o)
,.wt_req()
,.store_data(dword_width_p'(0))
,.data_mem_pkt_v_i(data_mem_pkt_v_i)
,.data_mem_pkt_i(data_mem_pkt_i)
,.data_mem_pkt_yumi_o(data_mem_pkt_yumi_o)
,.tag_mem_pkt_v_i(tag_mem_pkt_v_i)
,.tag_mem_pkt_i(tag_mem_pkt_i)
,.tag_mem_pkt_yumi_o(tag_mem_pkt_yumi_o)
,.stat_mem_pkt_v_i(stat_mem_pkt_v_i)
,.stat_mem_pkt_i(stat_mem_pkt_i)
,.stat_mem_pkt_yumi_o(stat_mem_pkt_yumi_o)
);
*/
/* bind bp_core_minimal
bp_be_nonsynth_vm_tracer
#(.bp_params_p(bp_params_p))
vm_tracer
(.clk_i(clk_i & (ExampleBlackParrotSystem.vm_trace_p == 1))
,.reset_i(reset_i)
,.freeze_i(be.be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.mhartid_i(be.be_checker.scheduler.int_regfile.cfg_bus.core_id)
,.itlb_clear_i(fe.mem.itlb.flush_i)
,.itlb_fill_v_i(fe.mem.itlb.v_i & fe.mem.itlb.w_i)
,.itlb_vtag_i(fe.mem.itlb.vtag_i)
,.itlb_entry_i(fe.mem.itlb.entry_i)
,.dtlb_clear_i(be.be_mem.dtlb.flush_i)
,.dtlb_fill_v_i(be.be_mem.dtlb.v_i & be.be_mem.dtlb.w_i)
,.dtlb_vtag_i(be.be_mem.dtlb.vtag_i)
,.dtlb_entry_i(be.be_mem.dtlb.entry_i)
);
*/
bp_mem_nonsynth_tracer
#(.bp_params_p(bp_params_p))
bp_mem_tracer
(.clk_i(clk_i & (ExampleBlackParrotSystem.dram_trace_p == 1))
,.reset_i(reset_i)
,.mem_cmd_i(proc_mem_cmd_lo)
,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
,.mem_cmd_ready_i(proc_mem_cmd_ready_li)
,.mem_resp_i(proc_mem_resp_li)
,.mem_resp_v_i(proc_mem_resp_v_li)
,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
);
/* bind bp_core_minimal
bp_nonsynth_core_profiler
#(.bp_params_p(bp_params_p))
core_profiler
(.clk_i(clk_i & (ExampleBlackParrotSystem.core_profile_p == 1))
,.reset_i(reset_i)
,.freeze_i(be.be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.mhartid_i(be.be_checker.scheduler.int_regfile.cfg_bus.core_id)
,.fe_wait_stall(fe.pc_gen.is_wait)
,.fe_queue_stall(~fe.pc_gen.fe_queue_ready_i)
,.itlb_miss(fe.mem.itlb_miss_r)
,.icache_miss(~fe.mem.icache.vaddr_ready_o | fe.pc_gen.icache_miss)
,.icache_fence(fe.mem.icache.fencei_req)
,.branch_override(fe.pc_gen.ovr_taken & ~fe.pc_gen.ovr_ret)
,.ret_override(fe.pc_gen.ovr_ret)
,.fe_cmd(fe.pc_gen.fe_cmd_yumi_o & ~fe.pc_gen.attaboy_v)
,.mispredict(be.be_checker.director.npc_mismatch_v)
,.target(be.be_checker.director.isd_status.isd_pc)
,.dtlb_miss(be.be_mem.dtlb_miss_r)
,.dcache_miss(~be.be_mem.dcache.ready_o)
,.long_haz(be.be_checker.detector.long_haz_v)
,.exception(be.be_checker.director.trap_pkt.exception)
,.eret(be.be_checker.director.trap_pkt.eret)
,._interrupt(be.be_checker.director.trap_pkt._interrupt)
,.control_haz(be.be_checker.detector.control_haz_v)
,.data_haz(be.be_checker.detector.data_haz_v)
,.load_dep((be.be_checker.detector.dep_status_li[0].mem_iwb_v
| be.be_checker.detector.dep_status_li[1].mem_iwb_v
) & be.be_checker.detector.data_haz_v
)
,.mul_dep((be.be_checker.detector.dep_status_li[0].mul_iwb_v
| be.be_checker.detector.dep_status_li[1].mul_iwb_v
| be.be_checker.detector.dep_status_li[2].mul_iwb_v
) & be.be_checker.detector.data_haz_v
)
,.struct_haz(be.be_checker.detector.struct_haz_v)
,.reservation(be.be_calculator.reservation_n)
,.commit_pkt(be.be_calculator.commit_pkt)
,.trap_pkt(be.be_mem.csr.trap_pkt_o)
);
*/
/* bind bp_core_minimal
bp_nonsynth_pc_profiler
#(.bp_params_p(bp_params_p))
pc_profiler
(.clk_i(clk_i & (ExampleBlackParrotSystem.core_profile_p == 1))
,.reset_i(reset_i)
,.freeze_i(be.be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.mhartid_i(be.be_checker.scheduler.int_regfile.cfg_bus.core_id)
,.commit_pkt(be.be_calculator.commit_pkt)
,.program_finish_i(ExampleBlackParrotSystem.program_finish_lo)
);
*/
/* bind bp_be_director
bp_nonsynth_branch_profiler
#(.bp_params_p(bp_params_p))
pc_profiler
(.clk_i(clk_i & (ExampleBlackParrotSystem.core_profile_p == 1))
,.reset_i(reset_i)
,.freeze_i(cfg_bus_cast_i.freeze)
,.mhartid_i(cfg_bus_cast_i.core_id)
,.fe_cmd_o(fe_cmd_o)
,.fe_cmd_v_o(fe_cmd_v_o)
,.fe_cmd_ready_i(fe_cmd_ready_i)
,.commit_v_i(commit_pkt.instret)
,.program_finish_i(ExampleBlackParrotSystem.program_finish_lo)
);
*/
/* bp_nonsynth_if_verif
#(.bp_params_p(bp_params_p))
if_verif
();
*/
endmodule

6
litex/soc/cores/cpu/blackparrot/core.py
View File

@ -134,9 +134,9 @@ class BlackParrotRV64(CPU):
@staticmethod
def add_sources(platform, variant="standard"):
vdir = os.path.abspath(os.path.dirname(__file__))
bp_litex_dir = os.path.join(vdir,"bp_litex")
filename = os.path.join(bp_litex_dir, {
vdir = get_data_mod("cpu", "blackparrot").data_location
bp_litex = os.path.join(vdir, "bp_litex")
filename = os.path.join(bp_litex, {
"standard": "flist.fpga",
"sim" : "flist.verilator"
}[variant])

2
litex/soc/cores/cpu/blackparrot/setEnvironment.sh
View File

@ -2,7 +2,7 @@
## Set common environment variables
export LITEX=$(git rev-parse --show-toplevel)
export BP=$LITEX/../pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog
export BP_LITEX_DIR=$LITEX/litex/soc/cores/cpu/blackparrot/bp_litex
export BP_LITEX_DIR=$BP/bp_litex
#TODO: check if BP exists and warn user
export BP_COMMON_DIR=$BP/bp_common