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interconnect/wishbone/DownConverter: Avoid FSM and Idle cycle.

This commit is contained in:
Florent Kermarrec 2022-09-08 17:41:24 +02:00
parent e5de4b356a
commit b7e2d24f37
1 changed files with 24 additions and 26 deletions
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46
litex/soc/interconnect/wishbone.py
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@ -258,41 +258,39 @@ class DownConverter(Module):
# # # # # #
skip = Signal() skip = Signal()
counter = Signal(max=ratio) done = Signal()
count = Signal(max=ratio)
# Control Path # Control Path.
fsm = FSM(reset_state="IDLE") self.comb += [
fsm = ResetInserter()(fsm) done.eq(count == (ratio - 1)),
self.submodules.fsm = fsm
self.comb += fsm.reset.eq(~master.cyc)
fsm.act("IDLE",
NextValue(counter, 0),
If(master.stb & master.cyc,
NextState("CONVERT"),
)
)
fsm.act("CONVERT",
slave.adr.eq(Cat(counter, master.adr)),
Case(counter, {i: slave.sel.eq(master.sel[i*dw_to//8:]) for i in range(ratio)}),
If(master.stb & master.cyc, If(master.stb & master.cyc,
skip.eq(slave.sel == 0), skip.eq(slave.sel == 0),
slave.we.eq(master.we),
slave.cyc.eq(~skip), slave.cyc.eq(~skip),
slave.stb.eq(~skip), slave.stb.eq(~skip),
slave.we.eq(master.we),
If(slave.ack | skip, If(slave.ack | skip,
NextValue(counter, counter + 1), master.ack.eq(done)
If(counter == (ratio - 1),
master.ack.eq(1),
NextState("IDLE")
)
) )
) )
]
self.sync += [
If((slave.stb & slave.cyc & slave.ack) | skip,
count.eq(count + 1)
),
If(master.ack | ~master.cyc,
count.eq(0)
) )
]
# Write Datapath # Address.
self.comb += Case(counter, {i: slave.dat_w.eq(master.dat_w[i*dw_to:]) for i in range(ratio)}) self.comb += slave.adr.eq(Cat(count, master.adr))
# Read Datapath # Write Datapath.
self.comb += Case(count, {i: slave.dat_w.eq(master.dat_w[i*dw_to:]) for i in range(ratio)})
self.comb += Case(count, {i: slave.sel.eq(master.sel[i*dw_to//8:]) for i in range(ratio)}),
# Read Datapath.
dat_r = Signal(dw_from, reset_less=True) dat_r = Signal(dw_from, reset_less=True)
self.comb += master.dat_r.eq(Cat(dat_r[dw_to:], slave.dat_r)) self.comb += master.dat_r.eq(Cat(dat_r[dw_to:], slave.dat_r))
self.sync += If(slave.ack | skip, dat_r.eq(master.dat_r)) self.sync += If(slave.ack | skip, dat_r.eq(master.dat_r))