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core/cpu/CPUNone: set endianness to little.
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@ -26,6 +26,7 @@ class CPU(Module):
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class CPUNone(CPU):
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variants = ["standard"]
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data_width = 32
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endianness = "little"
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reset_address = 0x00000000
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io_regions = {0x00000000: 0x100000000} # origin, length
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periph_buses = []
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