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replace self._r_register by self._register in all CSR declaration

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This commit is contained in:
Florent Kermarrec 2015-02-27 10:36:09 +01:00
parent e4de5a0c9d
commit b817cf49b3
8 changed files with 93 additions and 93 deletions
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50
misoclib/framebuffer/phy.py
View file

@ -51,20 +51,20 @@ class _FIFO(Module):
# This assumes a 50MHz base clock
class _Clocking(Module, AutoCSR):
def __init__(self, pads_vga, pads_dvi):
self._r_cmd_data = CSRStorage(10)
self._r_send_cmd_data = CSR()
self._r_send_go = CSR()
self._r_status = CSRStatus(4)
self._cmd_data = CSRStorage(10)
self._send_cmd_data = CSR()
self._send_go = CSR()
self._status = CSRStatus(4)
self.clock_domains.cd_pix = ClockDomain(reset_less=True)
if pads_dvi is not None:
self._r_pll_reset = CSRStorage()
self._r_pll_adr = CSRStorage(5)
self._r_pll_dat_r = CSRStatus(16)
self._r_pll_dat_w = CSRStorage(16)
self._r_pll_read = CSR()
self._r_pll_write = CSR()
self._r_pll_drdy = CSRStatus()
self._pll_reset = CSRStorage()
self._pll_adr = CSRStorage(5)
self._pll_dat_r = CSRStatus(16)
self._pll_dat_w = CSRStorage(16)
self._pll_read = CSR()
self._pll_write = CSR()
self._pll_drdy = CSRStatus()
self.clock_domains.cd_pix2x = ClockDomain(reset_less=True)
self.clock_domains.cd_pix10x = ClockDomain(reset_less=True)
@ -92,9 +92,9 @@ class _Clocking(Module, AutoCSR):
self.comb += transmitting.eq(remaining_bits != 0)
sr = Signal(10)
self.sync += [
If(self._r_send_cmd_data.re,
If(self._send_cmd_data.re,
remaining_bits.eq(10),
sr.eq(self._r_cmd_data.storage)
sr.eq(self._cmd_data.storage)
).Elif(transmitting,
remaining_bits.eq(remaining_bits - 1),
sr.eq(sr[1:])
@ -102,21 +102,21 @@ class _Clocking(Module, AutoCSR):
]
self.comb += [
pix_progdata.eq(transmitting & sr[0]),
pix_progen.eq(transmitting | self._r_send_go.re)
pix_progen.eq(transmitting | self._send_go.re)
]
# enforce gap between commands
busy_counter = Signal(max=14)
busy = Signal()
self.comb += busy.eq(busy_counter != 0)
self.sync += If(self._r_send_cmd_data.re,
self.sync += If(self._send_cmd_data.re,
busy_counter.eq(13)
).Elif(busy,
busy_counter.eq(busy_counter - 1)
)
mult_locked = Signal()
self.comb += self._r_status.status.eq(Cat(busy, pix_progdone, pix_locked, mult_locked))
self.comb += self._status.status.eq(Cat(busy, pix_progdone, pix_locked, mult_locked))
# Clock multiplication and buffering
if pads_dvi is None:
@ -133,10 +133,10 @@ class _Clocking(Module, AutoCSR):
pll_clk2 = Signal()
locked_async = Signal()
pll_drdy = Signal()
self.sync += If(self._r_pll_read.re | self._r_pll_write.re,
self._r_pll_drdy.status.eq(0)
self.sync += If(self._pll_read.re | self._pll_write.re,
self._pll_drdy.status.eq(0)
).Elif(pll_drdy,
self._r_pll_drdy.status.eq(1)
self._pll_drdy.status.eq(1)
)
self.specials += [
Instance("PLL_ADV",
@ -151,13 +151,13 @@ class _Clocking(Module, AutoCSR):
o_CLKOUT0=pll_clk0, o_CLKOUT1=pll_clk1, o_CLKOUT2=pll_clk2,
o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbout,
o_LOCKED=pll_locked,
i_RST=~pix_locked | self._r_pll_reset.storage,
i_RST=~pix_locked | self._pll_reset.storage,
i_DADDR=self._r_pll_adr.storage,
o_DO=self._r_pll_dat_r.status,
i_DI=self._r_pll_dat_w.storage,
i_DEN=self._r_pll_read.re | self._r_pll_write.re,
i_DWE=self._r_pll_write.re,
i_DADDR=self._pll_adr.storage,
o_DO=self._pll_dat_r.status,
i_DI=self._pll_dat_w.storage,
i_DEN=self._pll_read.re | self._pll_write.re,
i_DWE=self._pll_write.re,
o_DRDY=pll_drdy,
i_DCLK=ClockSignal()),
Instance("BUFPLL", p_DIVIDE=5,

8
misoclib/gpio/__init__.py
View file

@ -4,13 +4,13 @@ from migen.bank.description import *
class GPIOIn(Module, AutoCSR):
def __init__(self, signal):
self._r_in = CSRStatus(flen(signal))
self.specials += MultiReg(signal, self._r_in.status)
self._in = CSRStatus(flen(signal))
self.specials += MultiReg(signal, self._in.status)
class GPIOOut(Module, AutoCSR):
def __init__(self, signal):
self._r_out = CSRStorage(flen(signal))
self.comb += signal.eq(self._r_out.storage)
self._out = CSRStorage(flen(signal))
self.comb += signal.eq(self._out.storage)
class GPIOInOut(Module):
def __init__(self, in_signal, out_signal):

16
misoclib/identifier/__init__.py
View file

@ -5,10 +5,10 @@ from misoclib.identifier import git
class Identifier(Module, AutoCSR):
def __init__(self, sysid, frequency, l2_size, revision=None):
self._r_sysid = CSRStatus(16)
self._r_revision = CSRStatus(32)
self._r_frequency = CSRStatus(32)
self._r_l2_size = CSRStatus(8)
self._sysid = CSRStatus(16)
self._revision = CSRStatus(32)
self._frequency = CSRStatus(32)
self._l2_size = CSRStatus(8)
###
@ -16,8 +16,8 @@ class Identifier(Module, AutoCSR):
revision = git.get_id()
self.comb += [
self._r_sysid.status.eq(sysid),
self._r_revision.status.eq(revision),
self._r_frequency.status.eq(frequency),
self._r_l2_size.status.eq(l2_size)
self._sysid.status.eq(sysid),
self._revision.status.eq(revision),
self._frequency.status.eq(frequency),
self._l2_size.status.eq(l2_size)
]

12
misoclib/liteeth/example_designs/targets/__init__.py
View file

@ -9,9 +9,9 @@ def get_id():
class Identifier(Module, AutoCSR):
def __init__(self, sysid, frequency, revision=None):
self._r_sysid = CSRStatus(16)
self._r_revision = CSRStatus(32)
self._r_frequency = CSRStatus(32)
self._sysid = CSRStatus(16)
self._revision = CSRStatus(32)
self._frequency = CSRStatus(32)
###
@ -19,8 +19,8 @@ class Identifier(Module, AutoCSR):
revision = get_id()
self.comb += [
self._r_sysid.status.eq(sysid),
self._r_revision.status.eq(revision),
self._r_frequency.status.eq(frequency),
self._sysid.status.eq(sysid),
self._revision.status.eq(revision),
self._frequency.status.eq(frequency),
]

32
misoclib/memtest/__init__.py
View file

@ -29,24 +29,24 @@ memtest_magic = 0x361f
class MemtestWriter(Module):
def __init__(self, lasmim):
self._r_magic = CSRStatus(16)
self._r_reset = CSR()
self._r_shoot = CSR()
self._magic = CSRStatus(16)
self._reset = CSR()
self._shoot = CSR()
self.submodules._dma = DMAWriteController(dma_lasmi.Writer(lasmim), MODE_EXTERNAL)
###
self.comb += self._r_magic.status.eq(memtest_magic)
self.comb += self._magic.status.eq(memtest_magic)
lfsr = LFSR(lasmim.dw)
self.submodules += lfsr
self.comb += lfsr.reset.eq(self._r_reset.re)
self.comb += lfsr.reset.eq(self._reset.re)
en = Signal()
en_counter = Signal(lasmim.aw)
self.comb += en.eq(en_counter != 0)
self.sync += [
If(self._r_shoot.re,
If(self._shoot.re,
en_counter.eq(self._dma.length)
).Elif(lfsr.ce,
en_counter.eq(en_counter - 1)
@ -54,37 +54,37 @@ class MemtestWriter(Module):
]
self.comb += [
self._dma.trigger.eq(self._r_shoot.re),
self._dma.trigger.eq(self._shoot.re),
self._dma.data.stb.eq(en),
lfsr.ce.eq(en & self._dma.data.ack),
self._dma.data.d.eq(lfsr.o)
]
def get_csrs(self):
return [self._r_magic, self._r_reset, self._r_shoot] + self._dma.get_csrs()
return [self._magic, self._reset, self._shoot] + self._dma.get_csrs()
class MemtestReader(Module):
def __init__(self, lasmim):
self._r_magic = CSRStatus(16)
self._r_reset = CSR()
self._r_error_count = CSRStatus(lasmim.aw)
self._magic = CSRStatus(16)
self._reset = CSR()
self._error_count = CSRStatus(lasmim.aw)
self.submodules._dma = DMAReadController(dma_lasmi.Reader(lasmim), MODE_SINGLE_SHOT)
###
self.comb += self._r_magic.status.eq(memtest_magic)
self.comb += self._magic.status.eq(memtest_magic)
lfsr = LFSR(lasmim.dw)
self.submodules += lfsr
self.comb += lfsr.reset.eq(self._r_reset.re)
self.comb += lfsr.reset.eq(self._reset.re)
self.comb += [
lfsr.ce.eq(self._dma.data.stb),
self._dma.data.ack.eq(1)
]
err_cnt = self._r_error_count.status
err_cnt = self._error_count.status
self.sync += [
If(self._r_reset.re,
If(self._reset.re,
err_cnt.eq(0)
).Elif(self._dma.data.stb,
If(self._dma.data.d != lfsr.o, err_cnt.eq(err_cnt + 1))
@ -92,7 +92,7 @@ class MemtestReader(Module):
]
def get_csrs(self):
return [self._r_magic, self._r_reset, self._r_error_count] + self._dma.get_csrs()
return [self._magic, self._reset, self._error_count] + self._dma.get_csrs()
class _LFSRTB(Module):
def __init__(self, *args, **kwargs):

12
misoclib/sdram/lasmicon/perf.py
View file

@ -3,9 +3,9 @@ from migen.bank.description import *
class Bandwidth(Module, AutoCSR):
def __init__(self, cmd, period_bits=24):
self._r_update = CSR()
self._r_nreads = CSRStatus(period_bits)
self._r_nwrites = CSRStatus(period_bits)
self._update = CSR()
self._nreads = CSRStatus(period_bits)
self._nwrites = CSRStatus(period_bits)
###
@ -37,8 +37,8 @@ class Bandwidth(Module, AutoCSR):
If(cmd_is_read, nreads.eq(nreads + 1)),
If(cmd_is_write, nwrites.eq(nwrites + 1)),
),
If(self._r_update.re,
self._r_nreads.status.eq(nreads_r),
self._r_nwrites.status.eq(nwrites_r)
If(self._update.re,
self._nreads.status.eq(nreads_r),
self._nwrites.status.eq(nwrites_r)
)
]

48
misoclib/sdram/phy/k7ddrphy.py
View file

@ -13,16 +13,16 @@ class K7DDRPHY(Module, AutoCSR):
d = flen(pads.dq)
nphases = 4
self._r_wlevel_en = CSRStorage()
self._r_wlevel_strobe = CSR()
self._r_dly_sel = CSRStorage(d//8)
self._r_rdly_dq_rst = CSR()
self._r_rdly_dq_inc = CSR()
self._r_rdly_dq_bitslip = CSR()
self._r_wdly_dq_rst = CSR()
self._r_wdly_dq_inc = CSR()
self._r_wdly_dqs_rst = CSR()
self._r_wdly_dqs_inc = CSR()
self._wlevel_en = CSRStorage()
self._wlevel_strobe = CSR()
self._dly_sel = CSRStorage(d//8)
self._rdly_dq_rst = CSR()
self._rdly_dq_inc = CSR()
self._rdly_dq_bitslip = CSR()
self._wdly_dq_rst = CSR()
self._wdly_dq_inc = CSR()
self._wdly_dqs_rst = CSR()
self._wdly_dqs_inc = CSR()
self.phy_settings = sdram.PhySettings(
memtype=memtype,
@ -118,8 +118,8 @@ class K7DDRPHY(Module, AutoCSR):
oe_dqs = Signal()
dqs_serdes_pattern = Signal(8)
self.comb += \
If(self._r_wlevel_en.storage,
If(self._r_wlevel_strobe.re,
If(self._wlevel_en.storage,
If(self._wlevel_strobe.re,
dqs_serdes_pattern.eq(0b00000001)
).Else(
dqs_serdes_pattern.eq(0b00000000)
@ -151,8 +151,8 @@ class K7DDRPHY(Module, AutoCSR):
p_PIPE_SEL="FALSE", p_ODELAY_TYPE="VARIABLE", p_ODELAY_VALUE=0,
i_C=ClockSignal(),
i_LD=self._r_dly_sel.storage[i] & self._r_wdly_dq_rst.re,
i_CE=self._r_dly_sel.storage[i] & self._r_wdly_dq_inc.re,
i_LD=self._dly_sel.storage[i] & self._wdly_dq_rst.re,
i_CE=self._dly_sel.storage[i] & self._wdly_dq_inc.re,
i_LDPIPEEN=0, i_INC=1,
o_ODATAIN=dm_o_nodelay, o_DATAOUT=pads.dm[i]
@ -183,8 +183,8 @@ class K7DDRPHY(Module, AutoCSR):
p_PIPE_SEL="FALSE", p_ODELAY_TYPE="VARIABLE", p_ODELAY_VALUE=6,
i_C=ClockSignal(),
i_LD=self._r_dly_sel.storage[i] & self._r_wdly_dqs_rst.re,
i_CE=self._r_dly_sel.storage[i] & self._r_wdly_dqs_inc.re,
i_LD=self._dly_sel.storage[i] & self._wdly_dqs_rst.re,
i_CE=self._dly_sel.storage[i] & self._wdly_dqs_inc.re,
i_LDPIPEEN=0, i_INC=1,
o_ODATAIN=dqs_nodelay, o_DATAOUT=dqs_delayed
@ -226,9 +226,9 @@ class K7DDRPHY(Module, AutoCSR):
i_DDLY=dq_i_delayed,
i_CE1=1,
i_RST=ResetSignal() | (self._r_dly_sel.storage[i//8] & self._r_wdly_dq_rst.re),
i_RST=ResetSignal() | (self._dly_sel.storage[i//8] & self._wdly_dq_rst.re),
i_CLK=ClockSignal("sys4x"), i_CLKB=~ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
i_BITSLIP=self._r_dly_sel.storage[i//8] & self._r_rdly_dq_bitslip.re,
i_BITSLIP=self._dly_sel.storage[i//8] & self._rdly_dq_bitslip.re,
o_Q8=self.dfi.phases[0].rddata[i], o_Q7=self.dfi.phases[0].rddata[d+i],
o_Q6=self.dfi.phases[1].rddata[i], o_Q5=self.dfi.phases[1].rddata[d+i],
o_Q4=self.dfi.phases[2].rddata[i], o_Q3=self.dfi.phases[2].rddata[d+i],
@ -240,8 +240,8 @@ class K7DDRPHY(Module, AutoCSR):
p_PIPE_SEL="FALSE", p_ODELAY_TYPE="VARIABLE", p_ODELAY_VALUE=0,
i_C=ClockSignal(),
i_LD=self._r_dly_sel.storage[i//8] & self._r_wdly_dq_rst.re,
i_CE=self._r_dly_sel.storage[i//8] & self._r_wdly_dq_inc.re,
i_LD=self._dly_sel.storage[i//8] & self._wdly_dq_rst.re,
i_CE=self._dly_sel.storage[i//8] & self._wdly_dq_inc.re,
i_LDPIPEEN=0, i_INC=1,
o_ODATAIN=dq_o_nodelay, o_DATAOUT=dq_o_delayed
@ -252,8 +252,8 @@ class K7DDRPHY(Module, AutoCSR):
p_PIPE_SEL="FALSE", p_IDELAY_TYPE="VARIABLE", p_IDELAY_VALUE=6,
i_C=ClockSignal(),
i_LD=self._r_dly_sel.storage[i//8] & self._r_rdly_dq_rst.re,
i_CE=self._r_dly_sel.storage[i//8] & self._r_rdly_dq_inc.re,
i_LD=self._dly_sel.storage[i//8] & self._rdly_dq_rst.re,
i_CE=self._dly_sel.storage[i//8] & self._rdly_dq_inc.re,
i_LDPIPEEN=0, i_INC=1,
i_IDATAIN=dq_i_nodelay, o_DATAOUT=dq_i_delayed
@ -275,7 +275,7 @@ class K7DDRPHY(Module, AutoCSR):
n_rddata_en = Signal()
self.sync += n_rddata_en.eq(rddata_en)
rddata_en = n_rddata_en
self.sync += [phase.rddata_valid.eq(rddata_en | self._r_wlevel_en.storage)
self.sync += [phase.rddata_valid.eq(rddata_en | self._wlevel_en.storage)
for phase in self.dfi.phases]
oe = Signal()
@ -284,7 +284,7 @@ class K7DDRPHY(Module, AutoCSR):
self.sync += last_wrdata_en.eq(Cat(wrphase.wrdata_en, last_wrdata_en[:3]))
self.comb += oe.eq(last_wrdata_en[1] | last_wrdata_en[2] | last_wrdata_en[3])
self.sync += \
If(self._r_wlevel_en.storage,
If(self._wlevel_en.storage,
oe_dqs.eq(1), oe_dq.eq(0)
).Else(
oe_dqs.eq(oe), oe_dq.eq(oe)

8
misoclib/uart/__init__.py
View file

@ -101,7 +101,7 @@ class UARTTX(Module):
class UART(Module, AutoCSR):
def __init__(self, pads, clk_freq, baud=115200):
self._r_rxtx = CSR(8)
self._rxtx = CSR(8)
self.submodules.ev = EventManager()
self.ev.tx = EventSourcePulse()
@ -118,14 +118,14 @@ class UART(Module, AutoCSR):
self.submodules.tx = UARTTX(pads, tuning_word)
self.sync += [
If(self._r_rxtx.re,
If(self._rxtx.re,
self.tx.sink.stb.eq(1),
self.tx.sink.d.eq(self._r_rxtx.r),
self.tx.sink.d.eq(self._rxtx.r),
).Elif(self.tx.sink.ack,
self.tx.sink.stb.eq(0)
),
If(self.rx.source.stb,
self._r_rxtx.w.eq(self.rx.source.d)
self._rxtx.w.eq(self.rx.source.d)
)
]
self.comb += [