Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

soc/cores/cpus: improve ident/align, uniformize between cpus

This commit is contained in:
Florent Kermarrec 2019-09-29 15:41:18 +02:00
parent 355072c285
commit b826c1705f
6 changed files with 332 additions and 335 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

93
litex/soc/cores/cpu/lm32/core.py
View File

@ -34,10 +34,10 @@ class LM32(CPU):
def __init__(self, platform, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
self.reset = Signal()
self.ibus = i = wishbone.Interface()
self.dbus = d = wishbone.Interface()
self.variant = variant
self.reset = Signal()
self.ibus = i = wishbone.Interface()
self.dbus = d = wishbone.Interface()
self.interrupt = Signal(32)
# # #
@ -50,31 +50,32 @@ class LM32(CPU):
i_interrupt=self.interrupt,
o_I_ADR_O=i_adr_o,
o_I_DAT_O=i.dat_w,
o_I_SEL_O=i.sel,
o_I_CYC_O=i.cyc,
o_I_STB_O=i.stb,
o_I_WE_O=i.we,
o_I_CTI_O=i.cti,
o_I_BTE_O=i.bte,
i_I_DAT_I=i.dat_r,
i_I_ACK_I=i.ack,
i_I_ERR_I=i.err,
i_I_RTY_I=0,
o_I_ADR_O = i_adr_o,
o_I_DAT_O = i.dat_w,
o_I_SEL_O = i.sel,
o_I_CYC_O = i.cyc,
o_I_STB_O = i.stb,
o_I_WE_O = i.we,
o_I_CTI_O = i.cti,
o_I_BTE_O = i.bte,
i_I_DAT_I = i.dat_r,
i_I_ACK_I = i.ack,
i_I_ERR_I = i.err,
i_I_RTY_I = 0,
o_D_ADR_O=d_adr_o,
o_D_DAT_O=d.dat_w,
o_D_SEL_O=d.sel,
o_D_CYC_O=d.cyc,
o_D_STB_O=d.stb,
o_D_WE_O=d.we,
o_D_CTI_O=d.cti,
o_D_BTE_O=d.bte,
i_D_DAT_I=d.dat_r,
i_D_ACK_I=d.ack,
i_D_ERR_I=d.err,
i_D_RTY_I=0)
o_D_ADR_O = d_adr_o,
o_D_DAT_O = d.dat_w,
o_D_SEL_O = d.sel,
o_D_CYC_O = d.cyc,
o_D_STB_O = d.stb,
o_D_WE_O = d.we,
o_D_CTI_O = d.cti,
o_D_BTE_O = d.bte,
i_D_DAT_I = d.dat_r,
i_D_ACK_I = d.ack,
i_D_ERR_I = d.err,
i_D_RTY_I = 0,
)
self.comb += [
self.ibus.adr.eq(i_adr_o[2:]),
@ -96,24 +97,24 @@ class LM32(CPU):
vdir = os.path.join(
os.path.abspath(os.path.dirname(__file__)), "verilog")
platform.add_sources(os.path.join(vdir, "submodule", "rtl"),
"lm32_cpu.v",
"lm32_instruction_unit.v",
"lm32_decoder.v",
"lm32_load_store_unit.v",
"lm32_adder.v",
"lm32_addsub.v",
"lm32_logic_op.v",
"lm32_shifter.v",
"lm32_multiplier.v",
"lm32_mc_arithmetic.v",
"lm32_interrupt.v",
"lm32_ram.v",
"lm32_dp_ram.v",
"lm32_icache.v",
"lm32_dcache.v",
"lm32_debug.v",
"lm32_itlb.v",
"lm32_dtlb.v")
"lm32_cpu.v",
"lm32_instruction_unit.v",
"lm32_decoder.v",
"lm32_load_store_unit.v",
"lm32_adder.v",
"lm32_addsub.v",
"lm32_logic_op.v",
"lm32_shifter.v",
"lm32_multiplier.v",
"lm32_mc_arithmetic.v",
"lm32_interrupt.v",
"lm32_ram.v",
"lm32_dp_ram.v",
"lm32_icache.v",
"lm32_dcache.v",
"lm32_debug.v",
"lm32_itlb.v",
"lm32_dtlb.v")
platform.add_verilog_include_path(os.path.join(vdir, "submodule", "rtl"))
if variant == "minimal":
platform.add_verilog_include_path(os.path.join(vdir, "config_minimal"))

52
litex/soc/cores/cpu/minerva/core.py
View File

@ -29,10 +29,10 @@ class Minerva(CPU):
def __init__(self, platform, variant="standard"):
assert variant is "standard", "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
self.reset = Signal()
self.ibus = wishbone.Interface()
self.dbus = wishbone.Interface()
self.variant = variant
self.reset = Signal()
self.ibus = wishbone.Interface()
self.dbus = wishbone.Interface()
self.interrupt = Signal(32)
# # #
@ -46,30 +46,30 @@ class Minerva(CPU):
i_external_interrupt=self.interrupt,
# ibus
o_ibus__stb=self.ibus.stb,
o_ibus__cyc=self.ibus.cyc,
o_ibus__cti=self.ibus.cti,
o_ibus__bte=self.ibus.bte,
o_ibus__we=self.ibus.we,
o_ibus__adr=self.ibus.adr,
o_ibus__dat_w=self.ibus.dat_w,
o_ibus__sel=self.ibus.sel,
i_ibus__ack=self.ibus.ack,
i_ibus__err=self.ibus.err,
i_ibus__dat_r=self.ibus.dat_r,
o_ibus__stb = self.ibus.stb,
o_ibus__cyc = self.ibus.cyc,
o_ibus__cti = self.ibus.cti,
o_ibus__bte = self.ibus.bte,
o_ibus__we = self.ibus.we,
o_ibus__adr = self.ibus.adr,
o_ibus__dat_w = self.ibus.dat_w,
o_ibus__sel = self.ibus.sel,
i_ibus__ack = self.ibus.ack,
i_ibus__err = self.ibus.err,
i_ibus__dat_r = self.ibus.dat_r,
# dbus
o_dbus__stb=self.dbus.stb,
o_dbus__cyc=self.dbus.cyc,
o_dbus__cti=self.dbus.cti,
o_dbus__bte=self.dbus.bte,
o_dbus__we=self.dbus.we,
o_dbus__adr=self.dbus.adr,
o_dbus__dat_w=self.dbus.dat_w,
o_dbus__sel=self.dbus.sel,
i_dbus__ack=self.dbus.ack,
i_dbus__err=self.dbus.err,
i_dbus__dat_r=self.dbus.dat_r,
o_dbus__stb = self.dbus.stb,
o_dbus__cyc = self.dbus.cyc,
o_dbus__cti = self.dbus.cti,
o_dbus__bte = self.dbus.bte,
o_dbus__we = self.dbus.we,
o_dbus__adr = self.dbus.adr,
o_dbus__dat_w = self.dbus.dat_w,
o_dbus__sel = self.dbus.sel,
i_dbus__ack = self.dbus.ack,
i_dbus__err = self.dbus.err,
i_dbus__dat_r = self.dbus.dat_r,
)
# add verilog sources

110
litex/soc/cores/cpu/mor1kx/core.py
View File

@ -63,10 +63,10 @@ class MOR1KX(CPU):
def __init__(self, platform, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
self.reset = Signal()
self.ibus = i = wishbone.Interface()
self.dbus = d = wishbone.Interface()
self.variant = variant
self.reset = Signal()
self.ibus = i = wishbone.Interface()
self.dbus = d = wishbone.Interface()
self.interrupt = Signal(32)
if variant == "linux":
@ -75,42 +75,44 @@ class MOR1KX(CPU):
# # #
cpu_args = dict(
p_FEATURE_INSTRUCTIONCACHE="ENABLED",
p_OPTION_ICACHE_BLOCK_WIDTH=4,
p_OPTION_ICACHE_SET_WIDTH=8,
p_OPTION_ICACHE_WAYS=1,
p_OPTION_ICACHE_LIMIT_WIDTH=31,
p_FEATURE_DATACACHE="ENABLED",
p_OPTION_DCACHE_BLOCK_WIDTH=4,
p_OPTION_DCACHE_SET_WIDTH=8,
p_OPTION_DCACHE_WAYS=1,
p_OPTION_DCACHE_LIMIT_WIDTH=31,
p_FEATURE_TIMER="NONE",
p_OPTION_PIC_TRIGGER="LEVEL",
p_FEATURE_SYSCALL="NONE",
p_FEATURE_TRAP="NONE",
p_FEATURE_RANGE="NONE",
p_FEATURE_OVERFLOW="NONE",
p_FEATURE_ADDC="ENABLED",
p_FEATURE_CMOV="ENABLED",
p_FEATURE_FFL1="ENABLED",
p_OPTION_CPU0="CAPPUCCINO",
p_IBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
p_DBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
p_FEATURE_INSTRUCTIONCACHE = "ENABLED",
p_OPTION_ICACHE_BLOCK_WIDTH = 4,
p_OPTION_ICACHE_SET_WIDTH = 8,
p_OPTION_ICACHE_WAYS = 1,
p_OPTION_ICACHE_LIMIT_WIDTH = 31,
p_FEATURE_DATACACHE = "ENABLED",
p_OPTION_DCACHE_BLOCK_WIDTH = 4,
p_OPTION_DCACHE_SET_WIDTH = 8,
p_OPTION_DCACHE_WAYS = 1,
p_OPTION_DCACHE_LIMIT_WIDTH = 31,
p_FEATURE_TIMER = "NONE",
p_OPTION_PIC_TRIGGER = "LEVEL",
p_FEATURE_SYSCALL = "NONE",
p_FEATURE_TRAP = "NONE",
p_FEATURE_RANGE = "NONE",
p_FEATURE_OVERFLOW = "NONE",
p_FEATURE_ADDC = "ENABLED",
p_FEATURE_CMOV = "ENABLED",
p_FEATURE_FFL1 = "ENABLED",
p_OPTION_CPU0 = "CAPPUCCINO",
p_IBUS_WB_TYPE = "B3_REGISTERED_FEEDBACK",
p_DBUS_WB_TYPE = "B3_REGISTERED_FEEDBACK",
)
if variant == "linux":
cpu_args.update(
# Linux needs the memory management units.
p_FEATURE_IMMU="ENABLED",
p_FEATURE_DMMU="ENABLED",
p_FEATURE_IMMU = "ENABLED",
p_FEATURE_DMMU = "ENABLED",
# FIXME: Currently we need the or1k timer when we should be
# using the litex timer.
p_FEATURE_TIMER="ENABLED",
p_FEATURE_TIMER = "ENABLED",
)
# FIXME: Check if these are needed?
use_defaults = (
"p_FEATURE_SYSCALL", "p_FEATURE_TRAP", "p_FEATURE_RANGE",
"p_FEATURE_SYSCALL",
"p_FEATURE_TRAP",
"p_FEATURE_RANGE",
"p_FEATURE_OVERFLOW",
)
for to_remove in use_defaults:
@ -126,31 +128,31 @@ class MOR1KX(CPU):
i_irq_i=self.interrupt,
o_iwbm_adr_o=i_adr_o,
o_iwbm_dat_o=i.dat_w,
o_iwbm_sel_o=i.sel,
o_iwbm_cyc_o=i.cyc,
o_iwbm_stb_o=i.stb,
o_iwbm_we_o=i.we,
o_iwbm_cti_o=i.cti,
o_iwbm_bte_o=i.bte,
i_iwbm_dat_i=i.dat_r,
i_iwbm_ack_i=i.ack,
i_iwbm_err_i=i.err,
i_iwbm_rty_i=0,
o_iwbm_adr_o = i_adr_o,
o_iwbm_dat_o = i.dat_w,
o_iwbm_sel_o = i.sel,
o_iwbm_cyc_o = i.cyc,
o_iwbm_stb_o = i.stb,
o_iwbm_we_o = i.we,
o_iwbm_cti_o = i.cti,
o_iwbm_bte_o = i.bte,
i_iwbm_dat_i = i.dat_r,
i_iwbm_ack_i = i.ack,
i_iwbm_err_i = i.err,
i_iwbm_rty_i = 0,
o_dwbm_adr_o=d_adr_o,
o_dwbm_dat_o=d.dat_w,
o_dwbm_sel_o=d.sel,
o_dwbm_cyc_o=d.cyc,
o_dwbm_stb_o=d.stb,
o_dwbm_we_o=d.we,
o_dwbm_cti_o=d.cti,
o_dwbm_bte_o=d.bte,
i_dwbm_dat_i=d.dat_r,
i_dwbm_ack_i=d.ack,
i_dwbm_err_i=d.err,
i_dwbm_rty_i=0
o_dwbm_adr_o = d_adr_o,
o_dwbm_dat_o = d.dat_w,
o_dwbm_sel_o = d.sel,
o_dwbm_cyc_o = d.cyc,
o_dwbm_stb_o = d.stb,
o_dwbm_we_o = d.we,
o_dwbm_cti_o = d.cti,
o_dwbm_bte_o = d.bte,
i_dwbm_dat_i = d.dat_r,
i_dwbm_ack_i = d.ack,
i_dwbm_err_i = d.err,
i_dwbm_rty_i = 0,
)
self.comb += [

120
litex/soc/cores/cpu/picorv32/core.py
View File

@ -55,19 +55,19 @@ class PicoRV32(CPU):
def __init__(self, platform, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
self.reset = Signal()
self.ibus = i = wishbone.Interface()
self.dbus = d = wishbone.Interface()
self.variant = variant
self.reset = Signal()
self.ibus = i = wishbone.Interface()
self.dbus = d = wishbone.Interface()
self.interrupt = Signal(32)
self.trap = Signal()
self.trap = Signal()
# # #
mem_valid = Signal()
mem_instr = Signal()
mem_ready = Signal()
mem_addr = Signal(32)
mem_addr = Signal(32)
mem_wdata = Signal(32)
mem_wstrb = Signal(4)
mem_rdata = Signal(32)
@ -75,80 +75,80 @@ class PicoRV32(CPU):
# PicoRV32 parameters. To create a new variant, modify this dictionary
# and change the desired parameters.
self.cpu_params = dict(
p_ENABLE_COUNTERS=1,
p_ENABLE_COUNTERS64=1,
p_ENABLE_COUNTERS = 1,
p_ENABLE_COUNTERS64 = 1,
# Changing REGS has no effect as on FPGAs, the registers are
# implemented using a register file stored in DPRAM.
p_ENABLE_REGS_16_31=1,
p_ENABLE_REGS_DUALPORT=1,
p_LATCHED_MEM_RDATA=0,
p_TWO_STAGE_SHIFT=1,
p_TWO_CYCLE_COMPARE=0,
p_TWO_CYCLE_ALU=0,
p_CATCH_MISALIGN=1,
p_CATCH_ILLINSN=1,
p_ENABLE_PCPI=0,
p_ENABLE_MUL=1,
p_ENABLE_DIV=1,
p_ENABLE_FAST_MUL=0,
p_ENABLE_IRQ=1,
p_ENABLE_IRQ_QREGS=1,
p_ENABLE_IRQ_TIMER=1,
p_ENABLE_TRACE=0,
p_MASKED_IRQ=0x00000000,
p_LATCHED_IRQ=0xffffffff,
p_STACKADDR=0xffffffff
p_ENABLE_REGS_16_31 = 1,
p_ENABLE_REGS_DUALPORT = 1,
p_LATCHED_MEM_RDATA = 0,
p_TWO_STAGE_SHIFT = 1,
p_TWO_CYCLE_COMPARE = 0,
p_TWO_CYCLE_ALU = 0,
p_CATCH_MISALIGN = 1,
p_CATCH_ILLINSN = 1,
p_ENABLE_PCPI = 0,
p_ENABLE_MUL = 1,
p_ENABLE_DIV = 1,
p_ENABLE_FAST_MUL = 0,
p_ENABLE_IRQ = 1,
p_ENABLE_IRQ_QREGS = 1,
p_ENABLE_IRQ_TIMER = 1,
p_ENABLE_TRACE = 0,
p_MASKED_IRQ = 0x00000000,
p_LATCHED_IRQ = 0xffffffff,
p_STACKADDR = 0xffffffff,
)
if variant == "minimal":
self.cpu_params.update(
p_ENABLE_COUNTER=0,
p_ENABLE_COUNTERS64=0,
p_TWO_STAGE_SHIFT=0,
p_CATCH_MISALIGN=0,
p_ENABLE_MUL=0,
p_ENABLE_DIV=0,
p_ENABLE_IRQ_TIMER=0
p_ENABLE_COUNTER = 0,
p_ENABLE_COUNTERS64 = 0,
p_TWO_STAGE_SHIFT = 0,
p_CATCH_MISALIGN = 0,
p_ENABLE_MUL = 0,
p_ENABLE_DIV = 0,
p_ENABLE_IRQ_TIMER = 0,
)
self.cpu_params.update(
# clock / reset
i_clk=ClockSignal(),
i_resetn=~(ResetSignal() | self.reset),
i_clk =ClockSignal(),
i_resetn =~(ResetSignal() | self.reset),
# trap
o_trap=self.trap,
# memory interface
o_mem_valid=mem_valid,
o_mem_instr=mem_instr,
i_mem_ready=mem_ready,
o_mem_valid = mem_valid,
o_mem_instr = mem_instr,
i_mem_ready = mem_ready,
o_mem_addr=mem_addr,
o_mem_wdata=mem_wdata,
o_mem_wstrb=mem_wstrb,
i_mem_rdata=mem_rdata,
o_mem_addr = mem_addr,
o_mem_wdata = mem_wdata,
o_mem_wstrb = mem_wstrb,
i_mem_rdata = mem_rdata,
# look ahead interface (not used)
o_mem_la_read=Signal(),
o_mem_la_write=Signal(),
o_mem_la_addr=Signal(32),
o_mem_la_wdata=Signal(32),
o_mem_la_wstrb=Signal(4),
o_mem_la_read = Signal(),
o_mem_la_write = Signal(),
o_mem_la_addr = Signal(32),
o_mem_la_wdata = Signal(32),
o_mem_la_wstrb = Signal(4),
# co-processor interface (not used)
o_pcpi_valid=Signal(),
o_pcpi_insn=Signal(32),
o_pcpi_rs1=Signal(32),
o_pcpi_rs2=Signal(32),
i_pcpi_wr=0,
i_pcpi_rd=0,
i_pcpi_wait=0,
i_pcpi_ready=0,
o_pcpi_valid = Signal(),
o_pcpi_insn = Signal(32),
o_pcpi_rs1 = Signal(32),
o_pcpi_rs2 = Signal(32),
i_pcpi_wr = 0,
i_pcpi_rd = 0,
i_pcpi_wait = 0,
i_pcpi_ready = 0,
# irq interface
i_irq=self.interrupt,
o_eoi=Signal(32)) # not used
i_irq = self.interrupt,
o_eoi = Signal(32)) # not used
# adapt memory interface to wishbone
self.comb += [
@ -188,8 +188,8 @@ class PicoRV32(CPU):
assert not hasattr(self, "reset_address")
self.reset_address = reset_address
self.cpu_params.update(
p_PROGADDR_RESET=reset_address,
p_PROGADDR_IRQ=reset_address + 0x00000010
p_PROGADDR_RESET = reset_address,
p_PROGADDR_IRQ = reset_address + 0x00000010
)
@staticmethod

194
litex/soc/cores/cpu/rocket/core.py
View File

@ -76,25 +76,21 @@ class RocketRV64(CPU):
def __init__(self, platform, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
self.reset = Signal()
self.variant = variant
self.reset = Signal()
self.interrupt = Signal(4)
self.mem_axi = mem_axi = axi.AXIInterface(
data_width=64, address_width=32, id_width=4)
self.mmio_axi = mmio_axi = axi.AXIInterface(
data_width=64, address_width=32, id_width=4)
self.mem_axi = mem_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4)
self.mmio_axi = mmio_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4)
self.mem_wb = mem_wb = wishbone.Interface(data_width=64, adr_width=29)
self.mem_wb = mem_wb = wishbone.Interface(data_width=64, adr_width=29)
self.mmio_wb = mmio_wb = wishbone.Interface(data_width=64, adr_width=29)
self.ibus = ibus = wishbone.Interface()
self.dbus = dbus = wishbone.Interface()
# # #
self.cpu_params = dict(
@ -103,116 +99,114 @@ class RocketRV64(CPU):
i_reset=ResetSignal() | self.reset,
# debug (ignored)
#o_debug_clockeddmi_dmi_req_ready=,
i_debug_clockeddmi_dmi_req_valid=0,
i_debug_clockeddmi_dmi_req_bits_addr=0,
i_debug_clockeddmi_dmi_req_bits_data=0,
i_debug_clockeddmi_dmi_req_bits_op=0,
i_debug_clockeddmi_dmi_resp_ready=0,
#o_debug_clockeddmi_dmi_resp_valid=,
#o_debug_clockeddmi_dmi_resp_bits_data=,
#o_debug_clockeddmi_dmi_resp_bits_resp=,
i_debug_clockeddmi_dmiClock=0,
i_debug_clockeddmi_dmiReset=0,
#o_debug_ndreset=,
#o_debug_dmactive=,
#o_debug_clockeddmi_dmi_req_ready = ,
i_debug_clockeddmi_dmi_req_valid = 0,
i_debug_clockeddmi_dmi_req_bits_addr = 0,
i_debug_clockeddmi_dmi_req_bits_data = 0,
i_debug_clockeddmi_dmi_req_bits_op = 0,
i_debug_clockeddmi_dmi_resp_ready = 0,
#o_debug_clockeddmi_dmi_resp_valid = ,
#o_debug_clockeddmi_dmi_resp_bits_data = ,
#o_debug_clockeddmi_dmi_resp_bits_resp = ,
i_debug_clockeddmi_dmiClock = 0,
i_debug_clockeddmi_dmiReset = 0,
#o_debug_ndreset = ,
#o_debug_dmactive = ,
# irq
i_interrupts=self.interrupt,
# axi memory (L1-cached)
i_mem_axi4_0_aw_ready=mem_axi.aw.ready,
o_mem_axi4_0_aw_valid=mem_axi.aw.valid,
o_mem_axi4_0_aw_bits_id=mem_axi.aw.id,
o_mem_axi4_0_aw_bits_addr=mem_axi.aw.addr,
o_mem_axi4_0_aw_bits_len=mem_axi.aw.len,
o_mem_axi4_0_aw_bits_size=mem_axi.aw.size,
o_mem_axi4_0_aw_bits_burst=mem_axi.aw.burst,
o_mem_axi4_0_aw_bits_lock=mem_axi.aw.lock,
o_mem_axi4_0_aw_bits_cache=mem_axi.aw.cache,
o_mem_axi4_0_aw_bits_prot=mem_axi.aw.prot,
o_mem_axi4_0_aw_bits_qos=mem_axi.aw.qos,
i_mem_axi4_0_aw_ready = mem_axi.aw.ready,
o_mem_axi4_0_aw_valid = mem_axi.aw.valid,
o_mem_axi4_0_aw_bits_id = mem_axi.aw.id,
o_mem_axi4_0_aw_bits_addr = mem_axi.aw.addr,
o_mem_axi4_0_aw_bits_len = mem_axi.aw.len,
o_mem_axi4_0_aw_bits_size = mem_axi.aw.size,
o_mem_axi4_0_aw_bits_burst = mem_axi.aw.burst,
o_mem_axi4_0_aw_bits_lock = mem_axi.aw.lock,
o_mem_axi4_0_aw_bits_cache = mem_axi.aw.cache,
o_mem_axi4_0_aw_bits_prot = mem_axi.aw.prot,
o_mem_axi4_0_aw_bits_qos = mem_axi.aw.qos,
i_mem_axi4_0_w_ready=mem_axi.w.ready,
o_mem_axi4_0_w_valid=mem_axi.w.valid,
o_mem_axi4_0_w_bits_data=mem_axi.w.data,
o_mem_axi4_0_w_bits_strb=mem_axi.w.strb,
o_mem_axi4_0_w_bits_last=mem_axi.w.last,
i_mem_axi4_0_w_ready = mem_axi.w.ready,
o_mem_axi4_0_w_valid = mem_axi.w.valid,
o_mem_axi4_0_w_bits_data = mem_axi.w.data,
o_mem_axi4_0_w_bits_strb = mem_axi.w.strb,
o_mem_axi4_0_w_bits_last = mem_axi.w.last,
o_mem_axi4_0_b_ready=mem_axi.b.ready,
i_mem_axi4_0_b_valid=mem_axi.b.valid,
i_mem_axi4_0_b_bits_id=mem_axi.b.id,
i_mem_axi4_0_b_bits_resp=mem_axi.b.resp,
o_mem_axi4_0_b_ready = mem_axi.b.ready,
i_mem_axi4_0_b_valid = mem_axi.b.valid,
i_mem_axi4_0_b_bits_id = mem_axi.b.id,
i_mem_axi4_0_b_bits_resp = mem_axi.b.resp,
i_mem_axi4_0_ar_ready=mem_axi.ar.ready,
o_mem_axi4_0_ar_valid=mem_axi.ar.valid,
o_mem_axi4_0_ar_bits_id=mem_axi.ar.id,
o_mem_axi4_0_ar_bits_addr=mem_axi.ar.addr,
o_mem_axi4_0_ar_bits_len=mem_axi.ar.len,
o_mem_axi4_0_ar_bits_size=mem_axi.ar.size,
o_mem_axi4_0_ar_bits_burst=mem_axi.ar.burst,
o_mem_axi4_0_ar_bits_lock=mem_axi.ar.lock,
o_mem_axi4_0_ar_bits_cache=mem_axi.ar.cache,
o_mem_axi4_0_ar_bits_prot=mem_axi.ar.prot,
o_mem_axi4_0_ar_bits_qos=mem_axi.ar.qos,
i_mem_axi4_0_ar_ready = mem_axi.ar.ready,
o_mem_axi4_0_ar_valid = mem_axi.ar.valid,
o_mem_axi4_0_ar_bits_id = mem_axi.ar.id,
o_mem_axi4_0_ar_bits_addr = mem_axi.ar.addr,
o_mem_axi4_0_ar_bits_len = mem_axi.ar.len,
o_mem_axi4_0_ar_bits_size = mem_axi.ar.size,
o_mem_axi4_0_ar_bits_burst = mem_axi.ar.burst,
o_mem_axi4_0_ar_bits_lock = mem_axi.ar.lock,
o_mem_axi4_0_ar_bits_cache = mem_axi.ar.cache,
o_mem_axi4_0_ar_bits_prot = mem_axi.ar.prot,
o_mem_axi4_0_ar_bits_qos = mem_axi.ar.qos,
o_mem_axi4_0_r_ready=mem_axi.r.ready,
i_mem_axi4_0_r_valid=mem_axi.r.valid,
i_mem_axi4_0_r_bits_id=mem_axi.r.id,
i_mem_axi4_0_r_bits_data=mem_axi.r.data,
i_mem_axi4_0_r_bits_resp=mem_axi.r.resp,
i_mem_axi4_0_r_bits_last=mem_axi.r.last,
o_mem_axi4_0_r_ready = mem_axi.r.ready,
i_mem_axi4_0_r_valid = mem_axi.r.valid,
i_mem_axi4_0_r_bits_id = mem_axi.r.id,
i_mem_axi4_0_r_bits_data = mem_axi.r.data,
i_mem_axi4_0_r_bits_resp = mem_axi.r.resp,
i_mem_axi4_0_r_bits_last = mem_axi.r.last,
# axi mmio (not cached)
i_mmio_axi4_0_aw_ready=mmio_axi.aw.ready,
o_mmio_axi4_0_aw_valid=mmio_axi.aw.valid,
o_mmio_axi4_0_aw_bits_id=mmio_axi.aw.id,
o_mmio_axi4_0_aw_bits_addr=mmio_axi.aw.addr,
o_mmio_axi4_0_aw_bits_len=mmio_axi.aw.len,
o_mmio_axi4_0_aw_bits_size=mmio_axi.aw.size,
o_mmio_axi4_0_aw_bits_burst=mmio_axi.aw.burst,
o_mmio_axi4_0_aw_bits_lock=mmio_axi.aw.lock,
o_mmio_axi4_0_aw_bits_cache=mmio_axi.aw.cache,
o_mmio_axi4_0_aw_bits_prot=mmio_axi.aw.prot,
o_mmio_axi4_0_aw_bits_qos=mmio_axi.aw.qos,
i_mmio_axi4_0_aw_ready = mmio_axi.aw.ready,
o_mmio_axi4_0_aw_valid = mmio_axi.aw.valid,
o_mmio_axi4_0_aw_bits_id = mmio_axi.aw.id,
o_mmio_axi4_0_aw_bits_addr = mmio_axi.aw.addr,
o_mmio_axi4_0_aw_bits_len = mmio_axi.aw.len,
o_mmio_axi4_0_aw_bits_size = mmio_axi.aw.size,
o_mmio_axi4_0_aw_bits_burst = mmio_axi.aw.burst,
o_mmio_axi4_0_aw_bits_lock = mmio_axi.aw.lock,
o_mmio_axi4_0_aw_bits_cache = mmio_axi.aw.cache,
o_mmio_axi4_0_aw_bits_prot = mmio_axi.aw.prot,
o_mmio_axi4_0_aw_bits_qos = mmio_axi.aw.qos,
i_mmio_axi4_0_w_ready=mmio_axi.w.ready,
o_mmio_axi4_0_w_valid=mmio_axi.w.valid,
o_mmio_axi4_0_w_bits_data=mmio_axi.w.data,
o_mmio_axi4_0_w_bits_strb=mmio_axi.w.strb,
o_mmio_axi4_0_w_bits_last=mmio_axi.w.last,
i_mmio_axi4_0_w_ready = mmio_axi.w.ready,
o_mmio_axi4_0_w_valid = mmio_axi.w.valid,
o_mmio_axi4_0_w_bits_data = mmio_axi.w.data,
o_mmio_axi4_0_w_bits_strb = mmio_axi.w.strb,
o_mmio_axi4_0_w_bits_last = mmio_axi.w.last,
o_mmio_axi4_0_b_ready=mmio_axi.b.ready,
i_mmio_axi4_0_b_valid=mmio_axi.b.valid,
i_mmio_axi4_0_b_bits_id=mmio_axi.b.id,
i_mmio_axi4_0_b_bits_resp=mmio_axi.b.resp,
o_mmio_axi4_0_b_ready = mmio_axi.b.ready,
i_mmio_axi4_0_b_valid = mmio_axi.b.valid,
i_mmio_axi4_0_b_bits_id = mmio_axi.b.id,
i_mmio_axi4_0_b_bits_resp = mmio_axi.b.resp,
i_mmio_axi4_0_ar_ready=mmio_axi.ar.ready,
o_mmio_axi4_0_ar_valid=mmio_axi.ar.valid,
o_mmio_axi4_0_ar_bits_id=mmio_axi.ar.id,
o_mmio_axi4_0_ar_bits_addr=mmio_axi.ar.addr,
o_mmio_axi4_0_ar_bits_len=mmio_axi.ar.len,
o_mmio_axi4_0_ar_bits_size=mmio_axi.ar.size,
o_mmio_axi4_0_ar_bits_burst=mmio_axi.ar.burst,
o_mmio_axi4_0_ar_bits_lock=mmio_axi.ar.lock,
o_mmio_axi4_0_ar_bits_cache=mmio_axi.ar.cache,
o_mmio_axi4_0_ar_bits_prot=mmio_axi.ar.prot,
o_mmio_axi4_0_ar_bits_qos=mmio_axi.ar.qos,
i_mmio_axi4_0_ar_ready = mmio_axi.ar.ready,
o_mmio_axi4_0_ar_valid = mmio_axi.ar.valid,
o_mmio_axi4_0_ar_bits_id = mmio_axi.ar.id,
o_mmio_axi4_0_ar_bits_addr = mmio_axi.ar.addr,
o_mmio_axi4_0_ar_bits_len = mmio_axi.ar.len,
o_mmio_axi4_0_ar_bits_size = mmio_axi.ar.size,
o_mmio_axi4_0_ar_bits_burst = mmio_axi.ar.burst,
o_mmio_axi4_0_ar_bits_lock = mmio_axi.ar.lock,
o_mmio_axi4_0_ar_bits_cache = mmio_axi.ar.cache,
o_mmio_axi4_0_ar_bits_prot = mmio_axi.ar.prot,
o_mmio_axi4_0_ar_bits_qos = mmio_axi.ar.qos,
o_mmio_axi4_0_r_ready=mmio_axi.r.ready,
i_mmio_axi4_0_r_valid=mmio_axi.r.valid,
i_mmio_axi4_0_r_bits_id=mmio_axi.r.id,
i_mmio_axi4_0_r_bits_data=mmio_axi.r.data,
i_mmio_axi4_0_r_bits_resp=mmio_axi.r.resp,
i_mmio_axi4_0_r_bits_last=mmio_axi.r.last,
o_mmio_axi4_0_r_ready = mmio_axi.r.ready,
i_mmio_axi4_0_r_valid = mmio_axi.r.valid,
i_mmio_axi4_0_r_bits_id = mmio_axi.r.id,
i_mmio_axi4_0_r_bits_data = mmio_axi.r.data,
i_mmio_axi4_0_r_bits_resp = mmio_axi.r.resp,
i_mmio_axi4_0_r_bits_last = mmio_axi.r.last,
)
# adapt axi interfaces to wishbone
mem_a2w = ResetInserter()(
axi.AXI2Wishbone(mem_axi, mem_wb, base_address=0))
mmio_a2w = ResetInserter()(
axi.AXI2Wishbone(mmio_axi, mmio_wb, base_address=0))
mem_a2w = ResetInserter()(axi.AXI2Wishbone(mem_axi, mem_wb, base_address=0))
mmio_a2w = ResetInserter()(axi.AXI2Wishbone(mmio_axi, mmio_wb, base_address=0))
# NOTE: AXI2Wishbone FSMs must be reset with the CPU!
self.comb += [
mem_a2w.reset.eq(ResetSignal() | self.reset),

98
litex/soc/cores/cpu/vexriscv/core.py
View File

@ -57,8 +57,8 @@ GCC_FLAGS = {
class VexRiscvTimer(Module, AutoCSR):
def __init__(self):
self._latch = CSR()
self._time = CSRStatus(64)
self._latch = CSR()
self._time = CSRStatus(64)
self._time_cmp = CSRStorage(64, reset=2**64-1)
self.interrupt = Signal()
@ -89,46 +89,46 @@ class VexRiscv(CPU, AutoCSR):
def __init__(self, platform, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
self.platform = platform
self.variant = variant
self.external_variant = None
self.reset = Signal()
self.ibus = ibus = wishbone.Interface()
self.dbus = dbus = wishbone.Interface()
self.reset = Signal()
self.ibus = ibus = wishbone.Interface()
self.dbus = dbus = wishbone.Interface()
self.interrupt = Signal(32)
self.cpu_params = dict(
i_clk=ClockSignal(),
i_reset=ResetSignal() | self.reset,
i_externalInterruptArray=self.interrupt,
i_timerInterrupt=0,
i_softwareInterrupt=0,
i_externalInterruptArray = self.interrupt,
i_timerInterrupt = 0,
i_softwareInterrupt = 0,
o_iBusWishbone_ADR=ibus.adr,
o_iBusWishbone_DAT_MOSI=ibus.dat_w,
o_iBusWishbone_SEL=ibus.sel,
o_iBusWishbone_CYC=ibus.cyc,
o_iBusWishbone_STB=ibus.stb,
o_iBusWishbone_WE=ibus.we,
o_iBusWishbone_CTI=ibus.cti,
o_iBusWishbone_BTE=ibus.bte,
i_iBusWishbone_DAT_MISO=ibus.dat_r,
i_iBusWishbone_ACK=ibus.ack,
i_iBusWishbone_ERR=ibus.err,
o_iBusWishbone_ADR = ibus.adr,
o_iBusWishbone_DAT_MOSI = ibus.dat_w,
o_iBusWishbone_SEL = ibus.sel,
o_iBusWishbone_CYC = ibus.cyc,
o_iBusWishbone_STB = ibus.stb,
o_iBusWishbone_WE = ibus.we,
o_iBusWishbone_CTI = ibus.cti,
o_iBusWishbone_BTE = ibus.bte,
i_iBusWishbone_DAT_MISO = ibus.dat_r,
i_iBusWishbone_ACK = ibus.ack,
i_iBusWishbone_ERR = ibus.err,
o_dBusWishbone_ADR=dbus.adr,
o_dBusWishbone_DAT_MOSI=dbus.dat_w,
o_dBusWishbone_SEL=dbus.sel,
o_dBusWishbone_CYC=dbus.cyc,
o_dBusWishbone_STB=dbus.stb,
o_dBusWishbone_WE=dbus.we,
o_dBusWishbone_CTI=dbus.cti,
o_dBusWishbone_BTE=dbus.bte,
i_dBusWishbone_DAT_MISO=dbus.dat_r,
i_dBusWishbone_ACK=dbus.ack,
i_dBusWishbone_ERR=dbus.err)
o_dBusWishbone_ADR = dbus.adr,
o_dBusWishbone_DAT_MOSI = dbus.dat_w,
o_dBusWishbone_SEL = dbus.sel,
o_dBusWishbone_CYC = dbus.cyc,
o_dBusWishbone_STB = dbus.stb,
o_dBusWishbone_WE = dbus.we,
o_dBusWishbone_CTI = dbus.cti,
o_dBusWishbone_BTE = dbus.bte,
i_dBusWishbone_DAT_MISO = dbus.dat_r,
i_dBusWishbone_ACK = dbus.ack,
i_dBusWishbone_ERR = dbus.err
)
if "linux" in variant:
self.add_timer()
@ -142,18 +142,18 @@ class VexRiscv(CPU, AutoCSR):
ibus_err = Signal()
dbus_err = Signal()
self.i_cmd_valid = Signal()
self.i_cmd_payload_wr = Signal()
self.i_cmd_valid = Signal()
self.i_cmd_payload_wr = Signal()
self.i_cmd_payload_address = Signal(8)
self.i_cmd_payload_data = Signal(32)
self.o_cmd_ready = Signal()
self.o_rsp_data = Signal(32)
self.o_resetOut = Signal()
self.i_cmd_payload_data = Signal(32)
self.o_cmd_ready = Signal()
self.o_rsp_data = Signal(32)
self.o_resetOut = Signal()
reset_debug_logic = Signal()
self.transfer_complete = Signal()
self.transfer_in_progress = Signal()
self.transfer_complete = Signal()
self.transfer_in_progress = Signal()
self.transfer_wait_for_ack = Signal()
self.debug_bus = wishbone.Interface()
@ -212,14 +212,14 @@ class VexRiscv(CPU, AutoCSR):
i_reset=ResetSignal() | self.reset | debug_reset,
i_iBusWishbone_ERR=self.ibus.err | ibus_err,
i_dBusWishbone_ERR=self.dbus.err | dbus_err,
i_debugReset=ResetSignal(),
i_debug_bus_cmd_valid=self.i_cmd_valid,
i_debug_bus_cmd_payload_wr=self.i_cmd_payload_wr,
i_debug_bus_cmd_payload_address=self.i_cmd_payload_address,
i_debug_bus_cmd_payload_data=self.i_cmd_payload_data,
o_debug_bus_cmd_ready=self.o_cmd_ready,
o_debug_bus_rsp_data=self.o_rsp_data,
o_debug_resetOut=self.o_resetOut
i_debugReset = ResetSignal(),
i_debug_bus_cmd_valid = self.i_cmd_valid,
i_debug_bus_cmd_payload_wr = self.i_cmd_payload_wr,
i_debug_bus_cmd_payload_address = self.i_cmd_payload_address,
i_debug_bus_cmd_payload_data = self.i_cmd_payload_data,
o_debug_bus_cmd_ready = self.o_cmd_ready,
o_debug_bus_rsp_data = self.o_rsp_data,
o_debug_resetOut = self.o_resetOut
)
def set_reset_address(self, reset_address):