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build/sim/core/veril.cpp: Flush trace file on finish, fix issue with empty .fst dumps with short simulations.

This commit is contained in:
Florent Kermarrec 2024-09-25 08:53:57 +02:00
parent c95a6e041c
commit b86d76baed
2 changed files with 2 additions and 0 deletions
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1
CHANGES.md
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@ -11,6 +11,7 @@
- soc/cores/clock/colognechip : Fixed and reworked locked signal handling. - soc/cores/clock/colognechip : Fixed and reworked locked signal handling.
- litesdcard : Fixed data_i sampling (https://github.com/enjoy-digital/litesdcard/pull/34). - litesdcard : Fixed data_i sampling (https://github.com/enjoy-digital/litesdcard/pull/34).
- litespi/mmap : Fixed dummy bits (https://github.com/litex-hub/litespi/pull/71). - litespi/mmap : Fixed dummy bits (https://github.com/litex-hub/litespi/pull/71).
- sim/verilator : Fixed .fst empty dump with short simulation.
[> Added [> Added
-------- --------

1
litex/build/sim/core/veril.cpp
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@ -78,6 +78,7 @@ extern "C" void litex_sim_tracer_dump()
extern "C" int litex_sim_got_finish() extern "C" int litex_sim_got_finish()
{ {
tfp->flush();
return Verilated::gotFinish(); return Verilated::gotFinish();
} }