soc/cores/clock/lattice_nx.py: added clk contraints for OSCA output
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@ -32,7 +32,7 @@ class NXOSCA(LiteXModule):
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clk_hf_freq_range = (1.76, 450e6)
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clk_hf_freq = 450e6
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def __init__(self):
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def __init__(self, platform=None):
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self.logger = logging.getLogger("NXOSCA")
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self.logger.info("Creating NXOSCA.")
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@ -40,6 +40,7 @@ class NXOSCA(LiteXModule):
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self.hfsdc_clk_out = {}
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self.lf_clk_out = None
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self.params = {}
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self.platform = platform
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def create_hf_clk(self, cd, freq, margin=.05):
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"""450 - 1.7 Mhz Clk"""
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@ -86,21 +87,29 @@ class NXOSCA(LiteXModule):
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def do_finalize(self):
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if self.hf_clk_out:
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divisor = self.compute_divisor(self.hf_clk_out[1], self.hf_clk_out[2])
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clk_freq = self.hf_clk_out[1]
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divisor = self.compute_divisor(clk_freq, self.hf_clk_out[2])
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self.params["i_HFOUTEN"] = 0b1
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self.params["p_HF_CLK_DIV"] = divisor
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self.params["o_HFCLKOUT"] = self.hf_clk_out[0]
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self.params["p_HF_OSC_EN"] = "ENABLED"
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if self.platform:
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self.platform.add_platform_command("create_clock -period {} -name OSCA_HFCLKOUT [get_pins OSCA.OSCA_inst/HFCLKOUT]".format(str(1e9/clk_freq)))
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if self.hfsdc_clk_out:
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divisor = self.compute_divisor(self.hfsdc_clk_out[1], self.hfsdc_clk_out[2])
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clk_freq = self.hf_clk_out[1]
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divisor = self.compute_divisor(clk_freq, self.hfsdc_clk_out[2])
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self.params["i_HFSDSCEN"] = 0b1
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self.params["p_HF_SED_SEC_DIV"] = divisor
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self.params["o_HFSDCOUT"] = self.hfsdc_clk_out[0]
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if self.platform:
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self.platform.add_platform_command("create_clock -period {} -name OSCA_HFSDCOUT [get_pins OSCA.OSCA_inst/HFSDCOUT]".format(str(1e9/clk_freq)))
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if self.lf_clk_out is not None:
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self.params["o_LFCLKOUT"] = self.lf_clk_out[0]
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self.params["p_LF_OUTPUT_EN"] = "ENABLED"
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if self.platform:
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self.platform.add_platform_command("create_clock -period {} -name OSCA_LF_OUTPUT_EN [get_pins OSCA.OSCA_inst/LF_OUTPUT_EN]".format(str(1e9/128e3)))
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self.specials += Instance("OSCA", **self.params)
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