cores/code_8b10b: set reset_less to True on datapath signals.
Reset is only required on control signals.
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@ -153,8 +153,8 @@ class SingleEncoder(Module):
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# stage 1: 5b/6b and 3b/4b encoding
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code5b = self.d[:5]
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code6b = Signal(6)
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code6b_unbalanced = Signal()
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code6b = Signal(6, reset_less=True)
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code6b_unbalanced = Signal(reset_less=True)
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code6b_flip = Signal()
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self.sync += [
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If(self.k & (code5b == 28),
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@ -169,8 +169,8 @@ class SingleEncoder(Module):
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]
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code3b = self.d[5:]
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code4b = Signal(4)
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code4b_unbalanced = Signal()
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code4b = Signal(4, reset_less=True)
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code4b_unbalanced = Signal(reset_less=True)
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code4b_flip = Signal()
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self.sync += [
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code4b.eq(Array(table_3b4b)[code3b]),
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@ -182,8 +182,8 @@ class SingleEncoder(Module):
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)
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]
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alt7_rd0 = Signal() # if disparity is -1, use alternative D.x.7
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alt7_rd1 = Signal() # if disparity is +1, use alternative D.x.7
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alt7_rd0 = Signal(reset_less=True) # if disparity is -1, use alternative D.x.7
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alt7_rd1 = Signal(reset_less=True) # if disparity is +1, use alternative D.x.7
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self.sync += [
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alt7_rd0.eq(0),
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alt7_rd1.eq(0),
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@ -242,7 +242,7 @@ class Encoder(Module):
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def __init__(self, nwords=1, lsb_first=False):
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self.d = [Signal(8) for _ in range(nwords)]
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self.k = [Signal() for _ in range(nwords)]
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self.output = [Signal(10) for _ in range(nwords)]
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self.output = [Signal(10, reset_less=True) for _ in range(nwords)]
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self.disparity = [Signal() for _ in range(nwords)]
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# # #
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@ -260,6 +260,7 @@ class Encoder(Module):
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encoder.d.eq(d),
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encoder.k.eq(k)
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]
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output.reset_less = True
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self.sync += [
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output.eq(encoder.output),
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disparity.eq(encoder.disp_out)
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@ -285,7 +286,7 @@ class Decoder(Module):
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code6b = input_msb_first[4:]
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code5b = Signal(5)
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code4b = input_msb_first[:4]
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code3b = Signal(3)
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code3b = Signal(3, reset_less=True)
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mem_6b5b = Memory(5, len(table_6b5b), init=table_6b5b)
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port_6b5b = mem_6b5b.get_port()
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@ -317,6 +318,6 @@ class Decoder(Module):
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# Basic invalid symbols detection: check that we have 4,5 or 6 ones in the symbol. This does
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# not report all invalid symbols but still allow detecting issues with the link.
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ones = Signal(4)
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ones = Signal(4, reset_less=True)
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self.sync += ones.eq(reduce(add, [self.input[i] for i in range(10)]))
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self.comb += self.invalid.eq((ones != 4) & (ones != 5) & (ones != 6))
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