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Merge pull request #549 from antmicro/mglb/fix-vivado-yosys 

build/xilinx: do not assume build name is "top"
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enjoy-digital 2020-06-01 19:58:01 +02:00 committed by GitHub
parent 5cc7a98845 a4e8323485
commit b98a919226
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1 changed files with 2 additions and 2 deletions
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litex/build/xilinx/common.py
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@ -374,7 +374,7 @@ def _run_yosys(device, sources, vincpaths, build_name):
ys_contents += "read_{}{} {}\n".format(language, incflags, filename) ys_contents += "read_{}{} {}\n".format(language, incflags, filename)
ys_contents += """\ ys_contents += """\
hierarchy -top top hierarchy -top {build_name}
# FIXME: Are these needed? # FIXME: Are these needed?
# proc; memory; opt; fsm; opt # proc; memory; opt; fsm; opt
@ -401,7 +401,7 @@ log
select -list a:async_reg=true select -list a:async_reg=true
setattr -set keep 1 a:async_reg=true setattr -set keep 1 a:async_reg=true
synth_xilinx -top top synth_xilinx -top {build_name}
write_edif -pvector bra -attrprop {build_name}.edif write_edif -pvector bra -attrprop {build_name}.edif
""".format(build_name=build_name) """.format(build_name=build_name)