transport: merge cmd and data Sink/Source, will be easier
This commit is contained in:
Florent Kermarrec
parent
9ae703efbe
commit
b9a9e075fd
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@ -48,7 +48,7 @@ def link_layout(dw):
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]
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return EndpointDescription(layout, packetized=True)
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def transport_cmd_tx_layout():
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def transport_tx_layout(dw):
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layout = [
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("type", 8),
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("pm_port", 4),
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@ -66,10 +66,11 @@ def transport_cmd_tx_layout():
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("dma_buffer_id", 64),
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("dma_buffer_offset", 32),
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("dma_transfer_count", 32),
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("data", dw)
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]
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return EndpointDescription(layout, packetized=False)
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return EndpointDescription(layout, packetized=True)
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def transport_cmd_rx_layout():
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def transport_rx_layout(dw):
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layout = [
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("type", 8),
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("pm_port", 4),
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@ -85,12 +86,7 @@ def transport_cmd_rx_layout():
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("transfer_count", 16),
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("dma_buffer_id", 64),
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("dma_buffer_offset", 32),
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("dma_transfer_count", 32)
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]
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return EndpointDescription(layout, packetized=False)
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def transport_data_layout(dw):
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layout = [
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("d", dw)
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("dma_transfer_count", 32),
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("data", dw)
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]
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return EndpointDescription(layout, packetized=True)
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@ -21,32 +21,35 @@ class TB(Module):
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def gen_simulation(self, selfp):
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for i in range(100):
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yield
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selfp.transport.tx.cmd.stb = 1
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selfp.transport.tx.cmd.type = fis_types["REG_H2D"]
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selfp.transport.tx.cmd.lba = 0x0123456789
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selfp.transport.sink.stb = 1
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selfp.transport.sink.sop = 1
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selfp.transport.sink.eop = 1
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selfp.transport.sink.type = fis_types["REG_H2D"]
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selfp.transport.sink.lba = 0x0123456789
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yield
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while selfp.transport.tx.cmd.ack == 0:
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while selfp.transport.sink.ack == 0:
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yield
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selfp.transport.tx.cmd.stb = 1
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selfp.transport.tx.cmd.type = fis_types["DMA_SETUP"]
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selfp.transport.tx.cmd.dma_buffer_id = 0x0123456789ABCDEF
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selfp.transport.sink.stb = 1
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selfp.transport.sink.sop = 1
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selfp.transport.sink.eop = 1
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selfp.transport.sink.type = fis_types["DMA_SETUP"]
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selfp.transport.sink.dma_buffer_id = 0x0123456789ABCDEF
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yield
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while selfp.transport.tx.cmd.ack == 0:
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yield
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selfp.transport.tx.cmd.stb = 1
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selfp.transport.tx.cmd.type = fis_types["DATA"]
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while selfp.transport.sink.ack == 0:
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yield
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for i in range(32):
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selfp.transport.tx.data.stb = 1
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#selfp.transport.tx.data.sop = (i==0)
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selfp.transport.tx.data.eop = (i==31)
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selfp.transport.tx.data.d = i
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if selfp.transport.tx.data.ack == 1:
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selfp.transport.sink.stb = 1
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selfp.transport.sink.sop = (i==0)
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selfp.transport.sink.eop = (i==31)
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selfp.transport.sink.type = fis_types["DATA"]
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selfp.transport.sink.data = i
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if selfp.transport.sink.ack == 1:
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yield
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else:
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while selfp.transport.tx.data.ack == 0:
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while selfp.transport.sink.ack == 0:
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yield
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selfp.transport.tx.cmd.stb = 0
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selfp.transport.sink.stb = 0
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=512, vcd_name="my.vcd", keep_files=True)
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@ -20,8 +20,7 @@ def _encode_cmd(obj, layout, signal):
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class SATATransportLayerTX(Module):
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def __init__(self, link):
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self.cmd = cmd = Sink(transport_cmd_tx_layout())
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self.data = data = Sink(transport_data_layout(32))
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self.sink = sink = Sink(transport_tx_layout(32))
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###
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@ -38,17 +37,16 @@ class SATATransportLayerTX(Module):
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cmd_send = Signal()
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data_send = Signal()
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cmd_done = Signal()
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data_done = Signal()
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def test_type(name):
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return cmd.type == fis_types[name]
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return sink.type == fis_types[name]
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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clr_cnt.eq(1),
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If(cmd.stb,
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If(sink.stb & sink.sop,
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If(test_type("REG_H2D"),
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NextState("SEND_REG_H2D_CMD")
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).Elif(test_type("DMA_SETUP"),
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@ -56,29 +54,32 @@ class SATATransportLayerTX(Module):
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).Elif(test_type("DATA"),
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NextState("SEND_DATA_CMD")
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).Else(
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# XXX: Generate error to command layer?
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cmd.ack.eq(1)
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sink.ack.eq(1)
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)
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).Else(
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sink.ack.eq(1)
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)
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)
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fsm.act("SEND_REG_H2D_CMD",
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_encode_cmd(self.cmd, fis_reg_h2d_layout, encoded_cmd),
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_encode_cmd(sink, fis_reg_h2d_layout, encoded_cmd),
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cmd_len.eq(fis_reg_h2d_cmd_len),
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cmd_send.eq(1),
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If(cmd_done,
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NextState("ACK")
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sink.ack.eq(1),
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NextState("IDLE")
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)
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)
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fsm.act("SEND_DMA_SETUP_CMD",
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_encode_cmd(self.cmd, fis_dma_setup_layout, encoded_cmd),
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_encode_cmd(sink, fis_dma_setup_layout, encoded_cmd),
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cmd_len.eq(fis_dma_setup_cmd_len),
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cmd_send.eq(1),
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If(cmd_done,
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NextState("ACK")
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sink.ack.eq(1),
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NextState("IDLE")
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)
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)
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fsm.act("SEND_DATA_CMD",
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_encode_cmd(self.cmd, fis_data_layout, encoded_cmd),
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_encode_cmd(sink, fis_data_layout, encoded_cmd),
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cmd_len.eq(fis_data_cmd_len),
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cmd_with_data.eq(1),
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cmd_send.eq(1),
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@ -88,14 +89,12 @@ class SATATransportLayerTX(Module):
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)
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fsm.act("SEND_DATA",
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data_send.eq(1),
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If(data_done,
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NextState("ACK")
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)
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)
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fsm.act("ACK",
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cmd.ack.eq(1),
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sink.ack.eq(link.sink.ack),
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If(sink.stb & sink.eop & sink.ack,
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NextState("IDLE")
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)
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)
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cmd_cases = {}
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for i in range(cmd_ndwords):
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@ -110,12 +109,10 @@ class SATATransportLayerTX(Module):
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inc_cnt.eq(link.sink.ack),
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cmd_done.eq(cnt==cmd_len)
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).Elif(data_send,
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link.sink.stb.eq(data.stb),
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link.sink.stb.eq(sink.stb),
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link.sink.sop.eq(0),
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link.sink.eop.eq(data.eop),
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link.sink.d.eq(data.d),
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data.ack.eq(link.sink.ack),
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data_done.eq(data.eop & data.ack)
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link.sink.eop.eq(sink.eop),
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link.sink.d.eq(sink.data),
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)
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self.sync += \
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@ -141,8 +138,7 @@ def _decode_cmd(signal, layout, obj):
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class SATATransportLayerRX(Module):
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def __init__(self, link):
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self.cmd = cmd = Source(transport_cmd_rx_layout())
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self.data = data = Source(transport_data_layout(32))
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self.source = source = Source(transport_rx_layout(32))
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###
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@ -195,9 +191,9 @@ class SATATransportLayerRX(Module):
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)
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)
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fsm.act("PRESENT_REG_D2H_CMD",
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cmd.stb.eq(1),
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_decode_cmd(encoded_cmd, fis_reg_d2h_layout ,cmd),
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If(cmd.ack,
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source.stb.eq(1),
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_decode_cmd(encoded_cmd, fis_reg_d2h_layout, source),
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If(source.ack,
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NextState("IDLE")
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)
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)
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@ -209,9 +205,9 @@ class SATATransportLayerRX(Module):
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)
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)
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fsm.act("PRESENT_DMA_ACTIVATE_D2H_CMD",
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cmd.stb.eq(1),
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_decode_cmd(encoded_cmd, fis_dma_activate_d2h_layout ,cmd),
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If(cmd.ack,
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source.stb.eq(1),
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_decode_cmd(encoded_cmd, fis_dma_activate_d2h_layout, source),
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If(source.ack,
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NextState("IDLE")
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)
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)
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@ -223,9 +219,9 @@ class SATATransportLayerRX(Module):
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)
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)
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fsm.act("PRESENT_DMA_SETUP_CMD",
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cmd.stb.eq(1),
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_decode_cmd(encoded_cmd, fis_pio_setup_d2h_layout ,cmd),
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If(cmd.ack,
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source.stb.eq(1),
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_decode_cmd(encoded_cmd, fis_pio_setup_d2h_layout, source),
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If(source.ack,
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NextState("IDLE")
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)
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)
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@ -233,19 +229,17 @@ class SATATransportLayerRX(Module):
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cmd_len.eq(fis_data_cmd_len),
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cmd_receive.eq(1),
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If(cmd_done,
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NextState("RECEIVE_DATA")
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NextState("PRESENT_DATA")
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)
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)
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fsm.act("RECEIVE_DATA",
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fsm.act("PRESENT_DATA",
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data_receive.eq(1),
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If(data_done,
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NextState("PRESENT_DATA_CMD")
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)
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)
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fsm.act("PRESENT_DATA_CMD",
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cmd.stb.eq(1),
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_decode_cmd(encoded_cmd, fis_data_layout ,cmd),
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If(cmd.ack,
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source.stb.eq(link.source.stb),
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_decode_cmd(encoded_cmd, fis_data_layout, source),
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source.sop.eq(0), # XXX
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source.eop.eq(link.source.eop),
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source.d.eq(link.source.d),
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If(source.stb & source.eop & source.ack,
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NextState("IDLE")
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)
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)
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@ -257,9 +251,9 @@ class SATATransportLayerRX(Module):
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)
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)
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fsm.act("PRESENT_PIO_SETUP_D2H_CMD",
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cmd.stb.eq(1),
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_decode_cmd(encoded_cmd, fis_pio_setup_d2h_layout ,cmd),
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If(cmd.ack,
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source.stb.eq(1),
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_decode_cmd(encoded_cmd, fis_pio_setup_d2h_layout, source),
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If(source.ack,
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NextState("IDLE")
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)
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)
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@ -278,18 +272,10 @@ class SATATransportLayerRX(Module):
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)
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)
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self.comb += cmd_done.eq(cnt==cmd_len)
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self.comb += \
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If(data_receive,
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data.stb.eq(link.source.stb),
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data.sop.eq(0), # XXX
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data.eop.eq(link.source.eop),
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data.d.eq(link.source.d),
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data_done.eq(link.source.stb & link.source.eop)
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)
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self.comb += link.source.ack.eq(cmd_receive | (data_receive & data.ack))
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self.comb += link.source.ack.eq(cmd_receive | (data_receive & source.ack))
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class SATATransportLayer(Module):
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def __init__(self, link):
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self.submodules.tx = SATATransportLayerTX(link)
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self.submodules.rx = SATATransportLayerRX(link)
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self.sink, self.source = self.tx.sink, self.rx.source
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