integration/soc/sata: fix sys_clk_freq vs sata_freq_clk check.

2020-10-29 10:50:10 +01:00 · 2020-10-29 10:50:10 +01:00 · b9ceed0f74
parent e7ad705359
commit b9ceed0f74
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@ -1440,7 +1440,7 @@ class LiteXSoC(SoC):
            "gen3": 300e6,
        }
        sata_clk_freq = sata_clk_freqs[phy.gen]
-        assert self.clk_freq >= sata_clk_freq
+        assert self.clk_freq >= sata_clk_freq/2 # FIXME: /2 for 16-bit data-width, add support for 32-bit.

        # Core
        self.submodules.sata_core = LiteSATACore(phy)