integration/soc: set use_rom when cpu_reset_address is defined in a rom region.
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@ -68,7 +68,7 @@ class BaseSoC(SoCCore):
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kwargs["integrated_sram_size"] = 0
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kwargs["integrated_rom_size"] = 0
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# Set CPU variant / reset address
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# Set CPU variant / reset address
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kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
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# CRG --------------------------------------------------------------------------------------
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@ -774,7 +774,6 @@ class SoC(Module):
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self.csr.update_alignment(self.cpu.data_width)
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# Add Bus Masters/CSR/IRQs
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if not isinstance(self.cpu, cpu.CPUNone):
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self.cpu.use_rom = (reset_address is None)
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if reset_address is None:
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reset_address = self.mem_map["rom"]
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self.cpu.set_reset_address(reset_address)
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@ -854,20 +853,20 @@ class SoC(Module):
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# SoC CPU Check ----------------------------------------------------------------------------
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if not isinstance(self.cpu, cpu.CPUNone):
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for name in ["sram"] + ["rom"] if self.cpu.use_rom else []:
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if name not in self.bus.regions.keys():
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self.logger.error("CPU needs {} Region to be {} as Bus or Linker Region.".format(
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colorer(name),
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colorer("defined", color="red")))
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self.logger.error(self.bus)
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raise
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if "sram" not in self.bus.regions.keys():
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self.logger.error("CPU needs {} Region to be {} as Bus or Linker Region.".format(
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colorer("sram"),
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colorer("defined", color="red")))
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self.logger.error(self.bus)
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raise
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cpu_reset_address_valid = False
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for container in self.bus.regions.values():
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for name, container in self.bus.regions.items():
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if self.bus.check_region_is_in(
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region = SoCRegion(origin=self.cpu.reset_address, size=self.bus.data_width//8),
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container = container):
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cpu_reset_address_valid = True
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if name == "rom":
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self.cpu.use_rom = True
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if not cpu_reset_address_valid:
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self.logger.error("CPU needs {} to be in a {} Region.".format(
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colorer("reset address 0x{:08x}".format(self.cpu.reset_address)),
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