Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

mila: fixes when used without RLE

Browse source
This commit is contained in:
Florent Kermarrec 2014-10-06 12:30:06 +02:00
parent f72f11f7b4
commit ba30a01830
2 changed files with 8 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
miscope/host/drivers.py
View file

@ -23,7 +23,7 @@ class MiIoDriver():
return self.miio_i.read()
class MiLaDriver():
def __init__(self, regs, name, config_csv=None, use_rle=True):
def __init__(self, regs, name, config_csv=None, use_rle=False):
self.regs = regs
self.name = name
self.use_rle = use_rle
@ -33,7 +33,7 @@ class MiLaDriver():
self.get_layout()
self.build_mila()
self.dat = Dat(self.width)
def get_config(self):
csv_reader = csv.reader(open(self.config_csv), delimiter=',', quotechar='#')
for item in csv_reader:
@ -86,14 +86,14 @@ class MiLaDriver():
rm.write(rising_mask)
fm.write(falling_mask)
bm.write(both_mask)
def prog_sum(self, equation):
datas = gen_truth_table(equation)
for adr, dat in enumerate(datas):
self.mila_trigger_sum_prog_adr.write(adr)
self.mila_trigger_sum_prog_dat.write(dat)
self.mila_trigger_sum_prog_we.write(1)
def config_rle(self, v):
self.mila_rle_enable.write(v)
@ -120,8 +120,9 @@ class MiLaDriver():
self.dat.append(self.mila_recorder_read_dat.read())
empty = self.mila_recorder_read_empty.read()
self.mila_recorder_read_en.write(1)
if self.use_rle:
self.dat = self.dat.decode_rle()
if self.with_rle:
if self.use_rle:
self.dat = self.dat.decode_rle()
return self.dat
def export(self, export_fn=None):

3
miscope/mila.py
View file

@ -36,7 +36,6 @@ class MiLa(Module, AutoCSR):
self.submodules.trigger = trigger = Trigger(width, ports)
self.submodules.recorder = recorder = Recorder(width, depth)
self.comb += [
sink.connect(trigger.sink),
trigger.source.connect(recorder.trig_sink)
@ -49,7 +48,7 @@ class MiLa(Module, AutoCSR):
rle.source.connect(recorder.dat_sink)
]
else:
sink.connect(recorder.dat_sink)
self.comb += sink.connect(recorder.dat_sink)
def export(self, design, layout, filename):
ret, ns = verilog.convert(design, return_ns=True)