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mila: fixes when used without RLE

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This commit is contained in:
Florent Kermarrec 2014-10-06 12:30:06 +02:00
parent f72f11f7b4
commit ba30a01830
2 changed files with 8 additions and 8 deletions
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3
miscope/host/drivers.py
View file

@ -23,7 +23,7 @@ class MiIoDriver():
return self.miio_i.read() return self.miio_i.read()
class MiLaDriver(): class MiLaDriver():
def __init__(self, regs, name, config_csv=None, use_rle=True): def __init__(self, regs, name, config_csv=None, use_rle=False):
self.regs = regs self.regs = regs
self.name = name self.name = name
self.use_rle = use_rle self.use_rle = use_rle
@ -120,6 +120,7 @@ class MiLaDriver():
self.dat.append(self.mila_recorder_read_dat.read()) self.dat.append(self.mila_recorder_read_dat.read())
empty = self.mila_recorder_read_empty.read() empty = self.mila_recorder_read_empty.read()
self.mila_recorder_read_en.write(1) self.mila_recorder_read_en.write(1)
if self.with_rle:
if self.use_rle: if self.use_rle:
self.dat = self.dat.decode_rle() self.dat = self.dat.decode_rle()
return self.dat return self.dat

3
miscope/mila.py
View file

@ -36,7 +36,6 @@ class MiLa(Module, AutoCSR):
self.submodules.trigger = trigger = Trigger(width, ports) self.submodules.trigger = trigger = Trigger(width, ports)
self.submodules.recorder = recorder = Recorder(width, depth) self.submodules.recorder = recorder = Recorder(width, depth)
self.comb += [ self.comb += [
sink.connect(trigger.sink), sink.connect(trigger.sink),
trigger.source.connect(recorder.trig_sink) trigger.source.connect(recorder.trig_sink)
@ -49,7 +48,7 @@ class MiLa(Module, AutoCSR):
rle.source.connect(recorder.dat_sink) rle.source.connect(recorder.dat_sink)
] ]
else: else:
sink.connect(recorder.dat_sink) self.comb += sink.connect(recorder.dat_sink)
def export(self, design, layout, filename): def export(self, design, layout, filename):
ret, ns = verilog.convert(design, return_ns=True) ret, ns = verilog.convert(design, return_ns=True)