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corelogic: operator tree
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parent
8a394f9159
commit
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3 changed files with 40 additions and 28 deletions
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@ -1,5 +1,6 @@
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from migen.fhdl.structure import *
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from migen.fhdl.structure import *
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from migen.corelogic import roundrobin, multimux
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from migen.corelogic import roundrobin
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from migen.corelogic.misc import multimux, optree
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from migen.bus.simple import Simple, get_sig_name
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from migen.bus.simple import Simple, get_sig_name
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_desc = [
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_desc = [
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@ -37,7 +38,7 @@ class Arbiter:
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m2s_names = [get_sig_name(x, False) for x in _desc if x[0]]
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m2s_names = [get_sig_name(x, False) for x in _desc if x[0]]
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m2s_masters = [[getattr(m, name) for name in m2s_names] for m in self.masters]
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m2s_masters = [[getattr(m, name) for name in m2s_names] for m in self.masters]
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m2s_target = [getattr(self.target, name) for name in m2s_names]
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m2s_target = [getattr(self.target, name) for name in m2s_names]
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comb += multimux.multimux(self.rr.grant, m2s_masters, m2s_target)
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comb += multimux(self.rr.grant, m2s_masters, m2s_target)
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# connect slave->master signals
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# connect slave->master signals
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s2m_names = [get_sig_name(x, False) for x in _desc if not x[0]]
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s2m_names = [get_sig_name(x, False) for x in _desc if not x[0]]
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@ -115,21 +116,12 @@ class Decoder:
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i += 1
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i += 1
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# generate master ack (resp. err) by ORing all slave acks (resp. errs)
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# generate master ack (resp. err) by ORing all slave acks (resp. errs)
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ackv = Constant(0)
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comb.append(self.master.ack_i.eq(optree('|', [slave[1].ack_o for slave in self.slaves])))
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errv = Constant(0)
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comb.append(self.master.err_i.eq(optree('|', [slave[1].err_o for slave in self.slaves])))
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for slave in self.slaves:
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ackv = ackv | slave[1].ack_o
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errv = errv | slave[1].err_o
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comb.append(self.master.ack_i.eq(ackv))
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comb.append(self.master.err_i.eq(errv))
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# mux (1-hot) slave data return
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# mux (1-hot) slave data return
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i = 0
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masked = [Replicate(slave_sel_r[i], self.master.dat_i.bv.width) & self.slaves[i][1].dat_o for i in range(len(self.slaves))]
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datav = Constant(0, self.master.dat_i.bv)
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comb.append(self.master.dat_i.eq(optree('|', masked)))
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for slave in self.slaves:
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datav = datav | (Replicate(slave_sel_r[i], self.master.dat_i.bv.width) & slave[1].dat_o)
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i += 1
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comb.append(self.master.dat_i.eq(datav))
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return Fragment(comb, sync)
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return Fragment(comb, sync)
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33
migen/corelogic/misc.py
Normal file
33
migen/corelogic/misc.py
Normal file
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@ -0,0 +1,33 @@
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from migen.fhdl.structure import *
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from migen.fhdl.structure import _Operator
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def multimux(sel, inputs, output):
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n = len(inputs)
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i = 0
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comb = []
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for osig in output:
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choices = [x[i] for x in inputs]
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cases = [[Constant(j, sel.bv), osig.eq(choices[j])] for j in range(n)]
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cases[n-1][0] = Default()
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comb.append(Case(sel, *cases))
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i += 1
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return comb
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def optree(op, operands, lb=None, ub=None, default=None):
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if lb is None:
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lb = 0
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if ub is None:
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ub = len(operands)
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l = ub - lb
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if l == 0:
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if default is None:
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raise AttributeError
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else:
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return default
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elif l == 1:
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return operands[lb]
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else:
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s = lb + l//2
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return _Operator(op,
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[optree(op, operands, lb, s, default),
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optree(op, operands, s, ub, default)])
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@ -1,13 +0,0 @@
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from migen.fhdl.structure import *
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def multimux(sel, inputs, output):
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n = len(inputs)
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i = 0
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comb = []
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for osig in output:
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choices = [x[i] for x in inputs]
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cases = [[Constant(j, sel.bv), osig.eq(choices[j])] for j in range(n)]
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cases[n-1][0] = Default()
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comb.append(Case(sel, *cases))
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i += 1
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return comb
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