sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy
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@ -21,8 +21,9 @@ from migen.fhdl.std import *
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from misoclib.mem import sdram
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class SDRAMModule:
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def __init__(self, clk_freq, geom_settings, timing_settings):
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def __init__(self, clk_freq, memtype, geom_settings, timing_settings):
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self.clk_freq = clk_freq
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self.memtype = memtype
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self.geom_settings = sdram.GeomSettings(
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databits=geom_settings["nbits"],
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bankbits=log2_int(geom_settings["nbanks"]),
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@ -62,7 +63,7 @@ class IS42S16160(SDRAMModule):
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"tRFC": 70
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}
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def __init__(self, clk_freq):
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SDRAMModule.__init__(self, clk_freq, self.geom_settings,
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SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
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self.timing_settings)
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class MT48LC4M16(SDRAMModule):
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@ -81,7 +82,7 @@ class MT48LC4M16(SDRAMModule):
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"tRFC": 66
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}
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def __init__(self, clk_freq):
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SDRAMModule.__init__(self, clk_freq, self.geom_settings,
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SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
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self.timing_settings)
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class AS4C16M16(SDRAMModule):
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@ -101,7 +102,7 @@ class AS4C16M16(SDRAMModule):
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"tRFC": 60
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}
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def __init__(self, clk_freq):
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SDRAMModule.__init__(self, clk_freq, self.geom_settings,
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SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
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self.timing_settings)
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# DDR
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@ -121,7 +122,7 @@ class MT46V32M16(SDRAMModule):
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"tRFC": 70
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}
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def __init__(self, clk_freq):
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SDRAMModule.__init__(self, clk_freq, self.geom_settings,
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SDRAMModule.__init__(self, clk_freq, "DDR", self.geom_settings,
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self.timing_settings)
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# LPDDR
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@ -141,7 +142,7 @@ class MT46H32M16(SDRAMModule):
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"tRFC": 72
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}
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def __init__(self, clk_freq):
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SDRAMModule.__init__(self, clk_freq, self.geom_settings,
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SDRAMModule.__init__(self, clk_freq, "LPDDR", self.geom_settings,
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self.timing_settings)
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# DDR2
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@ -161,7 +162,7 @@ class MT47H128M8(SDRAMModule):
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"tRFC": 127.5
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}
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def __init__(self, clk_freq):
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SDRAMModule.__init__(self, clk_freq, self.geom_settings,
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SDRAMModule.__init__(self, clk_freq, "DDR2", self.geom_settings,
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self.timing_settings)
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# DDR3
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@ -181,5 +182,5 @@ class MT8JTF12864(SDRAMModule):
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"tRFC": 70
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}
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def __init__(self, clk_freq):
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SDRAMModule.__init__(self, clk_freq, self.geom_settings,
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SDRAMModule.__init__(self, clk_freq, "DDR3", self.geom_settings,
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self.timing_settings)
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@ -29,13 +29,13 @@ from misoclib.mem.sdram.phy.dfi import *
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from misoclib.mem import sdram
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class GENSDRPHY(Module):
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def __init__(self, pads):
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def __init__(self, pads, module):
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addressbits = flen(pads.a)
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bankbits = flen(pads.ba)
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databits = flen(pads.dq)
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self.settings = sdram.PhySettings(
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memtype="SDR",
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memtype=module.memtype,
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dfi_databits=databits,
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nphases=1,
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rdphase=0,
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@ -46,6 +46,7 @@ class GENSDRPHY(Module):
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read_latency=4,
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write_latency=0
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)
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self.module = module
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self.dfi = Interface(addressbits, bankbits, databits)
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@ -7,7 +7,7 @@ from misoclib.mem.sdram.phy.dfi import *
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from misoclib.mem import sdram
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class K7DDRPHY(Module, AutoCSR):
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def __init__(self, pads, memtype):
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def __init__(self, pads, module):
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addressbits = flen(pads.a)
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bankbits = flen(pads.ba)
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databits = flen(pads.dq)
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@ -25,7 +25,7 @@ class K7DDRPHY(Module, AutoCSR):
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self._wdly_dqs_inc = CSR()
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self.settings = sdram.PhySettings(
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memtype=memtype,
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memtype=module.memtype,
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dfi_databits=2*databits,
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nphases=nphases,
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rdphase=0,
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@ -37,6 +37,7 @@ class K7DDRPHY(Module, AutoCSR):
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read_latency=6,
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write_latency=2
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)
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self.module = module
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self.dfi = Interface(addressbits, bankbits, 2*databits, nphases)
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@ -21,8 +21,8 @@ from misoclib.mem.sdram.phy.dfi import *
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from misoclib.mem import sdram
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class S6DDRPHY(Module):
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def __init__(self, pads, memtype, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
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if memtype not in ["DDR", "LPDDR", "DDR2"]:
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def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
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if module.memtype not in ["DDR", "LPDDR", "DDR2"]:
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raise NotImplementedError("S6DDRPHY only supports DDR, LPDDR and DDR2")
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addressbits = flen(pads.a)
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bankbits = flen(pads.ba)
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@ -30,7 +30,7 @@ class S6DDRPHY(Module):
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nphases = 2
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self.settings = sdram.PhySettings(
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memtype=memtype,
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memtype=module.memtype,
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dfi_databits=2*databits,
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nphases=nphases,
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rdphase=0,
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@ -41,6 +41,7 @@ class S6DDRPHY(Module):
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read_latency=5,
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write_latency=0
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)
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self.module = module
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self.dfi = Interface(addressbits, bankbits, 2*databits, nphases)
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self.clk4x_wr_strb = Signal()
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@ -26,7 +26,7 @@ class SDRAMSoC(SoC):
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self.sdram_controller_settings = sdram_controller_settings
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self._sdram_phy_registered = False
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def register_sdram_phy(self, phy, geom_settings, timing_settings):
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def register_sdram_phy(self, phy):
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if self._sdram_phy_registered:
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raise FinalizeError
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self._sdram_phy_registered = True
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@ -34,7 +34,7 @@ class SDRAMSoC(SoC):
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raise NotImplementedError("Minicon only supports SDR memtype for now (" + phy.settings.memtype + ")")
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# Core
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self.submodules.sdram = SDRAMCore(phy, geom_settings, timing_settings, self.sdram_controller_settings)
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self.submodules.sdram = SDRAMCore(phy, phy.module.geom_settings, phy.module.timing_settings, self.sdram_controller_settings)
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# LASMICON frontend
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if isinstance(self.sdram_controller_settings, LASMIconSettings):
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@ -63,7 +63,9 @@ class SDRAMSoC(SoC):
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# MINICON frontend
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elif isinstance(self.sdram_controller_settings, MiniconSettings):
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sdram_width = flen(self.sdram.controller.bus.dat_r)
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main_ram_size = 2**(geom_settings.bankbits+geom_settings.rowbits+geom_settings.colbits)*sdram_width//8
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main_ram_size = 2**(phy.module.geom_settings.bankbits+
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phy.module.geom_settings.rowbits+
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phy.module.geom_settings.colbits)*sdram_width//8
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if sdram_width == 32:
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self.register_mem("main_ram", self.mem_map["main_ram"], self.sdram.controller.bus, main_ram_size)
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@ -93,8 +93,7 @@ class BaseSoC(SDRAMSoC):
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self.submodules.crg = _CRG(platform)
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if not self.with_integrated_main_ram:
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sdram_module = IS42S16160(self.clk_freq)
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self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
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self.register_sdram_phy(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
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self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"), IS42S16160(self.clk_freq))
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self.register_sdram_phy(self.sdrphy)
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default_subtarget = BaseSoC
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@ -86,9 +86,8 @@ class BaseSoC(SDRAMSoC):
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self.submodules.crg = _CRG(platform)
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if not self.with_integrated_main_ram:
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sdram_modules = MT8JTF12864(self.clk_freq)
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self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
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self.register_sdram_phy(self.ddrphy, sdram_modules.geom_settings, sdram_modules.timing_settings)
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self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), MT8JTF12864(self.clk_freq))
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self.register_sdram_phy(self.ddrphy)
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spiflash_pads = platform.request("spiflash")
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spiflash_pads.clk = Signal()
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@ -73,8 +73,7 @@ class BaseSoC(SDRAMSoC):
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self.submodules.crg = _CRG(platform, clk_freq)
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if not self.with_integrated_main_ram:
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sdram_module = AS4C16M16(clk_freq)
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self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
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self.register_sdram_phy(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
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self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"), AS4C16M16(clk_freq))
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self.register_sdram_phy(self.sdrphy)
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default_subtarget = BaseSoC
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@ -44,10 +44,9 @@ class BaseSoC(SDRAMSoC):
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self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
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if not self.with_integrated_main_ram:
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sdram_modules = MT46V32M16(self.clk_freq)
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self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR",
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self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), MT46V32M16(self.clk_freq),
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rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
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self.register_sdram_phy(self.ddrphy, sdram_modules.geom_settings, sdram_modules.timing_settings)
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self.register_sdram_phy(self.ddrphy)
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self.comb += [
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self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
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@ -102,9 +102,8 @@ class BaseSoC(SDRAMSoC):
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self.submodules.crg = _CRG(platform, clk_freq)
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if not self.with_integrated_main_ram:
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sdram_module = MT46H32M16(self.clk_freq)
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self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"),
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"LPDDR", rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1")
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self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), MT46H32M16(self.clk_freq),
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rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1")
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self.comb += [
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self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
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self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
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@ -112,7 +111,7 @@ class BaseSoC(SDRAMSoC):
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platform.add_platform_command("""
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PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
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""")
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self.register_sdram_phy(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings)
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self.register_sdram_phy(self.ddrphy)
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self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=10, div=4)
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# If not in ROM, BIOS is in SPI flash
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@ -78,9 +78,8 @@ class BaseSoC(SDRAMSoC):
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self.submodules.crg = _CRG(platform, clk_freq)
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if not self.with_integrated_main_ram:
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sdram_module = MT48LC4M16(clk_freq)
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self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
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self.register_sdram_phy(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
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self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"), MT48LC4M16(clk_freq))
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self.register_sdram_phy(self.sdrphy)
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self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
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self.flash_boot_address = 0x70000
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