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sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy

This commit is contained in:
Florent Kermarrec 2015-03-24 18:26:18 +01:00
parent 7ea9e2ba89
commit ba8b24df57
11 changed files with 37 additions and 37 deletions
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17
misoclib/mem/sdram/module.py
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@ -21,8 +21,9 @@ from migen.fhdl.std import *
from misoclib.mem import sdram from misoclib.mem import sdram
class SDRAMModule: class SDRAMModule:
def __init__(self, clk_freq, geom_settings, timing_settings): def __init__(self, clk_freq, memtype, geom_settings, timing_settings):
self.clk_freq = clk_freq self.clk_freq = clk_freq
self.memtype = memtype
self.geom_settings = sdram.GeomSettings( self.geom_settings = sdram.GeomSettings(
databits=geom_settings["nbits"], databits=geom_settings["nbits"],
bankbits=log2_int(geom_settings["nbanks"]), bankbits=log2_int(geom_settings["nbanks"]),
@ -62,7 +63,7 @@ class IS42S16160(SDRAMModule):
"tRFC": 70 "tRFC": 70
} }
def __init__(self, clk_freq): def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, self.geom_settings, SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
self.timing_settings) self.timing_settings)
class MT48LC4M16(SDRAMModule): class MT48LC4M16(SDRAMModule):
@ -81,7 +82,7 @@ class MT48LC4M16(SDRAMModule):
"tRFC": 66 "tRFC": 66
} }
def __init__(self, clk_freq): def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, self.geom_settings, SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
self.timing_settings) self.timing_settings)
class AS4C16M16(SDRAMModule): class AS4C16M16(SDRAMModule):
@ -101,7 +102,7 @@ class AS4C16M16(SDRAMModule):
"tRFC": 60 "tRFC": 60
} }
def __init__(self, clk_freq): def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, self.geom_settings, SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
self.timing_settings) self.timing_settings)
# DDR # DDR
@ -121,7 +122,7 @@ class MT46V32M16(SDRAMModule):
"tRFC": 70 "tRFC": 70
} }
def __init__(self, clk_freq): def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, self.geom_settings, SDRAMModule.__init__(self, clk_freq, "DDR", self.geom_settings,
self.timing_settings) self.timing_settings)
# LPDDR # LPDDR
@ -141,7 +142,7 @@ class MT46H32M16(SDRAMModule):
"tRFC": 72 "tRFC": 72
} }
def __init__(self, clk_freq): def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, self.geom_settings, SDRAMModule.__init__(self, clk_freq, "LPDDR", self.geom_settings,
self.timing_settings) self.timing_settings)
# DDR2 # DDR2
@ -161,7 +162,7 @@ class MT47H128M8(SDRAMModule):
"tRFC": 127.5 "tRFC": 127.5
} }
def __init__(self, clk_freq): def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, self.geom_settings, SDRAMModule.__init__(self, clk_freq, "DDR2", self.geom_settings,
self.timing_settings) self.timing_settings)
# DDR3 # DDR3
@ -181,5 +182,5 @@ class MT8JTF12864(SDRAMModule):
"tRFC": 70 "tRFC": 70
} }
def __init__(self, clk_freq): def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, self.geom_settings, SDRAMModule.__init__(self, clk_freq, "DDR3", self.geom_settings,
self.timing_settings) self.timing_settings)

5
misoclib/mem/sdram/phy/gensdrphy.py
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@ -29,13 +29,13 @@ from misoclib.mem.sdram.phy.dfi import *
from misoclib.mem import sdram from misoclib.mem import sdram
class GENSDRPHY(Module): class GENSDRPHY(Module):
def __init__(self, pads): def __init__(self, pads, module):
addressbits = flen(pads.a) addressbits = flen(pads.a)
bankbits = flen(pads.ba) bankbits = flen(pads.ba)
databits = flen(pads.dq) databits = flen(pads.dq)
self.settings = sdram.PhySettings( self.settings = sdram.PhySettings(
memtype="SDR", memtype=module.memtype,
dfi_databits=databits, dfi_databits=databits,
nphases=1, nphases=1,
rdphase=0, rdphase=0,
@ -46,6 +46,7 @@ class GENSDRPHY(Module):
read_latency=4, read_latency=4,
write_latency=0 write_latency=0
) )
self.module = module
self.dfi = Interface(addressbits, bankbits, databits) self.dfi = Interface(addressbits, bankbits, databits)

5
misoclib/mem/sdram/phy/k7ddrphy.py
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@ -7,7 +7,7 @@ from misoclib.mem.sdram.phy.dfi import *
from misoclib.mem import sdram from misoclib.mem import sdram
class K7DDRPHY(Module, AutoCSR): class K7DDRPHY(Module, AutoCSR):
def __init__(self, pads, memtype): def __init__(self, pads, module):
addressbits = flen(pads.a) addressbits = flen(pads.a)
bankbits = flen(pads.ba) bankbits = flen(pads.ba)
databits = flen(pads.dq) databits = flen(pads.dq)
@ -25,7 +25,7 @@ class K7DDRPHY(Module, AutoCSR):
self._wdly_dqs_inc = CSR() self._wdly_dqs_inc = CSR()
self.settings = sdram.PhySettings( self.settings = sdram.PhySettings(
memtype=memtype, memtype=module.memtype,
dfi_databits=2*databits, dfi_databits=2*databits,
nphases=nphases, nphases=nphases,
rdphase=0, rdphase=0,
@ -37,6 +37,7 @@ class K7DDRPHY(Module, AutoCSR):
read_latency=6, read_latency=6,
write_latency=2 write_latency=2
) )
self.module = module
self.dfi = Interface(addressbits, bankbits, 2*databits, nphases) self.dfi = Interface(addressbits, bankbits, 2*databits, nphases)

7
misoclib/mem/sdram/phy/s6ddrphy.py
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@ -21,8 +21,8 @@ from misoclib.mem.sdram.phy.dfi import *
from misoclib.mem import sdram from misoclib.mem import sdram
class S6DDRPHY(Module): class S6DDRPHY(Module):
def __init__(self, pads, memtype, rd_bitslip, wr_bitslip, dqs_ddr_alignment): def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
if memtype not in ["DDR", "LPDDR", "DDR2"]: if module.memtype not in ["DDR", "LPDDR", "DDR2"]:
raise NotImplementedError("S6DDRPHY only supports DDR, LPDDR and DDR2") raise NotImplementedError("S6DDRPHY only supports DDR, LPDDR and DDR2")
addressbits = flen(pads.a) addressbits = flen(pads.a)
bankbits = flen(pads.ba) bankbits = flen(pads.ba)
@ -30,7 +30,7 @@ class S6DDRPHY(Module):
nphases = 2 nphases = 2
self.settings = sdram.PhySettings( self.settings = sdram.PhySettings(
memtype=memtype, memtype=module.memtype,
dfi_databits=2*databits, dfi_databits=2*databits,
nphases=nphases, nphases=nphases,
rdphase=0, rdphase=0,
@ -41,6 +41,7 @@ class S6DDRPHY(Module):
read_latency=5, read_latency=5,
write_latency=0 write_latency=0
) )
self.module = module
self.dfi = Interface(addressbits, bankbits, 2*databits, nphases) self.dfi = Interface(addressbits, bankbits, 2*databits, nphases)
self.clk4x_wr_strb = Signal() self.clk4x_wr_strb = Signal()

8
misoclib/soc/sdram.py
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@ -26,7 +26,7 @@ class SDRAMSoC(SoC):
self.sdram_controller_settings = sdram_controller_settings self.sdram_controller_settings = sdram_controller_settings
self._sdram_phy_registered = False self._sdram_phy_registered = False
def register_sdram_phy(self, phy, geom_settings, timing_settings): def register_sdram_phy(self, phy):
if self._sdram_phy_registered: if self._sdram_phy_registered:
raise FinalizeError raise FinalizeError
self._sdram_phy_registered = True self._sdram_phy_registered = True
@ -34,7 +34,7 @@ class SDRAMSoC(SoC):
raise NotImplementedError("Minicon only supports SDR memtype for now (" + phy.settings.memtype + ")") raise NotImplementedError("Minicon only supports SDR memtype for now (" + phy.settings.memtype + ")")
# Core # Core
self.submodules.sdram = SDRAMCore(phy, geom_settings, timing_settings, self.sdram_controller_settings) self.submodules.sdram = SDRAMCore(phy, phy.module.geom_settings, phy.module.timing_settings, self.sdram_controller_settings)
# LASMICON frontend # LASMICON frontend
if isinstance(self.sdram_controller_settings, LASMIconSettings): if isinstance(self.sdram_controller_settings, LASMIconSettings):
@ -63,7 +63,9 @@ class SDRAMSoC(SoC):
# MINICON frontend # MINICON frontend
elif isinstance(self.sdram_controller_settings, MiniconSettings): elif isinstance(self.sdram_controller_settings, MiniconSettings):
sdram_width = flen(self.sdram.controller.bus.dat_r) sdram_width = flen(self.sdram.controller.bus.dat_r)
main_ram_size = 2**(geom_settings.bankbits+geom_settings.rowbits+geom_settings.colbits)*sdram_width//8 main_ram_size = 2**(phy.module.geom_settings.bankbits+
phy.module.geom_settings.rowbits+
phy.module.geom_settings.colbits)*sdram_width//8
if sdram_width == 32: if sdram_width == 32:
self.register_mem("main_ram", self.mem_map["main_ram"], self.sdram.controller.bus, main_ram_size) self.register_mem("main_ram", self.mem_map["main_ram"], self.sdram.controller.bus, main_ram_size)

5
targets/de0nano.py
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@ -93,8 +93,7 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = _CRG(platform) self.submodules.crg = _CRG(platform)
if not self.with_integrated_main_ram: if not self.with_integrated_main_ram:
sdram_module = IS42S16160(self.clk_freq) self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"), IS42S16160(self.clk_freq))
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram")) self.register_sdram_phy(self.sdrphy)
self.register_sdram_phy(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
default_subtarget = BaseSoC default_subtarget = BaseSoC

5
targets/kc705.py
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@ -86,9 +86,8 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = _CRG(platform) self.submodules.crg = _CRG(platform)
if not self.with_integrated_main_ram: if not self.with_integrated_main_ram:
sdram_modules = MT8JTF12864(self.clk_freq) self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), MT8JTF12864(self.clk_freq))
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3") self.register_sdram_phy(self.ddrphy)
self.register_sdram_phy(self.ddrphy, sdram_modules.geom_settings, sdram_modules.timing_settings)
spiflash_pads = platform.request("spiflash") spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal() spiflash_pads.clk = Signal()

5
targets/minispartan6.py
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@ -73,8 +73,7 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = _CRG(platform, clk_freq) self.submodules.crg = _CRG(platform, clk_freq)
if not self.with_integrated_main_ram: if not self.with_integrated_main_ram:
sdram_module = AS4C16M16(clk_freq) self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"), AS4C16M16(clk_freq))
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram")) self.register_sdram_phy(self.sdrphy)
self.register_sdram_phy(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
default_subtarget = BaseSoC default_subtarget = BaseSoC

5
targets/mlabs_video.py
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@ -44,10 +44,9 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq) self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
if not self.with_integrated_main_ram: if not self.with_integrated_main_ram:
sdram_modules = MT46V32M16(self.clk_freq) self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), MT46V32M16(self.clk_freq),
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR",
rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1") rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
self.register_sdram_phy(self.ddrphy, sdram_modules.geom_settings, sdram_modules.timing_settings) self.register_sdram_phy(self.ddrphy)
self.comb += [ self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),

7
targets/pipistrello.py
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@ -102,9 +102,8 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = _CRG(platform, clk_freq) self.submodules.crg = _CRG(platform, clk_freq)
if not self.with_integrated_main_ram: if not self.with_integrated_main_ram:
sdram_module = MT46H32M16(self.clk_freq) self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), MT46H32M16(self.clk_freq),
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1")
"LPDDR", rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1")
self.comb += [ self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
@ -112,7 +111,7 @@ class BaseSoC(SDRAMSoC):
platform.add_platform_command(""" platform.add_platform_command("""
PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE; PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
""") """)
self.register_sdram_phy(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) self.register_sdram_phy(self.ddrphy)
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=10, div=4) self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=10, div=4)
# If not in ROM, BIOS is in SPI flash # If not in ROM, BIOS is in SPI flash

5
targets/ppro.py
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@ -78,9 +78,8 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = _CRG(platform, clk_freq) self.submodules.crg = _CRG(platform, clk_freq)
if not self.with_integrated_main_ram: if not self.with_integrated_main_ram:
sdram_module = MT48LC4M16(clk_freq) self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"), MT48LC4M16(clk_freq))
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram")) self.register_sdram_phy(self.sdrphy)
self.register_sdram_phy(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6) self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
self.flash_boot_address = 0x70000 self.flash_boot_address = 0x70000