soc/cores/clock: add S7MMCM support
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ef40524924
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@ -30,7 +30,7 @@ class _CRG(Module):
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_clk200, 200e6)
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pll.create_clkout(self.cd_clk200, 200e6)
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pll.add_idelayctrl(self.cd_clk200)
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pll.add_idelayctrl(self.cd_clk200)
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@ -10,16 +10,11 @@ from migen.genlib.io import DifferentialInput
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.resetsync import AsyncResetSynchronizer
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# TODO:
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# - add S7MMCM support (should be very similar to S7PLL)
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def period_ns(freq):
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def period_ns(freq):
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return 1e9/freq
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return 1e9/freq
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class S7PLL(Module):
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class S7Clocking(Module):
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nclkouts_max = 6
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clkin_freq_range = (10e6, 800e6)
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clkin_freq_range = (10e6, 800e6)
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clkfbout_mult_frange = (2, 64+1)
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clkfbout_mult_frange = (2, 64+1)
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clkout_divide_range = (1, 128+1)
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clkout_divide_range = (1, 128+1)
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@ -102,10 +97,17 @@ class S7PLL(Module):
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def do_finalize(self):
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def do_finalize(self):
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assert hasattr(self, "clkin")
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assert hasattr(self, "clkin")
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class S7PLL(S7Clocking):
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nclkouts_max = 6
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def do_finalize(self):
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S7Clocking.do_finalize(self)
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config = self.compute_config()
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config = self.compute_config()
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pll_fb = Signal()
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pll_fb = Signal()
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pll_params = dict(
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pll_params = dict(
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p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked,
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p_STARTUP_WAIT="FALSE", i_RST=self.reset, o_LOCKED=self.locked,
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# VCO
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# VCO
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=period_ns(self.clkin_freq),
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=period_ns(self.clkin_freq),
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@ -117,3 +119,28 @@ class S7PLL(Module):
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pll_params["p_CLKOUT{}_PHASE".format(n)] = config["clkout{}_phase".format(n)]
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pll_params["p_CLKOUT{}_PHASE".format(n)] = config["clkout{}_phase".format(n)]
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pll_params["o_CLKOUT{}".format(n)] = clk
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pll_params["o_CLKOUT{}".format(n)] = clk
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self.specials += Instance("PLLE2_BASE", **pll_params)
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self.specials += Instance("PLLE2_BASE", **pll_params)
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class S7MMCM(S7Clocking):
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nclkouts_max = 7
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def do_finalize(self):
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S7Clocking.do_finalize(self)
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config = self.compute_config()
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mmcm_fb = Signal()
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mmcm_params = dict(
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p_BANDWIDTH="OPTIMIZED", i_RST=self.reset, o_LOCKED=self.locked,
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# VCO
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=period_ns(self.clkin_freq),
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p_CLKFBOUT_MULT_F=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
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i_CLKIN1=self.clkin, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
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)
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for n, (clk, f, p) in sorted(self.clkouts.items()):
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if n == 0:
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mmcm_params["p_CLKOUT{}_DIVIDE_F".format(n)] = config["clkout{}_divide".format(n)]
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else:
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mmcm_params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
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mmcm_params["p_CLKOUT{}_PHASE".format(n)] = config["clkout{}_phase".format(n)]
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mmcm_params["o_CLKOUT{}".format(n)] = clk
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self.specials += Instance("MMCME2_BASE", **mmcm_params)
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