soc/integration/export: Rewrite and fix zicsr RISC-V workaround.
- Improve regex to be more robust (Was not working with binutils from Sifive). - Improve readability. - Only do it for RISC-V. - Add comments.
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@ -75,7 +75,7 @@ def get_cpu_mak(cpu, compile_software):
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for i in range(len(triple)):
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for i in range(len(triple)):
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t = triple[i]
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t = triple[i]
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# Use native toolchain if host and target platforms are the same.
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# Use native toolchain if host and target platforms are the same.
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if t == 'riscv64-unknown-elf' and p == 'linux-riscv64':
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if t == "riscv64-unknown-elf" and p == "linux-riscv64":
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r = '--native--'
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r = '--native--'
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break
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break
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if which(t+"-gcc"):
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if which(t+"-gcc"):
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@ -89,12 +89,25 @@ def get_cpu_mak(cpu, compile_software):
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msg += "- " + triple[i] + "\n"
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msg += "- " + triple[i] + "\n"
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raise OSError(msg)
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raise OSError(msg)
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return r
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return r
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selected_triple = select_triple(triple)
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selected_triple = select_triple(triple)
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if not clang:
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binutils_version = re.match("GNU ar \(GNU Binutils\) (.+)", os.popen(selected_triple + "-ar -V").read()).group(1).split(".")
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# RISC-V's march zicsr workaround (for binutils >= 2.37).
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if int(binutils_version[1]) >= 2 and int(binutils_version[2]) >= 37 and (not re.search("zicsr", flags)):
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def get_binutils_version():
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flags = re.compile("-march=([^ ]+)").sub("-march=\\1_zicsr", flags)
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version = 0
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for i, l in enumerate(os.popen(selected_triple + "-ar -V")):
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# Version is last float reported in first line.
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if i == 0:
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version = float(re.findall("\d+\.\d+", l)[-1])
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return version
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def apply_riscv_zicsr_march_workaround(flags):
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# Append _zicsr to march when binutils >= 2.37 and zicsr is not present.
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if (get_binutils_version() >= 2.37) and ("zicsr" not in flags):
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flags = re.compile("-march=([^ ]+)").sub("-march=\\1_zicsr", flags)
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return flags
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if (not clang) and ("riscv" in selected_triple):
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flags = apply_riscv_zicsr_march_workaround(flags)
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# Return informations.
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# Return informations.
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return [
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return [
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