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integration/export: Align MEM_REGIONS for BIOS display with mem_list. 

Before:
litex> mem_list
Available memory regions:
ROM       0x00000000 0x10000
SRAM      0x01000000 0x2000
AXI_RAM   0x00010000 0x1000
AXI_DP_RAM_A  0x00011000 0x1000
AXI_DP_RAM_B  0x00012000 0x1000
AXI_RAM_REG  0x00013000 0x1000
AXI_RAM_FIFO  0x00014000 0x1000
AXI_RAM_XBAR  0x00100000 0x10000
AXI_RAM_INT  0x00200000 0x10000
CSR       0x82000000 0x10000

After:
litex> mem_list
Available memory regions:
ROM           0x00000000 0x10000
SRAM          0x10000000 0x2000
AXI_RAM       0x00010000 0x1000
AXI_DP_RAM_A  0x00011000 0x1000
AXI_DP_RAM_B  0x00012000 0x1000
AXI_RAM_REG   0x00013000 0x1000
AXI_RAM_FIFO  0x00014000 0x1000
AXI_RAM_XBAR  0x00100000 0x10000
AXI_RAM_INT   0x00200000 0x10000
CSR           0xf0000000 0x10000
This commit is contained in:
Florent Kermarrec 2022-06-20 15:21:16 +02:00
parent b00d22f56a
commit bb1702e6d5
1 changed files with 2 additions and 1 deletions
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3
litex/soc/integration/export.py
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@ -154,8 +154,9 @@ def get_mem_header(regions):
r += "#ifndef MEM_REGIONS\n" r += "#ifndef MEM_REGIONS\n"
r += "#define MEM_REGIONS \""; r += "#define MEM_REGIONS \"";
name_length = max([len(name) for name in regions.keys()])
for name, region in regions.items(): for name, region in regions.items():
r += f"{name.upper()} {' '*(8-len(name))} 0x{region.origin:08x} 0x{region.size:x} \\n" r += f"{name.upper()} {' '*(name_length-len(name))} 0x{region.origin:08x} 0x{region.size:x} \\n"
r = r[:-2] r = r[:-2]
r += "\"\n" r += "\"\n"
r += "#endif\n" r += "#endif\n"