Common include files
This commit is contained in:
Sebastien Bourdeauducq
parent
b6aa40d845
commit
bb798176fc
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@ -0,0 +1,8 @@
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#ifndef __CSRBASE_H
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#define __CSRBASE_H
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#define UART_BASE 0xe0000000
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#define DFII_BASE 0xe0000800
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#define ID_BASE 0xe0001000
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#endif /* __CSRBASE_H */
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@ -1,6 +1,6 @@
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#ifndef __VERSION_H
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#define __VERSION_H
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#define VERSION "2.0-X"
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#define VERSION "2.0"
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#endif /* __VERSION_H */
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@ -204,7 +204,7 @@ void memtest(void)
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int ddrinit(void)
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{
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printf("Initializing DDRAM...\n");
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printf("Initializing DDR SDRAM...\n");
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init_sequence();
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CSR_DFII_CONTROL = DFII_CONTROL_SEL|DFII_CONTROL_CKE;
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@ -36,7 +36,7 @@ endif
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# Toolchain options
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#
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INCLUDES_NOLIBC ?= -nostdinc -I$(M2DIR)/software/include/base
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INCLUDES = $(INCLUDES_NOLIBC) -I$(M2DIR)/software/include -I$(M2DIR)/tools
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INCLUDES = $(INCLUDES_NOLIBC) -I$(M2DIR)/software/include -I$(M2DIR)/common
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ASFLAGS = $(INCLUDES) -nostdinc
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CFLAGS = -O9 -Wall -Wstrict-prototypes -Wold-style-definition -Wshadow \
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-Wmissing-prototypes -fsigned-char $(INCLUDES)
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@ -19,59 +19,62 @@
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#define __HW_DFII_H
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#include <hw/common.h>
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#include <csrbase.h>
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#define CSR_DFII_CONTROL MMPTR(0xe0000800)
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#define DFII_CSR(x) MMPTR(DFII_BASE+(x))
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#define DFII_CONTROL_SEL (0x01)
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#define DFII_CONTROL_CKE (0x02)
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#define CSR_DFII_CONTROL DFII_CSR(0x00)
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#define CSR_DFII_COMMAND_P0 MMPTR(0xe0000804)
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#define CSR_DFII_AH_P0 MMPTR(0xe0000808)
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#define CSR_DFII_AL_P0 MMPTR(0xe000080C)
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#define CSR_DFII_BA_P0 MMPTR(0xe0000810)
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#define CSR_DFII_WD0_P0 MMPTR(0xe0000814)
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#define CSR_DFII_WD1_P0 MMPTR(0xe0000818)
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#define CSR_DFII_WD2_P0 MMPTR(0xe000081C)
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#define CSR_DFII_WD3_P0 MMPTR(0xe0000820)
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#define CSR_DFII_WD4_P0 MMPTR(0xe0000824)
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#define CSR_DFII_WD5_P0 MMPTR(0xe0000828)
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#define CSR_DFII_WD6_P0 MMPTR(0xe000082C)
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#define CSR_DFII_WD7_P0 MMPTR(0xe0000830)
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#define CSR_DFII_RD0_P0 MMPTR(0xe0000834)
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#define CSR_DFII_RD1_P0 MMPTR(0xe0000838)
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#define CSR_DFII_RD2_P0 MMPTR(0xe000083C)
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#define CSR_DFII_RD3_P0 MMPTR(0xe0000840)
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#define CSR_DFII_RD4_P0 MMPTR(0xe0000844)
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#define CSR_DFII_RD5_P0 MMPTR(0xe0000848)
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#define CSR_DFII_RD6_P0 MMPTR(0xe000084C)
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#define CSR_DFII_RD7_P0 MMPTR(0xe0000850)
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#define DFII_CONTROL_SEL 0x01
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#define DFII_CONTROL_CKE 0x02
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#define CSR_DFII_COMMAND_P1 MMPTR(0xe0000854)
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#define CSR_DFII_AH_P1 MMPTR(0xe0000858)
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#define CSR_DFII_AL_P1 MMPTR(0xe000085C)
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#define CSR_DFII_BA_P1 MMPTR(0xe0000860)
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#define CSR_DFII_WD0_P1 MMPTR(0xe0000864)
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#define CSR_DFII_WD1_P1 MMPTR(0xe0000868)
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#define CSR_DFII_WD2_P1 MMPTR(0xe000086C)
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#define CSR_DFII_WD3_P1 MMPTR(0xe0000870)
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#define CSR_DFII_WD4_P1 MMPTR(0xe0000874)
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#define CSR_DFII_WD5_P1 MMPTR(0xe0000878)
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#define CSR_DFII_WD6_P1 MMPTR(0xe000087C)
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#define CSR_DFII_WD7_P1 MMPTR(0xe0000880)
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#define CSR_DFII_RD0_P1 MMPTR(0xe0000884)
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#define CSR_DFII_RD1_P1 MMPTR(0xe0000888)
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#define CSR_DFII_RD2_P1 MMPTR(0xe000088C)
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#define CSR_DFII_RD3_P1 MMPTR(0xe0000890)
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#define CSR_DFII_RD4_P1 MMPTR(0xe0000894)
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#define CSR_DFII_RD5_P1 MMPTR(0xe0000898)
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#define CSR_DFII_RD6_P1 MMPTR(0xe000089C)
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#define CSR_DFII_RD7_P1 MMPTR(0xe00008a0)
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#define CSR_DFII_COMMAND_P0 DFII_CSR(0x04)
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#define CSR_DFII_AH_P0 DFII_CSR(0x08)
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#define CSR_DFII_AL_P0 DFII_CSR(0x0C)
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#define CSR_DFII_BA_P0 DFII_CSR(0x10)
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#define CSR_DFII_WD0_P0 DFII_CSR(0x14)
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#define CSR_DFII_WD1_P0 DFII_CSR(0x18)
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#define CSR_DFII_WD2_P0 DFII_CSR(0x1C)
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#define CSR_DFII_WD3_P0 DFII_CSR(0x20)
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#define CSR_DFII_WD4_P0 DFII_CSR(0x24)
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#define CSR_DFII_WD5_P0 DFII_CSR(0x28)
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#define CSR_DFII_WD6_P0 DFII_CSR(0x2C)
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#define CSR_DFII_WD7_P0 DFII_CSR(0x30)
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#define CSR_DFII_RD0_P0 DFII_CSR(0x34)
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#define CSR_DFII_RD1_P0 DFII_CSR(0x38)
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#define CSR_DFII_RD2_P0 DFII_CSR(0x3C)
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#define CSR_DFII_RD3_P0 DFII_CSR(0x40)
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#define CSR_DFII_RD4_P0 DFII_CSR(0x44)
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#define CSR_DFII_RD5_P0 DFII_CSR(0x48)
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#define CSR_DFII_RD6_P0 DFII_CSR(0x4C)
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#define CSR_DFII_RD7_P0 DFII_CSR(0x50)
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#define DFII_COMMAND_CS (0x01)
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#define DFII_COMMAND_WE (0x02)
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#define DFII_COMMAND_CAS (0x04)
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#define DFII_COMMAND_RAS (0x08)
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#define DFII_COMMAND_WRDATA (0x10)
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#define DFII_COMMAND_RDDATA (0x20)
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#define CSR_DFII_COMMAND_P1 DFII_CSR(0x54)
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#define CSR_DFII_AH_P1 DFII_CSR(0x58)
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#define CSR_DFII_AL_P1 DFII_CSR(0x5C)
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#define CSR_DFII_BA_P1 DFII_CSR(0x60)
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#define CSR_DFII_WD0_P1 DFII_CSR(0x64)
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#define CSR_DFII_WD1_P1 DFII_CSR(0x68)
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#define CSR_DFII_WD2_P1 DFII_CSR(0x6C)
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#define CSR_DFII_WD3_P1 DFII_CSR(0x70)
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#define CSR_DFII_WD4_P1 DFII_CSR(0x74)
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#define CSR_DFII_WD5_P1 DFII_CSR(0x78)
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#define CSR_DFII_WD6_P1 DFII_CSR(0x7C)
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#define CSR_DFII_WD7_P1 DFII_CSR(0x80)
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#define CSR_DFII_RD0_P1 DFII_CSR(0x84)
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#define CSR_DFII_RD1_P1 DFII_CSR(0x88)
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#define CSR_DFII_RD2_P1 DFII_CSR(0x8C)
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#define CSR_DFII_RD3_P1 DFII_CSR(0x90)
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#define CSR_DFII_RD4_P1 DFII_CSR(0x94)
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#define CSR_DFII_RD5_P1 DFII_CSR(0x98)
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#define CSR_DFII_RD6_P1 DFII_CSR(0x9C)
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#define CSR_DFII_RD7_P1 DFII_CSR(0xA0)
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#define DFII_COMMAND_CS 0x01
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#define DFII_COMMAND_WE 0x02
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#define DFII_COMMAND_CAS 0x04
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#define DFII_COMMAND_RAS 0x08
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#define DFII_COMMAND_WRDATA 0x10
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#define DFII_COMMAND_RDDATA 0x20
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#endif /* __HW_DFII_H */
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@ -19,16 +19,19 @@
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#define __HW_UART_H
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#include <hw/common.h>
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#include <csrbase.h>
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#define CSR_UART_RXTX MMPTR(0xe0000000)
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#define CSR_UART_DIVISORH MMPTR(0xe0000004)
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#define CSR_UART_DIVISORL MMPTR(0xe0000008)
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#define UART_CSR(x) MMPTR(UART_BASE+(x))
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#define CSR_UART_EV_STAT MMPTR(0xe000000c)
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#define CSR_UART_EV_PENDING MMPTR(0xe0000010)
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#define CSR_UART_EV_ENABLE MMPTR(0xe0000014)
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#define CSR_UART_RXTX UART_CSR(0x00)
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#define CSR_UART_DIVISORH UART_CSR(0x04)
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#define CSR_UART_DIVISORL UART_CSR(0x08)
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#define UART_EV_TX (0x1)
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#define UART_EV_RX (0x2)
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#define CSR_UART_EV_STAT UART_CSR(0x0c)
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#define CSR_UART_EV_PENDING UART_CSR(0x10)
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#define CSR_UART_EV_ENABLE UART_CSR(0x14)
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#define UART_EV_TX 0x1
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#define UART_EV_RX 0x2
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#endif /* __HW_UART_H */
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@ -4,7 +4,7 @@ CC=clang
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all: $(TARGETS)
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%: %.c
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$(CC) -O2 -Wall -I. -s -o $@ $<
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$(CC) -O2 -Wall -I../common -s -o $@ $<
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install: mkmmimg flterm
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install -d /usr/local/bin
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