k7ddrphy: fix write_latency and take care of OSERDESE2 latency on oe
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@ -23,7 +23,7 @@ class K7DDRPHY(Module):
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cl=8,
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cl=8,
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cwl=6,
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cwl=6,
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read_latency=8,
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read_latency=8,
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write_latency=1
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write_latency=2
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)
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)
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self.dfi = Interface(a, ba, self.phy_settings.dfi_d, nphases)
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self.dfi = Interface(a, ba, self.phy_settings.dfi_d, nphases)
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@ -212,7 +212,7 @@ class K7DDRPHY(Module):
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rddata_en = n_rddata_en
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rddata_en = n_rddata_en
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self.sync += [phase.rddata_valid.eq(rddata_en) for phase in self.dfi.phases]
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self.sync += [phase.rddata_valid.eq(rddata_en) for phase in self.dfi.phases]
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last_wrdata_en = Signal(3)
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last_wrdata_en = Signal(5)
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wrphase = self.dfi.phases[self.phy_settings.wrphase]
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wrphase = self.dfi.phases[self.phy_settings.wrphase]
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self.sync += last_wrdata_en.eq(Cat(wrphase.wrdata_en, last_wrdata_en[:2]))
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self.sync += last_wrdata_en.eq(Cat(wrphase.wrdata_en, last_wrdata_en[:4]))
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self.comb += oe.eq(last_wrdata_en[0] | last_wrdata_en[1] | last_wrdata_en[2])
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self.comb += oe.eq(last_wrdata_en[2+0] | last_wrdata_en[2+1] | last_wrdata_en[2+2])
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