cores/gpio: add CSR descriptions.
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@ -10,21 +10,21 @@ from litex.soc.interconnect.csr import *
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class GPIOIn(Module, AutoCSR):
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class GPIOIn(Module, AutoCSR):
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def __init__(self, signal):
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def __init__(self, signal):
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self._in = CSRStatus(len(signal))
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self._in = CSRStatus(len(signal), description="GPIO Input(s) Status.")
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self.specials += MultiReg(signal, self._in.status)
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self.specials += MultiReg(signal, self._in.status)
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# GPIO Output --------------------------------------------------------------------------------------
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# GPIO Output --------------------------------------------------------------------------------------
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class GPIOOut(Module, AutoCSR):
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class GPIOOut(Module, AutoCSR):
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def __init__(self, signal):
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def __init__(self, signal):
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self._out = CSRStorage(len(signal))
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self._out = CSRStorage(len(signal), description="GPIO Output(s) Control.")
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self.comb += signal.eq(self._out.storage)
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self.comb += signal.eq(self._out.storage)
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# GPIO Input/Output --------------------------------------------------------------------------------
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# GPIO Input/Output --------------------------------------------------------------------------------
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class GPIOInOut(Module):
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class GPIOInOut(Module):
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def __init__(self, in_signal, out_signal):
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def __init__(self, in_signal, out_signal):
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self.submodules.gpio_in = GPIOIn(in_signal)
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self.submodules.gpio_in = GPIOIn(in_signal)
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self.submodules.gpio_out = GPIOOut(out_signal)
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self.submodules.gpio_out = GPIOOut(out_signal)
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def get_csrs(self):
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def get_csrs(self):
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@ -35,9 +35,9 @@ class GPIOInOut(Module):
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class GPIOTristate(Module, AutoCSR):
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class GPIOTristate(Module, AutoCSR):
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def __init__(self, pads):
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def __init__(self, pads):
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nbits = len(pads)
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nbits = len(pads)
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self._oe = CSRStorage(nbits)
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self._oe = CSRStorage(nbits, description="GPIO Tristate(s) Control.")
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self._in = CSRStatus(nbits)
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self._in = CSRStatus(nbits, description="GPIO Input(s) Status.")
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self._out = CSRStorage(nbits)
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self._out = CSRStorage(nbits, description="GPIO Ouptut(s) Control.")
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# # #
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# # #
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