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cores/gpio: add CSR descriptions.

This commit is contained in:
Florent Kermarrec 2020-03-11 12:06:15 +01:00
parent 4dabc5a625
commit bb8905fa5d
1 changed files with 6 additions and 6 deletions
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10
litex/soc/cores/gpio.py
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@ -10,14 +10,14 @@ from litex.soc.interconnect.csr import *
class GPIOIn(Module, AutoCSR):
def __init__(self, signal):
self._in = CSRStatus(len(signal))
self._in = CSRStatus(len(signal), description="GPIO Input(s) Status.")
self.specials += MultiReg(signal, self._in.status)
# GPIO Output --------------------------------------------------------------------------------------
class GPIOOut(Module, AutoCSR):
def __init__(self, signal):
self._out = CSRStorage(len(signal))
self._out = CSRStorage(len(signal), description="GPIO Output(s) Control.")
self.comb += signal.eq(self._out.storage)
# GPIO Input/Output --------------------------------------------------------------------------------
@ -35,9 +35,9 @@ class GPIOInOut(Module):
class GPIOTristate(Module, AutoCSR):
def __init__(self, pads):
nbits = len(pads)
self._oe = CSRStorage(nbits)
self._in = CSRStatus(nbits)
self._out = CSRStorage(nbits)
self._oe = CSRStorage(nbits, description="GPIO Tristate(s) Control.")
self._in = CSRStatus(nbits, description="GPIO Input(s) Status.")
self._out = CSRStorage(nbits, description="GPIO Ouptut(s) Control.")
# # #