cores/clock/ECP5PLL: add phase support.
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@ -596,9 +596,6 @@ class iCE40PLL(Module):
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# Lattice / ECP5 -----------------------------------------------------------------------------------
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# Lattice / ECP5 -----------------------------------------------------------------------------------
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# TODO:
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# - add proper phase support.
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class ECP5PLL(Module):
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class ECP5PLL(Module):
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nclkouts_max = 3
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nclkouts_max = 3
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clkfb_div_range = (1, 128+1)
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clkfb_div_range = (1, 128+1)
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@ -655,8 +652,8 @@ class ECP5PLL(Module):
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for d in range(*self.clko_div_range):
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for d in range(*self.clko_div_range):
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clk_freq = vco_freq/d
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clk_freq = vco_freq/d
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if abs(clk_freq - f) <= f*m:
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if abs(clk_freq - f) <= f*m:
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config["clko{}_freq".format(n)] = clk_freq
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config["clko{}_freq".format(n)] = clk_freq
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config["clko{}_div".format(n)] = d
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config["clko{}_div".format(n)] = d
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config["clko{}_phase".format(n)] = p
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config["clko{}_phase".format(n)] = p
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valid = True
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valid = True
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break
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break
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@ -673,30 +670,29 @@ class ECP5PLL(Module):
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def do_finalize(self):
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def do_finalize(self):
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config = self.compute_config()
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config = self.compute_config()
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clkfb = Signal()
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clkfb = Signal()
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self.params.update(
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self.params.update(
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attr=[
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attr=[
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("ICP_CURRENT", "6"),
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("ICP_CURRENT", "6"),
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("LPF_RESISTOR", "16"),
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("LPF_RESISTOR", "16"),
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("MFG_ENABLE_FILTEROPAMP", "1"),
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("MFG_ENABLE_FILTEROPAMP", "1"),
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("MFG_GMCREF_SEL", "2")],
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("MFG_GMCREF_SEL", "2")],
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i_RST=self.reset,
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i_RST = self.reset,
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i_CLKI = self.clkin,
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i_CLKI = self.clkin,
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o_LOCK = self.locked,
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o_LOCK = self.locked,
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p_FEEDBK_PATH = "INT_OS3", # CLKOS3 reserved for feedback with div=1.
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p_CLKOS3_ENABLE = "ENABLED",
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p_FEEDBK_PATH = "INT_OS3", # CLKOS3 reserved for
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p_CLKOS3_ENABLE = "ENABLED", # feedback with div=1.
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p_CLKOS3_DIV = 1,
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p_CLKOS3_DIV = 1,
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p_CLKFB_DIV = config["clkfb_div"],
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p_CLKFB_DIV=config["clkfb_div"],
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p_CLKI_DIV = 1,
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p_CLKI_DIV=1,
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)
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)
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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n_to_l = {0: "P", 1: "S", 2: "S2"}
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n_to_l = {0: "P", 1: "S", 2: "S2"}
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div = config["clko{}_div".format(n)]
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cphase = int(p*(div + 1)/360 + div)
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self.params["p_CLKO{}_ENABLE".format(n_to_l[n])] = "ENABLED"
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self.params["p_CLKO{}_ENABLE".format(n_to_l[n])] = "ENABLED"
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self.params["p_CLKO{}_DIV".format(n_to_l[n])] = config["clko{}_div".format(n)]
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self.params["p_CLKO{}_DIV".format(n_to_l[n])] = div
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self.params["p_CLKO{}_FPHASE".format(n_to_l[n])] = 0
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self.params["p_CLKO{}_FPHASE".format(n_to_l[n])] = 0
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self.params["p_CLKO{}_CPHASE".format(n_to_l[n])] = p
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self.params["p_CLKO{}_CPHASE".format(n_to_l[n])] = cphase
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self.params["o_CLKO{}".format(n_to_l[n])] = clk
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self.params["o_CLKO{}".format(n_to_l[n])] = clk
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self.specials += Instance("EHXPLLL", **self.params)
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self.specials += Instance("EHXPLLL", **self.params)
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