build/efinix/common: Add EfinixClkInput/Ouptut to use then in RGMII PHYs and avoid duplicating block code.
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@ -62,6 +62,49 @@ class EfinixAsyncResetSynchronizer:
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def lower(dr):
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return EfinixAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
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# Efinix Clk Input ---------------------------------------------------------------------------------
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class EfinixClkInputImpl(Module):
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def __init__(self, platform, i, o):
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o_clk = platform.add_iface_io(o) # FIXME.
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block = {
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"type" : "GPIO",
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"size" : 1,
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"location" : platform.get_pin_location(i)[0],
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"properties" : platform.get_pin_properties(i),
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"name" : platform.get_pin_name(o_clk),
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"mode" : "INPUT_CLK",
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.toolchain.excluded_ios.append(i)
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class EfinixClkInput(Module):
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@staticmethod
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def lower(dr):
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return EfinixClkInputImpl(dr.platform, dr.i, dr.o)
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# Efinix Clk Output ---------------------------------------------------------------------------------
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class EfinixClkOutputImpl(Module):
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def __init__(self, platform, i, o):
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block = {
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"type" : "GPIO",
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"size" : 1,
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"location" : platform.get_pin_location(o)[0],
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"properties" : platform.get_pin_properties(o),
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"name" : i, # FIXME.
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"mode" : "OUTPUT_CLK",
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.toolchain.excluded_ios.append(o)
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class EfinixClkOutput(Module):
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@staticmethod
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def lower(dr):
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return EfinixClkOutputImpl(dr.platform, dr.i, dr.o)
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# Efinix Tristate ----------------------------------------------------------------------------------
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class EfinixTristateImpl(Module):
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@ -179,6 +222,8 @@ class EfinixDDRInput:
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efinix_special_overrides = {
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AsyncResetSynchronizer : EfinixAsyncResetSynchronizer,
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ClkInput : EfinixClkInput,
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ClkOutput : EfinixClkOutput,
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Tristate : EfinixTristate,
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SDRTristate : EfinixSDRTristate,
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DDROutput : EfinixDDROutput,
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