fhdl/bitcontainer: remove fiter
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@ -1,7 +1,7 @@
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from migen.fhdl import structure as f
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__all__ = ["log2_int", "bits_for", "flen", "fiter"]
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__all__ = ["log2_int", "bits_for", "flen"]
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def log2_int(n, need_pow2=True):
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@ -123,29 +123,3 @@ def flen(v):
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"""
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return value_bits_sign(v)[0]
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def fiter(v):
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"""Bit iterator
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Parameters
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----------
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v : int, bool or Value
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Returns
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-------
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iter
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Iterator over the bits in `v`
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Examples
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--------
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>>> list(fiter(f.Signal(2))) #doctest: +ELLIPSIS
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[<migen.fhdl.structure._Slice object at 0x...>, <migen.fhdl.structure._Slice object at 0x...>]
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>>> list(fiter(4))
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[0, 0, 1]
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"""
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if isinstance(v, (bool, int)):
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return ((v >> i) & 1 for i in range(bits_for(v)))
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elif isinstance(v, f.Value):
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return (v[i] for i in range(flen(v)))
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else:
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raise TypeError("Can not bit-iterate {} {}".format(type(v), v))
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