targets/netv2: remove LiteSPI integration (not mature enough to be directly integrated on targets).

The LiteSPI integration can be prototype in the LiteSPI example designs. Once mature and
fully tested, we could integrate it to the targets.

litex/boards/targets/netv2.py

@@ -48,7 +48,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_spi_xip=False, **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs):
         platform = netv2.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -74,16 +74,6 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
-        # SPI XIP ----------------------------------------------------------------------------------
-        if with_spi_xip:
-            from litespi import LiteSPI
-            from litespi.phy.generic import LiteSPIPHY
-            spi_xip_size = 1024*1024*8
-            self.submodules.spiphy = LiteSPIPHY(platform.request("spiflash4x"))
-            self.submodules.spictl = LiteSPI(phy=self.spiphy, endianness=self.cpu.endianness)
-            spi_xip_region = SoCRegion(origin=self.mem_map.get("spixip", None), size=spi_xip_size, cached=False)
-            self.bus.add_slave(name="spixip", slave=self.spictl.bus, region=spi_xip_region)
-
         # Ethernet ---------------------------------------------------------------------------------
         if with_ethernet:
             self.submodules.ethphy = LiteEthPHYRMII(
@@ -101,10 +91,9 @@ def main():
     builder_args(parser)
     soc_sdram_args(parser)
     parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
-    parser.add_argument("--with-spi-xip",  action="store_true", help="Enable SPI XIP support")
     args = parser.parse_args()
 
-    soc = BaseSoC(with_ethernet=args.with_ethernet, with_spi_xip=args.with_spi_xip, **soc_sdram_argdict(args))
+    soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)