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flow/actor, actorlib/structuring: add packet support

This commit is contained in:
Florent Kermarrec 2014-10-31 12:59:45 +01:00 committed by Sebastien Bourdeauducq
parent 4d1b6da42f
commit bd1d456f5d
2 changed files with 92 additions and 29 deletions
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60
migen/actorlib/structuring.py
View File

@ -8,9 +8,9 @@ def _rawbits_layout(l):
return l return l
class Cast(CombinatorialActor): class Cast(CombinatorialActor):
def __init__(self, layout_from, layout_to, reverse_from=False, reverse_to=False): def __init__(self, layout_from, layout_to, reverse_from=False, reverse_to=False, packetized=False):
self.sink = Sink(_rawbits_layout(layout_from)) self.sink = Sink(_rawbits_layout(layout_from), packetized)
self.source = Source(_rawbits_layout(layout_to)) self.source = Source(_rawbits_layout(layout_to), packetized)
CombinatorialActor.__init__(self) CombinatorialActor.__init__(self)
### ###
@ -29,16 +29,18 @@ def pack_layout(l, n):
return [("chunk"+str(i), l) for i in range(n)] return [("chunk"+str(i), l) for i in range(n)]
class Unpack(Module): class Unpack(Module):
def __init__(self, n, layout_to, reverse=False): def __init__(self, n, layout_to, reverse=False, packetized=False):
self.sink = Sink(pack_layout(layout_to, n)) self.sink = Sink(pack_layout(layout_to, n), packetized)
self.source = Source(layout_to) self.source = Source(layout_to, packetized)
self.busy = Signal() self.busy = Signal()
### ###
mux = Signal(max=n) mux = Signal(max=n)
first = Signal()
last = Signal() last = Signal()
self.comb += [ self.comb += [
first.eq(mux == 0),
last.eq(mux == (n-1)), last.eq(mux == (n-1)),
self.source.stb.eq(self.sink.stb), self.source.stb.eq(self.sink.stb),
self.sink.ack.eq(last & self.source.ack) self.sink.ack.eq(last & self.source.ack)
@ -58,10 +60,16 @@ class Unpack(Module):
cases[i] = [self.source.payload.raw_bits().eq(getattr(self.sink.payload, "chunk"+str(chunk)).raw_bits())] cases[i] = [self.source.payload.raw_bits().eq(getattr(self.sink.payload, "chunk"+str(chunk)).raw_bits())]
self.comb += Case(mux, cases).makedefault() self.comb += Case(mux, cases).makedefault()
if packetized:
self.comb += [
self.source.sop.eq(self.source.stb & self.sink.sop & first),
self.source.eop.eq(self.source.stb & self.sink.eop & last)
]
class Pack(Module): class Pack(Module):
def __init__(self, layout_from, n, reverse=False): def __init__(self, layout_from, n, reverse=False, packetized=False):
self.sink = Sink(layout_from) self.sink = sink = Sink(layout_from, packetized)
self.source = Source(pack_layout(layout_from, n)) self.source = source = Source(pack_layout(layout_from, n), packetized)
self.busy = Signal() self.busy = Signal()
### ###
@ -73,18 +81,24 @@ class Pack(Module):
cases = {} cases = {}
for i in range(n): for i in range(n):
chunk = n-i-1 if reverse else i chunk = n-i-1 if reverse else i
cases[i] = [getattr(self.source.payload, "chunk"+str(chunk)).raw_bits().eq(self.sink.payload.raw_bits())] cases[i] = [getattr(source.payload, "chunk"+str(chunk)).raw_bits().eq(sink.payload.raw_bits())]
self.comb += [ self.comb += [
self.busy.eq(strobe_all), self.busy.eq(strobe_all),
self.sink.ack.eq(~strobe_all | self.source.ack), sink.ack.eq(~strobe_all | source.ack),
self.source.stb.eq(strobe_all), source.stb.eq(strobe_all),
load_part.eq(self.sink.stb & self.sink.ack) load_part.eq(sink.stb & sink.ack)
] ]
if packetized:
demux_last = ((demux == (n - 1)) | sink.eop)
else:
demux_last = (demux == (n - 1))
self.sync += [ self.sync += [
If(self.source.ack, strobe_all.eq(0)), If(source.ack, strobe_all.eq(0)),
If(load_part, If(load_part,
Case(demux, cases), Case(demux, cases),
If(demux == (n - 1), If(demux_last,
demux.eq(0), demux.eq(0),
strobe_all.eq(1) strobe_all.eq(1)
).Else( ).Else(
@ -92,3 +106,19 @@ class Pack(Module):
) )
) )
] ]
if packetized:
sop = Signal()
eop = Signal()
self.sync += [
If(source.stb & source.ack,
sop.eq(load_part & sink.sop)
).Else(
sop.eq((load_part & sink.sop) | sop)
),
eop.eq(load_part & sink.eop)
]
self.comb += [
source.sop.eq(source.stb & sop),
source.eop.eq(source.stb & eop),
]

61
migen/flow/actor.py
View File

@ -22,6 +22,7 @@ def _check_layout(layout, packetized):
class _Endpoint(Record): class _Endpoint(Record):
def __init__(self, layout, packetized=False): def __init__(self, layout, packetized=False):
self.packetized = packetized
_check_layout(layout, packetized) _check_layout(layout, packetized)
endpoint_layout = [ endpoint_layout = [
("payload", _make_m2s(layout)), ("payload", _make_m2s(layout)),
@ -66,21 +67,30 @@ class BinaryActor(Module):
self.busy = Signal() self.busy = Signal()
sink = get_single_ep(self, Sink)[1] sink = get_single_ep(self, Sink)[1]
source = get_single_ep(self, Source)[1] source = get_single_ep(self, Source)[1]
self.build_binary_control(sink.stb, sink.ack, source.stb, source.ack, *args, **kwargs) self.build_binary_control(sink, source, *args, **kwargs)
def build_binary_control(self, stb_i, ack_o, stb_o, ack_i): def build_binary_control(self, sink, source):
raise NotImplementedError("Binary actor classes must overload build_binary_control_fragment") raise NotImplementedError("Binary actor classes must overload build_binary_control_fragment")
class CombinatorialActor(BinaryActor): class CombinatorialActor(BinaryActor):
def build_binary_control(self, stb_i, ack_o, stb_o, ack_i): def build_binary_control(self, sink, source):
self.comb += [stb_o.eq(stb_i), ack_o.eq(ack_i), self.busy.eq(0)] self.comb += [
source.stb.eq(sink.stb),
sink.ack.eq(source.ack),
self.busy.eq(0)
]
if sink.packetized:
self.comb += [
source.sop.eq(sink.sop),
source.eop.eq(sink.eop)
]
class SequentialActor(BinaryActor): class SequentialActor(BinaryActor):
def __init__(self, delay): def __init__(self, delay):
self.trigger = Signal() self.trigger = Signal()
BinaryActor.__init__(self, delay) BinaryActor.__init__(self, delay)
def build_binary_control(self, stb_i, ack_o, stb_o, ack_i, delay): def build_binary_control(self, sink, source, delay):
ready = Signal() ready = Signal()
timer = Signal(max=delay+1) timer = Signal(max=delay+1)
self.comb += ready.eq(timer == 0) self.comb += ready.eq(timer == 0)
@ -92,14 +102,19 @@ class SequentialActor(BinaryActor):
mask = Signal() mask = Signal()
self.comb += [ self.comb += [
stb_o.eq(ready & mask), source.stb.eq(ready & mask),
self.trigger.eq(stb_i & (ack_i | ~mask) & ready), self.trigger.eq(sink.stb & (source.ack | ~mask) & ready),
ack_o.eq(self.trigger), sink.ack.eq(self.trigger),
self.busy.eq(~ready) self.busy.eq(~ready)
] ]
self.sync += [ self.sync += [
If(self.trigger, mask.eq(1)), If(self.trigger, mask.eq(1)),
If(stb_o & ack_i, mask.eq(0)) If(source.stb & source.ack, mask.eq(0))
]
if sink.packetized:
self.comb += [
source.sop.eq(sink.sop),
source.eop.eq(sink.eop)
] ]
class PipelinedActor(BinaryActor): class PipelinedActor(BinaryActor):
@ -107,9 +122,9 @@ class PipelinedActor(BinaryActor):
self.pipe_ce = Signal() self.pipe_ce = Signal()
BinaryActor.__init__(self, latency) BinaryActor.__init__(self, latency)
def build_binary_control(self, stb_i, ack_o, stb_o, ack_i, latency): def build_binary_control(self, sink, source, latency):
busy = 0 busy = 0
valid = stb_i valid = sink.stb
for i in range(latency): for i in range(latency):
valid_n = Signal() valid_n = Signal()
self.sync += If(self.pipe_ce, valid_n.eq(valid)) self.sync += If(self.pipe_ce, valid_n.eq(valid))
@ -117,8 +132,26 @@ class PipelinedActor(BinaryActor):
busy = busy | valid busy = busy | valid
self.comb += [ self.comb += [
self.pipe_ce.eq(ack_i | ~valid), self.pipe_ce.eq(source.ack | ~valid),
ack_o.eq(self.pipe_ce), sink.ack.eq(self.pipe_ce),
stb_o.eq(valid), source.stb.eq(valid),
self.busy.eq(busy) self.busy.eq(busy)
] ]
if sink.packetized:
sop = sink.sop
eop = sink.eop
for i in range(latency):
sop_n = Signal()
eop_n = Signal()
self.sync += \
If(self.pipe_ce,
sop_n.eq(sop),
eop_n.eq(eop)
)
sop = sop_n
eop = eop_n
self.comb += [
source.eop.eq(eop),
source.sop.eq(sop)
]