platforms: add default_clk_freq/default_clk_name (to use it on simple designs to test MiSOC on various platforms)

mibuild/platforms/apf27.py

@@ -142,6 +142,8 @@ _connectors = [
 ]
 
 class Platform(XilinxISEPlatform):
+	default_clk_name = "clk0"
+	default_clk_period = 10
 	def __init__(self):
 		XilinxISEPlatform.__init__(self, "xc3s200a-ft256-4", _ios,
 			lambda p: SimpleCRG(p, "clk0", None), _connectors)

mibuild/platforms/apf51.py

@@ -169,6 +169,8 @@ _connectors = [
 ]
 
 class Platform(XilinxISEPlatform):
+	default_clk_name = "clk3"
+	default_clk_period = 10.526
 	def __init__(self):
 		XilinxISEPlatform.__init__(self, "xc6slx9-2csg225", _ios,
 			lambda p: SimpleCRG(p, "clk3", None), _connectors)

mibuild/platforms/de0nano.py

@@ -92,6 +92,8 @@ _io = [
 ]
 
 class Platform(AlteraQuartusPlatform):
+	default_clk_name = "clk50"
+	default_clk_period = 20
 	def __init__(self):
 		AlteraQuartusPlatform.__init__(self, "EP4CE22F17C6", _io,
 			lambda p: SimpleCRG(p, "clk50", None))

mibuild/platforms/kc705.py

@@ -348,6 +348,8 @@ def Platform(*args, toolchain="vivado", **kwargs):
 		raise ValueError
 
 	class RealPlatform(xilinx_platform):
+		default_clk_name = "clk156"
+		default_clk_period = 6.4
 		bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
 
 		def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset")):

mibuild/platforms/lx9_microboard.py

@@ -103,6 +103,8 @@ _io = [
 
 
 class Platform(XilinxISEPlatform):
+	default_clk_name = "clk_y3"
+	default_clk_period = 10
 	bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
 	ise_commands = """
 promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit

mibuild/platforms/m1.py

@@ -119,6 +119,8 @@ _io = [
 ]
 
 class Platform(XilinxISEPlatform):
+	default_clk_name = "clk50"
+	default_clk_period = 20
 	def __init__(self):
 		XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
 			lambda p: SimpleCRG(p, "clk50", None))

mibuild/platforms/mixxeo.py

@@ -155,6 +155,8 @@ _io = [
 ]
 
 class Platform(XilinxISEPlatform):
+	default_clk_name = "clk50"
+	default_clk_period = 20
 	def __init__(self):
 		XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
 			lambda p: SimpleCRG(p, "clk50", None))

mibuild/platforms/ml605.py

@@ -52,6 +52,8 @@ _io = [
 ]
 
 class Platform(XilinxISEPlatform):
+	default_clk_name = "clk200"
+	default_clk_period = 5
 	def __init__(self):
 		XilinxISEPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io,
 			lambda p: CRG_DS(p, "clk200", "user_btn"))

mibuild/platforms/papilio_pro.py

@@ -50,6 +50,8 @@ _connectors = [
 ]
 
 class Platform(XilinxISEPlatform):
+	default_clk_name = "clk32"
+	default_clk_period = 31.25
 	def __init__(self):
 		XilinxISEPlatform.__init__(self, "xc6slx9-tqg144-2", _io,
 			lambda p: SimpleCRG(p, "clk32", None), _connectors)

mibuild/platforms/rhino.py

@@ -134,6 +134,8 @@ _io = [
 ]
 
 class Platform(XilinxISEPlatform):
+	default_clk_name = "clk100"
+	default_clk_period = 10
 	def __init__(self):
 		XilinxISEPlatform.__init__(self, "xc6slx150t-fgg676-3", _io,
 			lambda p: CRG_DS(p, "clk100", "gpio"))

mibuild/platforms/usrp_b100.py

@@ -114,6 +114,8 @@ _io = [
 
 
 class Platform(XilinxISEPlatform):
+	default_clk_name = "clk64"
+	default_clk_period = 15.625
 	bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"
 	def __init__(self):
 		XilinxISEPlatform.__init__(self, "xc3s1400a-ft256-4", _io,

mibuild/platforms/zedboard.py

@@ -138,6 +138,8 @@ _io = [
 
 
 class Platform(XilinxISEPlatform):
+	default_clk_name = "clk100"
+	default_clk_period = 10
 	def __init__(self):
 		XilinxISEPlatform.__init__(self, "xc7z020-clg484-1", _io,
 			lambda p: SimpleCRG(p, "clk100", None))

mibuild/platforms/ztex_115d.py

@@ -83,6 +83,8 @@ _io = [
 
 class Platform(XilinxISEPlatform):
 	def __init__(self):
+		default_clk_name = "clk_if"
+		default_clk_period = 20
 		XilinxISEPlatform.__init__(self, "xc6slx150-3csg484", _io,
 				lambda p: SimpleCRG(p, "clk_if", "rst"))
 		self.add_platform_command("""