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Merge pull request #373 from antmicro/l2-reverse
tools/litex_sim: use l2_reverse flag
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@ -168,6 +168,7 @@ class SimSoC(SoCSDRAM):
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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ident = "LiteX Simulation", ident_version=True,
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with_uart = False,
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l2_reverse = False,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform.request("sys_clk"))
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