efinix: more DDR work, still WIP
This commit is contained in:
Franck Jullien
parent
b765bdf34e
commit
bd71dc663f
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@ -10,7 +10,7 @@ from litex.soc.interconnect import axi
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from litex.build import tools
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class EfinixDDR(Module):
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def __init__(self, platform, config):
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def __init__(self, platform, config, cd):
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self.blocks = []
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self.platform = platform
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self.config = config
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@ -19,15 +19,11 @@ class EfinixDDR(Module):
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if config['ports'] != None:
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self.nb_ports = self.config['ports']
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self.clock_domains.cd_axi_ddr = ClockDomain()
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self.port0 = port0 = axi.AXIInterface(data_width=256, address_width=32, id_width=8, clock_domain="axi_ddr")
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# TODO: set clock_domain ?
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self.port0 = port0 = axi.AXIInterface(data_width=256, address_width=32, id_width=8)
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if self.nb_ports == 2:
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self.port1 = port1 = axi.AXIInterface(data_width=256, address_width=32, id_width=8, clock_domain="axi_ddr")
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axi_clk = platform.add_iface_io('axi_user_clk')
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self.cd_axi_ddr.clk.eq(axi_clk),
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self.port1 = port1 = axi.AXIInterface(data_width=256, address_width=32, id_width=8)
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for i in range (0, self.nb_ports):
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ios = [('axi', i,
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@ -60,7 +56,7 @@ class EfinixDDR(Module):
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io = platform.add_iface_ios(ios)
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port = port0
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if i == 0:
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if i == 1:
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port = port1
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is_read = port.ar.valid
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@ -23,7 +23,7 @@ class InterfaceWriter():
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root = tree.getroot()
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ddr_info = root.find('efxpt:ddr_info', namespaces)
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et.SubElement(ddr_info, 'efxpt:ddr',
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ddr = et.SubElement(ddr_info, 'efxpt:ddr',
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name = 'ddr_inst1',
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ddr_def = 'DDR_0',
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cs_preset_id = '173',
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@ -39,7 +39,7 @@ class InterfaceWriter():
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axi_suffix = '' # '_1' for second port
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type_suffix = '_0' # '_1' for second port
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gen_pin_target0 = et.SubElement(ddr_info, 'efxpt:gen_pin_target0')
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gen_pin_target0 = et.SubElement(ddr, 'efxpt:gen_pin_target0')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_wdata{}'.format(axi_suffix), type_name='WDATA{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_wready{}'.format(axi_suffix), type_name='WREADY{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_wid{}'.format(axi_suffix), type_name='WID{}'.format(type_suffix), is_bus = 'true')
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@ -64,10 +64,39 @@ class InterfaceWriter():
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_wstrb{}'.format(axi_suffix), type_name='WSTRB{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_aready{}'.format(axi_suffix), type_name='AREADY{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_alen{}'.format(axi_suffix), type_name='ALEN{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_clk', type_name='ACLK{}'.format(type_suffix), is_bus = 'false', is_clk = 'true', is_clk_invert = 'false')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_clk', type_name='ACLK_0', is_bus = 'false', is_clk = 'true', is_clk_invert = 'false')
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axi_suffix = '_1' # '_1' for second port
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type_suffix = '_1' # '_1' for second port
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gen_pin_config = et.SubElement(ddr_info, 'efxpt:gen_pin_config')
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gen_pin_target1 = et.SubElement(ddr, 'efxpt:gen_pin_target1')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_wdata{}'.format(axi_suffix), type_name='WDATA{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_wready{}'.format(axi_suffix), type_name='WREADY{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_wid{}'.format(axi_suffix), type_name='WID{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_bready{}'.format(axi_suffix), type_name='BREADY{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_rdata{}'.format(axi_suffix), type_name='RDATA{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_aid{}'.format(axi_suffix), type_name='AID{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_bvalid{}'.format(axi_suffix), type_name='BVALID{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_rlast{}'.format(axi_suffix), type_name='RLAST{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_bid{}'.format(axi_suffix), type_name='BID{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_asize{}'.format(axi_suffix), type_name='ASIZE{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_atype{}'.format(axi_suffix), type_name='ATYPE{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_aburst{}'.format(axi_suffix), type_name='ABURST{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_wvalid{}'.format(axi_suffix), type_name='WVALID{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_wlast{}'.format(axi_suffix), type_name='WLAST{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_aaddr{}'.format(axi_suffix), type_name='AADDR{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_rid{}'.format(axi_suffix), type_name='RID{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_avalid{}'.format(axi_suffix), type_name='AVALID{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_rvalid{}'.format(axi_suffix), type_name='RVALID{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_alock{}'.format(axi_suffix), type_name='ALOCK{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_rready{}'.format(axi_suffix), type_name='RREADY{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_rresp{}'.format(axi_suffix), type_name='RRESP{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_wstrb{}'.format(axi_suffix), type_name='WSTRB{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_aready{}'.format(axi_suffix), type_name='AREADY{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_alen{}'.format(axi_suffix), type_name='ALEN{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target1, 'efxpt:pin', name='axi_clk', type_name='ACLK{}'.format(type_suffix), is_bus = 'false', is_clk = 'true', is_clk_invert = 'false')
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gen_pin_config = et.SubElement(ddr, 'efxpt:gen_pin_config')
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et.SubElement(gen_pin_config, 'efxpt:pin', name='', type_name='CFG_SEQ_RST', is_bus = 'false')
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et.SubElement(gen_pin_config, 'efxpt:pin', name='', type_name='CFG_SCL_IN', is_bus = 'false')
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et.SubElement(gen_pin_config, 'efxpt:pin', name='', type_name='CFG_SEQ_START', is_bus = 'false')
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@ -75,16 +104,16 @@ class InterfaceWriter():
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et.SubElement(gen_pin_config, 'efxpt:pin', name='', type_name='CFG_SDA_IN', is_bus = 'false')
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et.SubElement(gen_pin_config, 'efxpt:pin', name='', type_name='CFG_SDA_OEN', is_bus = 'false')
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cs_fpga = et.SubElement(ddr_info, 'efxpt:cs_fpga')
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cs_fpga = et.SubElement(ddr, 'efxpt:cs_fpga')
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et.SubElement(cs_fpga, 'efxpt:param', name='FPGA_ITERM', value='120', value_type = 'str')
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et.SubElement(cs_fpga, 'efxpt:param', name='FPGA_OTERM', value='34', value_type = 'str')
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cs_memory = et.SubElement(ddr_info, 'efxpt:cs_memory')
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cs_memory = et.SubElement(ddr, 'efxpt:cs_memory')
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et.SubElement(cs_memory, 'efxpt:param', name='RTT_NOM', value='RZQ/2', value_type = 'str')
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et.SubElement(cs_memory, 'efxpt:param', name='MEM_OTERM', value='40', value_type = 'str')
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et.SubElement(cs_memory, 'efxpt:param', name='CL', value='RL=6/WL=3', value_type = 'str')
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timing = et.SubElement(ddr_info, 'efxpt:cs_memory_timing')
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timing = et.SubElement(ddr, 'efxpt:cs_memory_timing')
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et.SubElement(timing, 'efxpt:param', name='tRAS', value= '42.000', value_type='float')
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et.SubElement(timing, 'efxpt:param', name='tRC', value= '60.000', value_type='float')
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et.SubElement(timing, 'efxpt:param', name='tRP', value= '18.000', value_type='float')
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@ -96,15 +125,15 @@ class InterfaceWriter():
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et.SubElement(timing, 'efxpt:param', name='tRRD', value= '10.000', value_type='float')
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et.SubElement(timing, 'efxpt:param', name='tFAW', value= '50.000', value_type='float')
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cs_control = et.SubElement(ddr_info, 'efxpt:cs_control')
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cs_control = et.SubElement(ddr, 'efxpt:cs_control')
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et.SubElement(cs_control, 'efxpt:param', name='AMAP', value= 'ROW-COL_HIGH-BANK-COL_LOW', value_type='str')
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et.SubElement(cs_control, 'efxpt:param', name='EN_AUTO_PWR_DN', value= 'Off', value_type='str')
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et.SubElement(cs_control, 'efxpt:param', name='EN_AUTO_SELF_REF', value= 'No', value_type='str')
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cs_gate_delay = et.SubElement(ddr_info, 'efxpt:cs_gate_delay')
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et.SubElement(cs_control, 'efxpt:param', name='EN_DLY_OVR', value= 'No', value_type='str')
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et.SubElement(cs_control, 'efxpt:param', name='GATE_C_DLY', value= '3', value_type='str')
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et.SubElement(cs_control, 'efxpt:param', name='GATE_F_DLY', value= '0', value_type='str')
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cs_gate_delay = et.SubElement(ddr, 'efxpt:cs_gate_delay')
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et.SubElement(cs_gate_delay, 'efxpt:param', name='EN_DLY_OVR', value= 'No', value_type='str')
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et.SubElement(cs_gate_delay, 'efxpt:param', name='GATE_C_DLY', value= '3', value_type='int')
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et.SubElement(cs_gate_delay, 'efxpt:param', name='GATE_F_DLY', value= '0', value_type='int')
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xml_string = et.tostring(root, 'utf-8')
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reparsed = expatbuilder.parseString(xml_string, False)
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@ -170,6 +199,9 @@ design.create('{2}', '{3}', './../build', overwrite=True)
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if i > 0:
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cmd += 'pll_config = {{ "CLKOUT{}_EN":"1", "CLKOUT{}_PIN":"{}" }}\n'.format(i, i, clock[0])
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cmd += 'design.set_property("{}", pll_config, block_type="PLL")\n\n'.format(name)
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else:
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cmd += 'pll_config = {{ "CLKOUT{}_PIN":"{}" }}\n'.format(i, clock[0])
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cmd += 'design.set_property("{}", pll_config, block_type="PLL")\n\n'.format(name)
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cmd += 'target_freq = {\n'
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for i, clock in enumerate(block['clk_out']):
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@ -201,7 +233,7 @@ design.create('{2}', '{3}', './../build', overwrite=True)
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def footer(self):
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return """
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# Check design, generate constraints and reports
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#design.generate(enable_bitstream=True)
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design.generate(enable_bitstream=True)
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# Save the configured periphery design
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design.save()"""
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