soc/software/bios/sdram: split memtest and allow external #define of memtest sizes
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619cd8e695
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@ -44,7 +44,9 @@ class BaseSoC(SoCSDRAM):
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self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings)
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self.register_sdram(self.sdrphy, "minicon",
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sdram_module.geom_settings, sdram_module.timing_settings)
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# reduce memtest size to speed up simulation
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self.add_constant("MEMTEST_DATA_SIZE", 8*1024)
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self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)
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def main():
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@ -423,15 +423,6 @@ int sdrlevel(void)
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#endif /* CSR_DDRPHY_BASE */
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#define TEST_DATA_SIZE (32*1024) // FIXME add #define
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#define TEST_DATA_RANDOM 1
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#define TEST_ADDR_SIZE (32*1024)
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#define TEST_ADDR_RANDOM 0
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#define ONEZERO 0xAAAAAAAA
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#define ZEROONE 0x55555555
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static unsigned int seed_to_data_32(unsigned int seed, int random)
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{
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if (random)
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@ -448,81 +439,123 @@ static unsigned short seed_to_data_16(unsigned short seed, int random)
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return seed + 1;
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}
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int memtest_silent(void)
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#define ONEZERO 0xAAAAAAAA
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#define ZEROONE 0x55555555
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#ifndef MEMTEST_BUS_SIZE
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#define MEMTEST_BUS_SIZE (512)
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#endif
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static int memtest_bus(void)
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{
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volatile unsigned int *array = (unsigned int *)MAIN_RAM_BASE;
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int i;
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unsigned int seed_32;
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unsigned short seed_16;
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unsigned int error_cnt;
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int i, errors;
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error_cnt = 0;
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errors = 0;
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/* test data bus */
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for(i=0;i<128;i++) {
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for(i=0;i<MEMTEST_BUS_SIZE/4;i++) {
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array[i] = ONEZERO;
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}
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flush_cpu_dcache();
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flush_l2_cache();
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for(i=0;i<128;i++) {
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for(i=0;i<MEMTEST_BUS_SIZE/4;i++) {
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if(array[i] != ONEZERO)
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error_cnt++;
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errors++;
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}
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for(i=0;i<128;i++) {
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for(i=0;i<MEMTEST_BUS_SIZE/4;i++) {
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array[i] = ZEROONE;
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}
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flush_cpu_dcache();
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flush_l2_cache();
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for(i=0;i<128;i++) {
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for(i=0;i<MEMTEST_BUS_SIZE/4;i++) {
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if(array[i] != ZEROONE)
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error_cnt++;
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errors++;
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}
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/* test counter or random data */
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return errors;
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}
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#ifndef MEMTEST_DATA_SIZE
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#define MEMTEST_DATA_SIZE (2*1024*1024)
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#endif
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#define MEMTEST_DATA_RANDOM 1
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static int memtest_data(void)
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{
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volatile unsigned int *array = (unsigned int *)MAIN_RAM_BASE;
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int i, errors;
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unsigned int seed_32;
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errors = 0;
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seed_32 = 0;
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for(i=0;i<TEST_DATA_SIZE/4;i++) {
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seed_32 = seed_to_data_32(seed_32, TEST_DATA_RANDOM);
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for(i=0;i<MEMTEST_DATA_SIZE/4;i++) {
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seed_32 = seed_to_data_32(seed_32, MEMTEST_DATA_RANDOM);
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array[i] = seed_32;
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}
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seed_32 = 0;
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flush_cpu_dcache();
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flush_l2_cache();
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for(i=0;i<TEST_DATA_SIZE/4;i++) {
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seed_32 = seed_to_data_32(seed_32, TEST_DATA_RANDOM);
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for(i=0;i<MEMTEST_DATA_SIZE/4;i++) {
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seed_32 = seed_to_data_32(seed_32, MEMTEST_DATA_RANDOM);
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if(array[i] != seed_32)
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error_cnt++;
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errors++;
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}
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/* test random addressing */
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return errors;
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}
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#ifndef MEMTEST_ADDR_SIZE
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#define MEMTEST_ADDR_SIZE (32*1024)
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#endif
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#define MEMTEST_ADDR_RANDOM 0
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static int memtest_addr(void)
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{
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volatile unsigned int *array = (unsigned int *)MAIN_RAM_BASE;
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int i, errors;
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unsigned short seed_16;
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errors = 0;
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seed_16 = 0;
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for(i=0;i<TEST_ADDR_SIZE/4;i++) {
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seed_16 = seed_to_data_16(seed_16, TEST_ADDR_RANDOM);
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for(i=0;i<MEMTEST_ADDR_SIZE/4;i++) {
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seed_16 = seed_to_data_16(seed_16, MEMTEST_ADDR_RANDOM);
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array[(unsigned int) seed_16] = i;
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}
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seed_16 = 0;
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flush_cpu_dcache();
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flush_l2_cache();
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for(i=0;i<TEST_ADDR_SIZE/4;i++) {
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seed_16 = seed_to_data_16(seed_16, TEST_ADDR_RANDOM);
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for(i=0;i<MEMTEST_ADDR_SIZE/4;i++) {
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seed_16 = seed_to_data_16(seed_16, MEMTEST_ADDR_RANDOM);
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if(array[(unsigned int) seed_16] != i)
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error_cnt++;
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errors++;
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}
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return error_cnt;
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return errors;
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}
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int memtest(void)
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{
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unsigned int e;
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int bus_errors, data_errors, addr_errors;
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e = memtest_silent();
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if(e != 0) {
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printf("Memtest failed: %d/%d words incorrect\n", e, 2*128 + TEST_DATA_SIZE/4 + TEST_ADDR_SIZE/4);
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bus_errors = memtest_bus();
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if(bus_errors != 0)
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printf("Memtest bus failed: %d/%d errors\n", bus_errors, 2*128);
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data_errors = memtest_data();
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if(bus_errors != 0)
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printf("Memtest data failed: %d/%d errors\n", data_errors, MEMTEST_DATA_SIZE/4);
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addr_errors = memtest_addr();
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if(addr_errors != 0)
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printf("Memtest addr failed: %d/%d errors\n", addr_errors, MEMTEST_ADDR_SIZE/4);
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if(bus_errors + data_errors + addr_errors != 0)
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return 0;
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} else {
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else {
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printf("Memtest OK\n");
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return 1;
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}
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