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litex_sim: load SPD data from files in hexdump format as printed in BIOS

This commit is contained in:
Jędrzej Boczar 2020-05-21 16:19:28 +02:00
parent a42dc97401
commit bdc7eb5c48
1 changed files with 4 additions and 4 deletions
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8
litex/tools/litex_sim.py
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@ -19,6 +19,7 @@ from litex.soc.integration.builder import *
from litex.soc.integration.soc import *
from litedram import modules as litedram_modules
from litedram.modules import parse_spd_hexdump
from litedram.common import *
from litedram.phy.model import SDRAMPHYModel
@ -298,7 +299,7 @@ def main():
parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip")
parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width")
parser.add_argument("--sdram-init", default=None, help="SDRAM init file")
parser.add_argument("--sdram-from-spd-data", default=None, help="Generate SDRAM module based on SPD data from file")
parser.add_argument("--sdram-from-spd-dump", default=None, help="Generate SDRAM module based on data from SPD EEPROM dump")
parser.add_argument("--sdram-verbosity", default=0, help="Set SDRAM checker verbosity")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
@ -337,9 +338,8 @@ def main():
soc_kwargs["sdram_module"] = args.sdram_module
soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
if args.sdram_from_spd_data:
with open(args.sdram_from_spd_data, "rb") as f:
soc_kwargs["sdram_spd_data"] = [int(b) for b in f.read()]
if args.sdram_from_spd_dump:
soc_kwargs["sdram_spd_data"] = parse_spd_hexdump(args.sdram_from_spd_dump)
if args.with_ethernet or args.with_etherbone:
sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": args.remote_ip})