soc/core/uart: add UartStub to enable fast simulation with cpu

litex/soc/cores/uart.py

@@ -185,6 +185,26 @@ class UART(Module, AutoCSR):
         ]
 
 
+class UARTStub(Module, AutoCSR):
+    def __init__(self):
+        self._rxtx = CSR(8)
+        self._txfull = CSRStatus()
+        self._rxempty = CSRStatus()
+
+        self.submodules.ev = EventManager()
+        self.ev.tx = EventSourceProcess()
+        self.ev.rx = EventSourceProcess()
+        self.ev.finalize()
+
+        # # #
+
+        self.comb += [
+            self._txfull.status.eq(0),
+            self.ev.tx.trigger.eq(~(self._rxtx.re & self._rxtx.r)),
+            self._rxempty.status.eq(1)
+        ]
+
+
 class UARTWishboneBridge(WishboneStreamingBridge):
     def __init__(self, pads, clk_freq, baudrate=115200):
         self.submodules.phy = RS232PHY(pads, clk_freq, baudrate)

litex/soc/integration/soc_core.py

@@ -41,7 +41,7 @@ class SoCCore(Module):
                 integrated_main_ram_size=0,
                 shadow_base=0x80000000,
                 csr_data_width=8, csr_address_width=14,
-                with_uart=True, uart_baudrate=115200,
+                with_uart=True, uart_baudrate=115200, uart_stub=False,
                 ident="",
                 with_timer=True):
         self.config = dict()
@@ -107,6 +107,9 @@ class SoCCore(Module):
         self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)
 
         if with_uart:
+            if uart_stub:
+                self.submodules.uart  = uart.UARTStub()
+            else:
                 self.submodules.uart_phy = uart.RS232PHY(platform.request("serial"), clk_freq, uart_baudrate)
                 self.submodules.uart = uart.UART(self.uart_phy)