cores/spi/spi_bone: More cosmetic cleanups.
This commit is contained in:
Florent Kermarrec
parent
0b05abb44f
commit
bdfb032be9
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@ -156,17 +156,21 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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miso = Signal()
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miso_en = Signal()
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# Clk (Resynchronize).
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self.specials += MultiReg(pads.clk, clk)
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# CSn (Resynchronize).
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if wires in [3, 4]:
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self.specials += MultiReg(pads.cs_n, cs_n)
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# MOSI/MISO (Resynchronize + Tristate)
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if wires in [2, 3]:
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io = TSTriple()
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self.specials += io.get_tristate(pads.mosi)
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self.specials += MultiReg(io.i, mosi)
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self.comb += io.o.eq(miso)
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self.comb += io.oe.eq(miso_en)
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if wires == 2:
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self.specials += MultiReg(pads.cs_n, cs_n)
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if wires in [4]:
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self.specials += MultiReg(pads.cs_n, cs_n)
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self.specials += MultiReg(pads.mosi, mosi)
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if with_tristate:
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self.specials += Tristate(pads.miso, miso, ~cs_n)
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@ -184,12 +188,12 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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# Signals.
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# --------
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counter = Signal(8)
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write_offset = Signal(5)
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count = Signal(8)
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offset = Signal(5)
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command = Signal(8)
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address = Signal(32)
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value = Signal(32)
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wr = Signal()
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write = Signal()
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sync_byte = Signal(8)
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# FSM.
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@ -206,8 +210,14 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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bus.sel.eq(2**len(bus.sel) - 1)
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]
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# Constantly have the counter increase, except when it's reset in the IDLE state.
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self.sync += If(cs_n, counter.eq(0)).Elif(clk_posedge, counter.eq(counter + 1))
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# Constantly have the count increase, except when it's reset in the IDLE state.
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self.sync += [
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If(cs_n,
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count.eq(0)
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).Elif(clk_posedge,
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count.eq(count + 1)
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)
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]
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if wires in [2]:
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fsm.act("IDLE",
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@ -218,8 +228,8 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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),
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If(sync_byte[0:7] == 0b101011,
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NextState("GET_TYPE_BYTE"),
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NextValue(counter, 0),
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NextValue(command, mosi),
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NextValue(count, 0),
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NextValue(command, mosi)
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)
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)
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if wires in [3, 4]:
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@ -228,7 +238,7 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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NextValue(miso, 1),
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If(clk_posedge,
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NextState("GET_TYPE_BYTE"),
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NextValue(command, mosi),
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NextValue(command, mosi)
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)
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)
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@ -236,47 +246,47 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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fsm.act("GET_TYPE_BYTE",
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miso_en.eq(0),
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NextValue(miso, 1),
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If(counter == 8,
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If(count == 8,
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# Write value
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If(command == 0,
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NextValue(wr, 1),
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NextState("READ_ADDRESS"),
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NextValue(write, 1),
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NextState("READ_ADDRESS")
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# Read value
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).Elif(command == 1,
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NextValue(wr, 0),
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NextState("READ_ADDRESS"),
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NextValue(write, 0),
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NextState("READ_ADDRESS")
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).Else(
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NextState("END"),
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NextState("END")
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),
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),
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If(clk_posedge,
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NextValue(command, Cat(mosi, command)),
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),
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NextValue(command, Cat(mosi, command))
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)
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)
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fsm.act("READ_ADDRESS",
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miso_en.eq(0),
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If(counter == 32 + 8,
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If(wr,
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If(count == (32 + 8),
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If(write,
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NextState("READ_VALUE"),
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).Else(
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NextState("READ_WISHBONE"),
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)
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),
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If(clk_posedge,
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NextValue(address, Cat(mosi, address)),
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),
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NextValue(address, Cat(mosi, address))
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)
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)
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fsm.act("READ_VALUE",
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miso_en.eq(0),
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If(counter == 32 + 32 + 8,
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If(count == (32 + 32 + 8),
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NextState("WRITE_WISHBONE"),
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),
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If(clk_posedge,
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NextValue(value, Cat(mosi, value)),
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),
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NextValue(value, Cat(mosi, value))
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)
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)
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fsm.act("WRITE_WISHBONE",
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@ -285,8 +295,8 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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bus.cyc.eq(1),
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miso_en.eq(1),
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If(bus.ack | bus.err,
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NextState("WAIT_BYTE_BOUNDARY"),
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),
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NextState("WAIT_BYTE_BOUNDARY")
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)
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)
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fsm.act("READ_WISHBONE",
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@ -296,58 +306,58 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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miso_en.eq(1),
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If(bus.ack | bus.err,
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NextState("WAIT_BYTE_BOUNDARY"),
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NextValue(value, bus.dat_r),
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),
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NextValue(value, bus.dat_r)
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)
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)
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fsm.act("WAIT_BYTE_BOUNDARY",
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miso_en.eq(1),
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If(clk_negedge,
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If(counter[0:3] == 0,
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If(count[0:3] == 0,
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NextValue(miso, 0),
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# For writes, fill in the 0 byte response
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If(wr,
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If(write,
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NextState("WRITE_WR_RESPONSE"),
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).Else(
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NextState("WRITE_RESPONSE"),
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),
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),
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),
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)
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)
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)
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)
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# Write the "01" byte that indicates a response
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fsm.act("WRITE_RESPONSE",
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miso_en.eq(1),
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If(clk_negedge,
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If(counter[0:3] == 0b111,
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If(count[0:3] == 0b111,
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NextValue(miso, 1),
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).Elif(counter[0:3] == 0,
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NextValue(write_offset, 31),
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).Elif(count[0:3] == 0,
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NextValue(offset, 31),
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NextState("WRITE_VALUE")
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),
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),
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)
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)
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)
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# Write the actual value
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fsm.act("WRITE_VALUE",
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miso_en.eq(1),
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NextValue(miso, value >> write_offset),
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NextValue(miso, value >> offset),
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If(clk_negedge,
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NextValue(write_offset, write_offset - 1),
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If(write_offset == 0,
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NextValue(offset, offset - 1),
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If(offset == 0,
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NextValue(miso, 0),
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NextState("END"),
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),
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),
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NextState("END")
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)
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)
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)
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fsm.act("WRITE_WR_RESPONSE",
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miso_en.eq(1),
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If(clk_negedge,
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If(counter[0:3] == 0,
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NextState("END"),
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),
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),
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If(count[0:3] == 0,
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NextState("END")
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)
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)
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)
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if wires in [2]:
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@ -358,5 +368,5 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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)
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if wires in [3, 4]:
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fsm.act("END",
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miso_en.eq(1),
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miso_en.eq(1)
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)
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