uptime: rework and integrate it in Timer to ease software support.

litex/soc/cores/timer.py

@@ -82,3 +82,13 @@ class Timer(Module, AutoCSR, ModuleDoc):
             If(self._update_value.re, self._value.status.eq(value))
         ]
         self.comb += self.ev.zero.trigger.eq(value != 0)
+
+    def add_uptime(self, width=64):
+        self._uptime_latch  = CSRStorage(description="Write a ``1`` to latch current Uptime cycles to ``uptime_cycles`` register.")
+        self._uptime_cycles = CSRStatus(width, description="Latched Uptime since power-up (in ``sys_clk`` cycles).")
+
+        # # #
+
+        uptime_cycles = Signal(width, reset_less=True)
+        self.sync += uptime_cycles.eq(uptime_cycles + 1)
+        self.sync += If(self._uptime_latch.re, self._uptime_cycles.status.eq(uptime_cycles))

litex/soc/integration/soc.py

@@ -614,8 +614,7 @@ class SoCController(Module, AutoCSR):
     def __init__(self,
         with_reset    = True,
         with_scratch  = True,
-        with_errors   = True,
-        with_uptime   = False):
+        with_errors   = True):
 
         if with_reset:
             self._reset = CSRStorage(1, description="""Write a ``1`` to this register to reset the SoC.""")
@@ -627,10 +626,6 @@ class SoCController(Module, AutoCSR):
         if with_errors:
             self._bus_errors = CSRStatus(32, description="Total number of Wishbone bus errors (timeouts) since start.")
 
-        if with_uptime:
-            self._uptime_latch = CSRStorage(description="Write a ``1`` to latch current Uptime to ``uptime`` register.")
-            self._uptime       = CSRStatus(64, description="Latched Uptime since power-up (in ``sys_clk`` cycles).")
-
         # # #
 
         # Reset
@@ -649,12 +644,6 @@ class SoCController(Module, AutoCSR):
             ]
             self.comb += self._bus_errors.status.eq(bus_errors)
 
-        # Uptime
-        if with_uptime:
-            uptime = Signal(64, reset_less=True)
-            self.sync += uptime.eq(uptime + 1)
-            self.sync += If(self._uptime_latch.re, self._uptime.status.eq(uptime))
-
 # SoC ----------------------------------------------------------------------------------------------
 
 class SoC(Module):

litex/soc/integration/soc_core.py

@@ -95,9 +95,9 @@ class SoCCore(LiteXSoC):
         uart_fifo_depth          = 16,
         # Timer parameters
         with_timer               = True,
+        timer_uptime             = False,
         # Controller parameters
         with_ctrl                = True,
-        ctrl_uptime              = False,
         # Others
         **kwargs):
 
@@ -147,7 +147,7 @@ class SoCCore(LiteXSoC):
 
         # Add SoCController
         if with_ctrl:
-            self.add_controller("ctrl", with_uptime=ctrl_uptime)
+            self.add_controller("ctrl")
 
         # Add CPU
         self.add_cpu(
@@ -183,6 +183,8 @@ class SoCCore(LiteXSoC):
         # Add Timer
         if with_timer:
             self.add_timer(name="timer0")
+            if timer_uptime:
+                self.timer0.add_uptime()
 
         # Add CSR bridge
         self.add_csr_bridge(self.mem_map["csr"])

litex/soc/software/bios/commands/cmd_bios.c

@@ -76,13 +76,13 @@ define_command(reboot, reboot, "Reboot the system", SYSTEM_CMDS);
  * Uptime of the system
  *
  */
-#ifdef CSR_CTRL_UPTIME_ADDR
+#ifdef CSR_TIMER0_UPTIME_CYCLES_ADDR
 static void uptime(int nb_params, char **params)
 {
 	unsigned long uptime;
 
-	ctrl_uptime_latch_write(1);
-	uptime = ctrl_uptime_read();
+	timer0_uptime_latch_write(1);
+	uptime = timer0_uptime_cycles_read();
 	printf("Uptime: %ld sys_clk cycles / %ld seconds",
 		uptime,
 		uptime/CONFIG_CLOCK_FREQUENCY