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soc_zynq: use zynq fabric reset as sys reset

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This commit is contained in:
Florent Kermarrec 2019-07-12 09:52:40 +02:00
parent 220f43753b
commit be280bed5e
1 changed files with 4 additions and 1 deletions
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5
litex/soc/integration/soc_zynq.py
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@ -32,6 +32,7 @@ class SoCZynq(SoCCore):
SoCCore.__init__(self, platform, clk_freq, cpu_type=None, shadow_base=0x00000000, **kwargs)
# PS7 (Minimal) ----------------------------------------------------------------------------
fclk_reset0_n = Signal()
ps7_ddram_pads = platform.request("ps7_ddram")
self.ps7_params = dict(
# clk/rst
@ -70,9 +71,11 @@ class SoCZynq(SoCCore):
# usb0
i_USB0_VBUS_PWRFAULT=0,
# fabric clk
# fabric clk/rst
o_FCLK_CLK0=ClockSignal("sys"),
o_FCLK_RESET0_N=fclk_reset0_n
)
self.comb += ResetSignal("sys").eq(~fclk_reset0_n)
platform.add_ip(os.path.join("ip", ps7_name + ".xci"))
# GP0 ------------------------------------------------------------------------------------------