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cpu/NaxRiscv: Now support reset from the jtag

This commit is contained in:
Dolu1990 2022-04-12 19:38:30 +02:00
parent 7416943f9c
commit be43ef6424
1 changed files with 25 additions and 2 deletions
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27
litex/soc/cores/cpu/naxriscv/core.py
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@ -229,8 +229,8 @@ class NaxRiscv(CPU):
ndir = os.path.join(vdir, "ext", "NaxRiscv")
sdir = os.path.join(vdir, "ext", "SpinalHDL")
NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "jtag", "d5777cfe")
NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "dev" , "f8f375e2")
NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "dev" , "d97112e1")
NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "dev" , "e1e5961d")
gen_args = []
gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}")
@ -350,6 +350,29 @@ class NaxRiscv(CPU):
o_jtag_instruction_tdo = self.jtag_tdo,
)
if NaxRiscv.jtag_instruction or NaxRiscv.jtag_tap:
# Create PoR Clk Domain for debug_reset.
self.clock_domains.cd_debug_por = ClockDomain()
self.comb += self.cd_debug_por.clk.eq(ClockSignal("sys"))
# Create PoR debug_reset.
debug_reset = Signal(reset=1)
self.sync.debug_por += debug_reset.eq(0)
# Debug resets.
debug_ndmreset = Signal()
debug_ndmreset_last = Signal()
debug_ndmreset_rise = Signal()
self.cpu_params.update(
i_debug_reset=debug_reset,
o_debug_ndmreset=debug_ndmreset,
)
# Reset SoC's CRG when debug_ndmreset rising edge.
self.sync.debug_por += debug_ndmreset_last.eq(debug_ndmreset)
self.comb += debug_ndmreset_rise.eq(debug_ndmreset & ~debug_ndmreset_last)
self.comb += If(debug_ndmreset_rise, soc.crg.rst.eq(1))
# Add CLINT Bus (Wishbone Slave).
self.clintbus = clintbus = axi.AXILiteInterface(address_width=32, data_width=32)
self.cpu_params.update(