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Merge pull request #918 from antmicro/jboc/sdram-leveling
Attempt to improve DRAM leveling robustness
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enjoy-digital
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commit
beac24b796
1 changed files with 79 additions and 27 deletions
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@ -27,6 +27,8 @@
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//#define SDRAM_TEST_DISABLE
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//#define SDRAM_WRITE_LEVELING_CMD_DELAY_DEBUG
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//#define SDRAM_WRITE_LATENCY_CALIBRATION_DEBUG
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//#define SDRAM_LEVELING_SCAN_DISPLAY_HEX_DIV 10
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#ifdef CSR_SDRAM_BASE
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@ -271,8 +273,37 @@ static void sdram_precharge_test_row(void) {
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cdelay(15);
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}
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static int sdram_write_read_check_test_pattern(int module, unsigned int seed) {
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// Count number of bits in a 32-bit word, faster version than a while loop
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// see: https://www.johndcook.com/blog/2020/02/21/popcount/
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static unsigned int popcount(unsigned int x) {
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x -= ((x >> 1) & 0x55555555);
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x = (x & 0x33333333) + ((x >> 2) & 0x33333333);
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x = (x + (x >> 4)) & 0x0F0F0F0F;
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x += (x >> 8);
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x += (x >> 16);
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return x & 0x0000003F;
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}
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static void print_scan_errors(unsigned int errors) {
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#ifdef SDRAM_LEVELING_SCAN_DISPLAY_HEX_DIV
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// Display '.' for no errors, errors/div in hex if it is a single char, else show 'X'
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errors = errors / SDRAM_LEVELING_SCAN_DISPLAY_HEX_DIV;
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if (errors == 0)
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printf(".");
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else if (errors > 0xf)
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printf("X");
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else
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printf("%x", errors);
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#else
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printf("%d", errors == 0);
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#endif
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}
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#define READ_CHECK_TEST_PATTERN_MAX_ERRORS (SDRAM_PHY_PHASES*2*32)
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static unsigned int sdram_write_read_check_test_pattern(int module, unsigned int seed) {
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int p, i;
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unsigned int errors;
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unsigned int prv;
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unsigned char tst[DFII_PIX_DATA_BYTES];
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unsigned char prs[SDRAM_PHY_PHASES][DFII_PIX_DATA_BYTES];
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@ -310,13 +341,13 @@ static int sdram_write_read_check_test_pattern(int module, unsigned int seed) {
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/* Precharge */
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sdram_precharge_test_row();
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errors = 0;
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for(p=0;p<SDRAM_PHY_PHASES;p++) {
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/* Read back test pattern */
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csr_rd_buf_uint8(sdram_dfii_pix_rddata_addr(p), tst, DFII_PIX_DATA_BYTES);
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/* Verify bytes matching current 'module' */
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if (prs[p][ SDRAM_PHY_MODULES-1-module] != tst[ SDRAM_PHY_MODULES-1-module] ||
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prs[p][2*SDRAM_PHY_MODULES-1-module] != tst[2*SDRAM_PHY_MODULES-1-module])
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return 0;
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errors += popcount(prs[p][ SDRAM_PHY_MODULES-1-module] ^ tst[ SDRAM_PHY_MODULES-1-module]);
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errors += popcount(prs[p][2*SDRAM_PHY_MODULES-1-module] ^ tst[2*SDRAM_PHY_MODULES-1-module]);
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}
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#ifdef SDRAM_PHY_ECP5DDRPHY
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@ -324,7 +355,7 @@ static int sdram_write_read_check_test_pattern(int module, unsigned int seed) {
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return 0;
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#endif
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return 1;
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return errors;
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}
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static void sdram_leveling_center_module(
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@ -333,6 +364,7 @@ static void sdram_leveling_center_module(
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int i;
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int show;
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int working;
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unsigned int errors;
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int delay, delay_mid, delay_range;
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int delay_min = -1, delay_max = -1;
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@ -343,14 +375,15 @@ static void sdram_leveling_center_module(
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delay = 0;
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rst_delay(module);
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while(1) {
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working = sdram_write_read_check_test_pattern(module, 42);
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working &= sdram_write_read_check_test_pattern(module, 84);
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errors = sdram_write_read_check_test_pattern(module, 42);
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errors += sdram_write_read_check_test_pattern(module, 84);
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working = errors == 0;
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show = show_long;
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#if SDRAM_PHY_DELAYS > 32
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show = show && (delay%16 == 0);
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#endif
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if (show)
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printf(working ? "1" : "0");
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print_scan_errors(errors);
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if(working && delay_min < 0) {
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delay_min = delay;
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break;
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@ -374,14 +407,15 @@ static void sdram_leveling_center_module(
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/* Find largest working delay */
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while(1) {
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working = sdram_write_read_check_test_pattern(module, 42);
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working &= sdram_write_read_check_test_pattern(module, 84);
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errors = sdram_write_read_check_test_pattern(module, 42);
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errors += sdram_write_read_check_test_pattern(module, 84);
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working = errors == 0;
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show = show_long;
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#if SDRAM_PHY_DELAYS > 32
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show = show && (delay%16 == 0);
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#endif
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if (show)
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printf(working ? "1" : "0");
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print_scan_errors(errors);
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if(!working && delay_max < 0) {
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delay_max = delay;
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}
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@ -873,15 +907,17 @@ static void sdram_read_leveling_inc_bitslip(char m)
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ddrphy_dly_sel_write(0);
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}
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static int sdram_read_leveling_scan_module(int module, int bitslip, int show)
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static unsigned int sdram_read_leveling_scan_module(int module, int bitslip, int show)
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{
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const unsigned int max_errors = 2*READ_CHECK_TEST_PATTERN_MAX_ERRORS;
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int i;
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int score;
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unsigned int score;
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unsigned int errors;
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/* Check test pattern for each delay value */
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/* Check test pattern for each delay value */
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score = 0;
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if (show)
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printf(" m%d, b%d: |", module, bitslip);
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printf(" m%d, b%02d: |", module, bitslip);
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sdram_read_leveling_rst_delay(module);
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for(i=0;i<SDRAM_PHY_DELAYS;i++) {
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int working;
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@ -889,11 +925,14 @@ static int sdram_read_leveling_scan_module(int module, int bitslip, int show)
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#if SDRAM_PHY_DELAYS > 32
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_show = (i%16 == 0) & show;
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#endif
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working = sdram_write_read_check_test_pattern(module, 42);
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working &= sdram_write_read_check_test_pattern(module, 84);
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if (_show)
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printf("%d", working);
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score += working;
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errors = sdram_write_read_check_test_pattern(module, 42);
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errors += sdram_write_read_check_test_pattern(module, 84);
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working = errors == 0;
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/* When any scan is working then the final score will always be higher then if no scan was working */
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score += (working * max_errors*SDRAM_PHY_DELAYS) + (max_errors - errors);
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if (_show) {
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print_scan_errors(errors);
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}
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sdram_read_leveling_inc_delay(module);
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}
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if (show)
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@ -914,8 +953,8 @@ void sdram_read_leveling(void)
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{
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int module;
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int bitslip;
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int score;
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int best_score;
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unsigned int score;
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unsigned int best_score;
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int best_bitslip;
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for(module=0; module<SDRAM_PHY_MODULES; module++) {
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@ -963,8 +1002,9 @@ static void sdram_write_latency_calibration(void) {
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int i;
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int module;
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int bitslip;
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int score;
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int best_score;
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unsigned int score;
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unsigned int subscore;
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unsigned int best_score;
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int best_bitslip;
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for(module=0; module<SDRAM_PHY_MODULES; module++) {
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@ -972,6 +1012,9 @@ static void sdram_write_latency_calibration(void) {
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best_score = 0;
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best_bitslip = -1;
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for(bitslip=0; bitslip<SDRAM_PHY_BITSLIPS; bitslip+=2) { /* +2 for tCK steps */
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#ifdef SDRAM_WRITE_LATENCY_CALIBRATION_DEBUG
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printf("m%d wb%02d:\n", module, bitslip);
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#endif
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score = 0;
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/* Select module */
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ddrphy_dly_sel_write(1 << module);
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@ -986,7 +1029,13 @@ static void sdram_write_latency_calibration(void) {
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sdram_read_leveling_rst_bitslip(module);
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for(i=0; i<SDRAM_PHY_BITSLIPS; i++) {
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/* Compute score */
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score += sdram_read_leveling_scan_module(module, i, 0);
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#ifdef SDRAM_WRITE_LATENCY_CALIBRATION_DEBUG
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subscore = sdram_read_leveling_scan_module(module, i, 1);
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printf("\n");
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#else
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subscore = sdram_read_leveling_scan_module(module, i, 0);
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#endif
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score = subscore > score ? subscore : score;
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/* Increment bitslip */
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sdram_read_leveling_inc_bitslip(module);
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}
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@ -1004,6 +1053,9 @@ static void sdram_write_latency_calibration(void) {
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printf("m%d:- ", module);
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else
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printf("m%d:%d ", module, bitslip);
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#ifdef SDRAM_WRITE_LATENCY_CALIBRATION_DEBUG
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printf("\n");
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#endif
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/* Select best write window */
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ddrphy_dly_sel_write(1 << module);
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@ -1061,10 +1113,10 @@ static void sdram_write_dq_dqs_training_inc_delay(int module) {
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static void sdram_read_leveling_best_bitslip(int module)
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{
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int score;
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unsigned int score;
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int bitslip;
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int best_bitslip = 0;
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int best_score = 0;
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unsigned int best_score = 0;
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sdram_read_leveling_rst_bitslip(module);
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for(bitslip=0; bitslip<SDRAM_PHY_BITSLIPS; bitslip++) {
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