utils/litex_read_verilog: fix generated indent on instance
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1fe7d09fb5
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beeca856e5
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@ -38,17 +38,17 @@ def main():
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length = "" if len(info["bits"]) == 1 else len(info["bits"])
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length = "" if len(info["bits"]) == 1 else len(info["bits"])
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migen_def.append(" " * 8 + "self.{} = Signal({})".format(name, length))
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migen_def.append(" " * 8 + "self.{} = Signal({})".format(name, length))
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migen_def.append("")
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migen_def.append("")
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migen_def.append(" "*4 + "# # #")
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migen_def.append(" "*8 + "# # #")
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migen_def.append("")
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migen_def.append("")
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migen_def.append(" "*4 + "self.specials += Instance(\"{}\",".format(module))
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migen_def.append(" "*8 + "self.specials += Instance(\"{}\",".format(module))
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for name, info in j["modules"][module]["ports"].items():
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for name, info in j["modules"][module]["ports"].items():
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io_prefix = {
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io_prefix = {
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"input": "i",
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"input": "i",
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"output": "o",
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"output": "o",
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"inout": "io"
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"inout": "io"
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}[info["direction"]]
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}[info["direction"]]
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migen_def.append(" "*8 + "{}_{}=self.{},".format(io_prefix, name, name))
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migen_def.append(" "*12 + "{}_{}=self.{},".format(io_prefix, name, name))
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migen_def.append(" "*4 + ")")
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migen_def.append(" "*8 + ")")
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migen_def.append("")
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migen_def.append("")
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print("\n".join(migen_def))
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print("\n".join(migen_def))
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