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utils/litex_read_verilog: fix generated indent on instance

This commit is contained in:
Florent Kermarrec 2018-11-22 17:33:46 +01:00
parent 1fe7d09fb5
commit beeca856e5
1 changed files with 4 additions and 4 deletions
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8
litex/utils/litex_read_verilog.py
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@ -38,17 +38,17 @@ def main():
length = "" if len(info["bits"]) == 1 else len(info["bits"])
migen_def.append(" " * 8 + "self.{} = Signal({})".format(name, length))
migen_def.append("")
migen_def.append(" "*4 + "# # #")
migen_def.append(" "*8 + "# # #")
migen_def.append("")
migen_def.append(" "*4 + "self.specials += Instance(\"{}\",".format(module))
migen_def.append(" "*8 + "self.specials += Instance(\"{}\",".format(module))
for name, info in j["modules"][module]["ports"].items():
io_prefix = {
"input": "i",
"output": "o",
"inout": "io"
}[info["direction"]]
migen_def.append(" "*8 + "{}_{}=self.{},".format(io_prefix, name, name))
migen_def.append(" "*4 + ")")
migen_def.append(" "*12 + "{}_{}=self.{},".format(io_prefix, name, name))
migen_def.append(" "*8 + ")")
migen_def.append("")
print("\n".join(migen_def))