gen: integrate migen changes

litex/gen/fhdl/verilog.py

@@ -377,8 +377,8 @@ def convert(f, ios=None, name="top",
     f = lower_complex_slices(f)
     insert_resets(f)
     f = lower_basics(f)
-    fs, lowered_specials = lower_specials(special_overrides, f.specials)
-    f += lower_basics(fs)
+    f, lowered_specials = lower_specials(special_overrides, f)
+    f = lower_basics(f)
 
     for io in sorted(ios, key=lambda x: x.duid):
         if io.name_override is None:

litex/gen/sim/core.py

@@ -250,9 +250,7 @@ class Simulator:
 
         overrides = {AsyncResetSynchronizer: DummyAsyncResetSynchronizer}
         overrides.update(special_overrides)
-        fs, lowered = lower_specials(overrides=overrides, specials=self.fragment.specials)
-        self.fragment += fs
-        self.fragment.specials -= lowered
+        f, lowered = lower_specials(overrides, self.fragment)
         if self.fragment.specials:
             raise ValueError("Could not lower all specials", self.fragment.specials)